drivers/irqchip/irq-csky-apb-intc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
0003
0004 #include <linux/kernel.h>
0005 #include <linux/init.h>
0006 #include <linux/of.h>
0007 #include <linux/of_address.h>
0008 #include <linux/module.h>
0009 #include <linux/irqdomain.h>
0010 #include <linux/irqchip.h>
0011 #include <linux/irq.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/io.h>
0014 #include <asm/irq.h>
0015
0016 #define INTC_IRQS       64
0017
0018 #define CK_INTC_ICR     0x00
0019 #define CK_INTC_PEN31_00    0x14
0020 #define CK_INTC_PEN63_32    0x2c
0021 #define CK_INTC_NEN31_00    0x10
0022 #define CK_INTC_NEN63_32    0x28
0023 #define CK_INTC_SOURCE      0x40
0024 #define CK_INTC_DUAL_BASE   0x100
0025
0026 #define GX_INTC_PEN31_00    0x00
0027 #define GX_INTC_PEN63_32    0x04
0028 #define GX_INTC_NEN31_00    0x40
0029 #define GX_INTC_NEN63_32    0x44
0030 #define GX_INTC_NMASK31_00  0x50
0031 #define GX_INTC_NMASK63_32  0x54
0032 #define GX_INTC_SOURCE      0x60
0033
0034 static void __iomem *reg_base;
0035 static struct irq_domain *root_domain;
0036
0037 static int nr_irq = INTC_IRQS;
0038
0039 /*
0040  * When controller support pulse signal, the PEN_reg will hold on signal
0041  * without software trigger.
0042  *
0043  * So, to support pulse signal we need to clear IFR_reg and the address of
0044  * IFR_offset is NEN_offset - 8.
0045  */
0046 static void irq_ck_mask_set_bit(struct irq_data *d)
0047 {
0048     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0049     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0050     unsigned long ifr = ct->regs.mask - 8;
0051     u32 mask = d->mask;
0052
0053     irq_gc_lock(gc);
0054     *ct->mask_cache |= mask;
0055     irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
0056     irq_reg_writel(gc, irq_reg_readl(gc, ifr) & ~mask, ifr);
0057     irq_gc_unlock(gc);
0058 }
0059
0060 static void __init ck_set_gc(struct device_node *node, void __iomem *reg_base,
0061                  u32 mask_reg, u32 irq_base)
0062 {
0063     struct irq_chip_generic *gc;
0064
0065     gc = irq_get_domain_generic_chip(root_domain, irq_base);
0066     gc->reg_base = reg_base;
0067     gc->chip_types[0].regs.mask = mask_reg;
0068     gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
0069     gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
0070
0071     if (of_find_property(node, "csky,support-pulse-signal", NULL))
0072         gc->chip_types[0].chip.irq_unmask = irq_ck_mask_set_bit;
0073 }
0074
0075 static inline u32 build_channel_val(u32 idx, u32 magic)
0076 {
0077     u32 res;
0078
0079     /*
0080      * Set the same index for each channel
0081      */
0082     res = idx | (idx << 8) | (idx << 16) | (idx << 24);
0083
0084     /*
0085      * Set the channel magic number in descending order.
0086      * The magic is 0x00010203 for ck-intc
0087      * The magic is 0x03020100 for gx6605s-intc
0088      */
0089     return res | magic;
0090 }
0091
0092 static inline void setup_irq_channel(u32 magic, void __iomem *reg_addr)
0093 {
0094     u32 i;
0095
0096     /* Setup 64 channel slots */
0097     for (i = 0; i < INTC_IRQS; i += 4)
0098         writel(build_channel_val(i, magic), reg_addr + i);
0099 }
0100
0101 static int __init
0102 ck_intc_init_comm(struct device_node *node, struct device_node *parent)
0103 {
0104     int ret;
0105
0106     if (parent) {
0107         pr_err("C-SKY Intc not a root irq controller\n");
0108         return -EINVAL;
0109     }
0110
0111     reg_base = of_iomap(node, 0);
0112     if (!reg_base) {
0113         pr_err("C-SKY Intc unable to map: %p.\n", node);
0114         return -EINVAL;
0115     }
0116
0117     root_domain = irq_domain_add_linear(node, nr_irq,
0118                         &irq_generic_chip_ops, NULL);
0119     if (!root_domain) {
0120         pr_err("C-SKY Intc irq_domain_add failed.\n");
0121         return -ENOMEM;
0122     }
0123
0124     ret = irq_alloc_domain_generic_chips(root_domain, 32, 1,
0125             "csky_intc", handle_level_irq,
0126             IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, 0, 0);
0127     if (ret) {
0128         pr_err("C-SKY Intc irq_alloc_gc failed.\n");
0129         return -ENOMEM;
0130     }
0131
0132     return 0;
0133 }
0134
0135 static inline bool handle_irq_perbit(struct pt_regs *regs, u32 hwirq,
0136                      u32 irq_base)
0137 {
0138     if (hwirq == 0)
0139         return false;
0140
0141     generic_handle_domain_irq(root_domain, irq_base + __fls(hwirq));
0142
0143     return true;
0144 }
0145
0146 /* gx6605s 64 irqs interrupt controller */
0147 static void gx_irq_handler(struct pt_regs *regs)
0148 {
0149     bool ret;
0150
0151 retry:
0152     ret = handle_irq_perbit(regs,
0153             readl(reg_base + GX_INTC_PEN63_32), 32);
0154     if (ret)
0155         goto retry;
0156
0157     ret = handle_irq_perbit(regs,
0158             readl(reg_base + GX_INTC_PEN31_00), 0);
0159     if (ret)
0160         goto retry;
0161 }
0162
0163 static int __init
0164 gx_intc_init(struct device_node *node, struct device_node *parent)
0165 {
0166     int ret;
0167
0168     ret = ck_intc_init_comm(node, parent);
0169     if (ret)
0170         return ret;
0171
0172     /*
0173      * Initial enable reg to disable all interrupts
0174      */
0175     writel(0x0, reg_base + GX_INTC_NEN31_00);
0176     writel(0x0, reg_base + GX_INTC_NEN63_32);
0177
0178     /*
0179      * Initial mask reg with all unmasked, because we only use enable reg
0180      */
0181     writel(0x0, reg_base + GX_INTC_NMASK31_00);
0182     writel(0x0, reg_base + GX_INTC_NMASK63_32);
0183
0184     setup_irq_channel(0x03020100, reg_base + GX_INTC_SOURCE);
0185
0186     ck_set_gc(node, reg_base, GX_INTC_NEN31_00, 0);
0187     ck_set_gc(node, reg_base, GX_INTC_NEN63_32, 32);
0188
0189     set_handle_irq(gx_irq_handler);
0190
0191     return 0;
0192 }
0193 IRQCHIP_DECLARE(csky_gx6605s_intc, "csky,gx6605s-intc", gx_intc_init);
0194
0195 /*
0196  * C-SKY simple 64 irqs interrupt controller, dual-together could support 128
0197  * irqs.
0198  */
0199 static void ck_irq_handler(struct pt_regs *regs)
0200 {
0201     bool ret;
0202     void __iomem *reg_pen_lo = reg_base + CK_INTC_PEN31_00;
0203     void __iomem *reg_pen_hi = reg_base + CK_INTC_PEN63_32;
0204
0205 retry:
0206     /* handle 0 - 63 irqs */
0207     ret = handle_irq_perbit(regs, readl(reg_pen_hi), 32);
0208     if (ret)
0209         goto retry;
0210
0211     ret = handle_irq_perbit(regs, readl(reg_pen_lo), 0);
0212     if (ret)
0213         goto retry;
0214
0215     if (nr_irq == INTC_IRQS)
0216         return;
0217
0218     /* handle 64 - 127 irqs */
0219     ret = handle_irq_perbit(regs,
0220             readl(reg_pen_hi + CK_INTC_DUAL_BASE), 96);
0221     if (ret)
0222         goto retry;
0223
0224     ret = handle_irq_perbit(regs,
0225             readl(reg_pen_lo + CK_INTC_DUAL_BASE), 64);
0226     if (ret)
0227         goto retry;
0228 }
0229
0230 static int __init
0231 ck_intc_init(struct device_node *node, struct device_node *parent)
0232 {
0233     int ret;
0234
0235     ret = ck_intc_init_comm(node, parent);
0236     if (ret)
0237         return ret;
0238
0239     /* Initial enable reg to disable all interrupts */
0240     writel(0, reg_base + CK_INTC_NEN31_00);
0241     writel(0, reg_base + CK_INTC_NEN63_32);
0242
0243     /* Enable irq intc */
0244     writel(BIT(31), reg_base + CK_INTC_ICR);
0245
0246     ck_set_gc(node, reg_base, CK_INTC_NEN31_00, 0);
0247     ck_set_gc(node, reg_base, CK_INTC_NEN63_32, 32);
0248
0249     setup_irq_channel(0x00010203, reg_base + CK_INTC_SOURCE);
0250
0251     set_handle_irq(ck_irq_handler);
0252
0253     return 0;
0254 }
0255 IRQCHIP_DECLARE(ck_intc, "csky,apb-intc", ck_intc_init);
0256
0257 static int __init
0258 ck_dual_intc_init(struct device_node *node, struct device_node *parent)
0259 {
0260     int ret;
0261
0262     /* dual-apb-intc up to 128 irq sources*/
0263     nr_irq = INTC_IRQS * 2;
0264
0265     ret = ck_intc_init(node, parent);
0266     if (ret)
0267         return ret;
0268
0269     /* Initial enable reg to disable all interrupts */
0270     writel(0, reg_base + CK_INTC_NEN31_00 + CK_INTC_DUAL_BASE);
0271     writel(0, reg_base + CK_INTC_NEN63_32 + CK_INTC_DUAL_BASE);
0272
0273     ck_set_gc(node, reg_base + CK_INTC_DUAL_BASE, CK_INTC_NEN31_00, 64);
0274     ck_set_gc(node, reg_base + CK_INTC_DUAL_BASE, CK_INTC_NEN63_32, 96);
0275
0276     setup_irq_channel(0x00010203,
0277               reg_base + CK_INTC_SOURCE + CK_INTC_DUAL_BASE);
0278
0279     return 0;
0280 }
0281 IRQCHIP_DECLARE(ck_dual_intc, "csky,dual-apb-intc", ck_dual_intc_init);