drivers/irqchip/irq-bcm7120-l2.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Broadcom BCM7120 style Level 2 interrupt controller driver
0004  *
0005  * Copyright (C) 2014 Broadcom Corporation
0006  */
0007
0008 #define pr_fmt(fmt) KBUILD_MODNAME  ": " fmt
0009
0010 #include <linux/init.h>
0011 #include <linux/slab.h>
0012 #include <linux/module.h>
0013 #include <linux/kernel.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/of.h>
0016 #include <linux/of_irq.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_platform.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/irq.h>
0021 #include <linux/io.h>
0022 #include <linux/irqdomain.h>
0023 #include <linux/reboot.h>
0024 #include <linux/bitops.h>
0025 #include <linux/irqchip.h>
0026 #include <linux/irqchip/chained_irq.h>
0027
0028 /* Register offset in the L2 interrupt controller */
0029 #define IRQEN       0x00
0030 #define IRQSTAT     0x04
0031
0032 #define MAX_WORDS   4
0033 #define MAX_MAPPINGS    (MAX_WORDS * 2)
0034 #define IRQS_PER_WORD   32
0035
0036 struct bcm7120_l1_intc_data {
0037     struct bcm7120_l2_intc_data *b;
0038     u32 irq_map_mask[MAX_WORDS];
0039 };
0040
0041 struct bcm7120_l2_intc_data {
0042     unsigned int n_words;
0043     void __iomem *map_base[MAX_MAPPINGS];
0044     void __iomem *pair_base[MAX_WORDS];
0045     int en_offset[MAX_WORDS];
0046     int stat_offset[MAX_WORDS];
0047     struct irq_domain *domain;
0048     bool can_wake;
0049     u32 irq_fwd_mask[MAX_WORDS];
0050     struct bcm7120_l1_intc_data *l1_data;
0051     int num_parent_irqs;
0052     const __be32 *map_mask_prop;
0053 };
0054
0055 static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
0056 {
0057     struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
0058     struct bcm7120_l2_intc_data *b = data->b;
0059     struct irq_chip *chip = irq_desc_get_chip(desc);
0060     unsigned int idx;
0061
0062     chained_irq_enter(chip, desc);
0063
0064     for (idx = 0; idx < b->n_words; idx++) {
0065         int base = idx * IRQS_PER_WORD;
0066         struct irq_chip_generic *gc =
0067             irq_get_domain_generic_chip(b->domain, base);
0068         unsigned long pending;
0069         int hwirq;
0070
0071         irq_gc_lock(gc);
0072         pending = irq_reg_readl(gc, b->stat_offset[idx]) &
0073                         gc->mask_cache &
0074                         data->irq_map_mask[idx];
0075         irq_gc_unlock(gc);
0076
0077         for_each_set_bit(hwirq, &pending, IRQS_PER_WORD)
0078             generic_handle_domain_irq(b->domain, base + hwirq);
0079     }
0080
0081     chained_irq_exit(chip, desc);
0082 }
0083
0084 static void bcm7120_l2_intc_suspend(struct irq_chip_generic *gc)
0085 {
0086     struct bcm7120_l2_intc_data *b = gc->private;
0087     struct irq_chip_type *ct = gc->chip_types;
0088
0089     irq_gc_lock(gc);
0090     if (b->can_wake)
0091         irq_reg_writel(gc, gc->mask_cache | gc->wake_active,
0092                    ct->regs.mask);
0093     irq_gc_unlock(gc);
0094 }
0095
0096 static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc)
0097 {
0098     struct irq_chip_type *ct = gc->chip_types;
0099
0100     /* Restore the saved mask */
0101     irq_gc_lock(gc);
0102     irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
0103     irq_gc_unlock(gc);
0104 }
0105
0106 static int bcm7120_l2_intc_init_one(struct device_node *dn,
0107                     struct bcm7120_l2_intc_data *data,
0108                     int irq, u32 *valid_mask)
0109 {
0110     struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
0111     int parent_irq;
0112     unsigned int idx;
0113
0114     parent_irq = irq_of_parse_and_map(dn, irq);
0115     if (!parent_irq) {
0116         pr_err("failed to map interrupt %d\n", irq);
0117         return -EINVAL;
0118     }
0119
0120     /* For multiple parent IRQs with multiple words, this looks like:
0121      * <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
0122      *
0123      * We need to associate a given parent interrupt with its corresponding
0124      * map_mask in order to mask the status register with it because we
0125      * have the same handler being called for multiple parent interrupts.
0126      *
0127      * This is typically something needed on BCM7xxx (STB chips).
0128      */
0129     for (idx = 0; idx < data->n_words; idx++) {
0130         if (data->map_mask_prop) {
0131             l1_data->irq_map_mask[idx] |=
0132                 be32_to_cpup(data->map_mask_prop +
0133                          irq * data->n_words + idx);
0134         } else {
0135             l1_data->irq_map_mask[idx] = 0xffffffff;
0136         }
0137         valid_mask[idx] |= l1_data->irq_map_mask[idx];
0138     }
0139
0140     l1_data->b = data;
0141
0142     irq_set_chained_handler_and_data(parent_irq,
0143                      bcm7120_l2_intc_irq_handle, l1_data);
0144     if (data->can_wake)
0145         enable_irq_wake(parent_irq);
0146
0147     return 0;
0148 }
0149
0150 static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
0151                          struct bcm7120_l2_intc_data *data)
0152 {
0153     int ret;
0154
0155     data->map_base[0] = of_iomap(dn, 0);
0156     if (!data->map_base[0]) {
0157         pr_err("unable to map registers\n");
0158         return -ENOMEM;
0159     }
0160
0161     data->pair_base[0] = data->map_base[0];
0162     data->en_offset[0] = IRQEN;
0163     data->stat_offset[0] = IRQSTAT;
0164     data->n_words = 1;
0165
0166     ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
0167                      data->irq_fwd_mask, data->n_words);
0168     if (ret != 0 && ret != -EINVAL) {
0169         /* property exists but has the wrong number of words */
0170         pr_err("invalid brcm,int-fwd-mask property\n");
0171         return -EINVAL;
0172     }
0173
0174     data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
0175     if (!data->map_mask_prop ||
0176         (ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
0177         pr_err("invalid brcm,int-map-mask property\n");
0178         return -EINVAL;
0179     }
0180
0181     return 0;
0182 }
0183
0184 static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
0185                          struct bcm7120_l2_intc_data *data)
0186 {
0187     unsigned int gc_idx;
0188
0189     for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
0190         unsigned int map_idx = gc_idx * 2;
0191         void __iomem *en = of_iomap(dn, map_idx + 0);
0192         void __iomem *stat = of_iomap(dn, map_idx + 1);
0193         void __iomem *base = min(en, stat);
0194
0195         data->map_base[map_idx + 0] = en;
0196         data->map_base[map_idx + 1] = stat;
0197
0198         if (!base)
0199             break;
0200
0201         data->pair_base[gc_idx] = base;
0202         data->en_offset[gc_idx] = en - base;
0203         data->stat_offset[gc_idx] = stat - base;
0204     }
0205
0206     if (!gc_idx) {
0207         pr_err("unable to map registers\n");
0208         return -EINVAL;
0209     }
0210
0211     data->n_words = gc_idx;
0212     return 0;
0213 }
0214
0215 static int __init bcm7120_l2_intc_probe(struct device_node *dn,
0216                  struct device_node *parent,
0217                  int (*iomap_regs_fn)(struct device_node *,
0218                     struct bcm7120_l2_intc_data *),
0219                  const char *intc_name)
0220 {
0221     unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
0222     struct bcm7120_l2_intc_data *data;
0223     struct platform_device *pdev;
0224     struct irq_chip_generic *gc;
0225     struct irq_chip_type *ct;
0226     int ret = 0;
0227     unsigned int idx, irq, flags;
0228     u32 valid_mask[MAX_WORDS] = { };
0229
0230     data = kzalloc(sizeof(*data), GFP_KERNEL);
0231     if (!data)
0232         return -ENOMEM;
0233
0234     pdev = of_find_device_by_node(dn);
0235     if (!pdev) {
0236         ret = -ENODEV;
0237         goto out_free_data;
0238     }
0239
0240     data->num_parent_irqs = platform_irq_count(pdev);
0241     put_device(&pdev->dev);
0242     if (data->num_parent_irqs <= 0) {
0243         pr_err("invalid number of parent interrupts\n");
0244         ret = -ENOMEM;
0245         goto out_unmap;
0246     }
0247
0248     data->l1_data = kcalloc(data->num_parent_irqs, sizeof(*data->l1_data),
0249                 GFP_KERNEL);
0250     if (!data->l1_data) {
0251         ret = -ENOMEM;
0252         goto out_free_l1_data;
0253     }
0254
0255     ret = iomap_regs_fn(dn, data);
0256     if (ret < 0)
0257         goto out_free_l1_data;
0258
0259     data->can_wake = of_property_read_bool(dn, "brcm,irq-can-wake");
0260
0261     for (irq = 0; irq < data->num_parent_irqs; irq++) {
0262         ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
0263         if (ret)
0264             goto out_free_l1_data;
0265     }
0266
0267     data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
0268                          &irq_generic_chip_ops, NULL);
0269     if (!data->domain) {
0270         ret = -ENOMEM;
0271         goto out_free_l1_data;
0272     }
0273
0274     /* MIPS chips strapped for BE will automagically configure the
0275      * peripheral registers for CPU-native byte order.
0276      */
0277     flags = IRQ_GC_INIT_MASK_CACHE;
0278     if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
0279         flags |= IRQ_GC_BE_IO;
0280
0281     ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
0282                 dn->full_name, handle_level_irq, clr, 0, flags);
0283     if (ret) {
0284         pr_err("failed to allocate generic irq chip\n");
0285         goto out_free_domain;
0286     }
0287
0288     for (idx = 0; idx < data->n_words; idx++) {
0289         irq = idx * IRQS_PER_WORD;
0290         gc = irq_get_domain_generic_chip(data->domain, irq);
0291
0292         gc->unused = 0xffffffff & ~valid_mask[idx];
0293         gc->private = data;
0294         ct = gc->chip_types;
0295
0296         gc->reg_base = data->pair_base[idx];
0297         ct->regs.mask = data->en_offset[idx];
0298
0299         /* gc->reg_base is defined and so is gc->writel */
0300         irq_reg_writel(gc, data->irq_fwd_mask[idx],
0301                    data->en_offset[idx]);
0302
0303         ct->chip.irq_mask = irq_gc_mask_clr_bit;
0304         ct->chip.irq_unmask = irq_gc_mask_set_bit;
0305         ct->chip.irq_ack = irq_gc_noop;
0306         gc->suspend = bcm7120_l2_intc_suspend;
0307         gc->resume = bcm7120_l2_intc_resume;
0308
0309         /*
0310          * Initialize mask-cache, in case we need it for
0311          * saving/restoring fwd mask even w/o any child interrupts
0312          * installed
0313          */
0314         gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);
0315
0316         if (data->can_wake) {
0317             /* This IRQ chip can wake the system, set all
0318              * relevant child interrupts in wake_enabled mask
0319              */
0320             gc->wake_enabled = 0xffffffff;
0321             gc->wake_enabled &= ~gc->unused;
0322             ct->chip.irq_set_wake = irq_gc_set_wake;
0323         }
0324     }
0325
0326     pr_info("registered %s intc (%pOF, parent IRQ(s): %d)\n",
0327         intc_name, dn, data->num_parent_irqs);
0328
0329     return 0;
0330
0331 out_free_domain:
0332     irq_domain_remove(data->domain);
0333 out_free_l1_data:
0334     kfree(data->l1_data);
0335 out_unmap:
0336     for (idx = 0; idx < MAX_MAPPINGS; idx++) {
0337         if (data->map_base[idx])
0338             iounmap(data->map_base[idx]);
0339     }
0340 out_free_data:
0341     kfree(data);
0342     return ret;
0343 }
0344
0345 static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
0346                          struct device_node *parent)
0347 {
0348     return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
0349                      "BCM7120 L2");
0350 }
0351
0352 static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
0353                          struct device_node *parent)
0354 {
0355     return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
0356                      "BCM3380 L2");
0357 }
0358
0359 IRQCHIP_PLATFORM_DRIVER_BEGIN(bcm7120_l2)
0360 IRQCHIP_MATCH("brcm,bcm7120-l2-intc", bcm7120_l2_intc_probe_7120)
0361 IRQCHIP_MATCH("brcm,bcm3380-l2-intc", bcm7120_l2_intc_probe_3380)
0362 IRQCHIP_PLATFORM_DRIVER_END(bcm7120_l2)
0363 MODULE_DESCRIPTION("Broadcom STB 7120-style L2 interrupt controller driver");
0364 MODULE_LICENSE("GPL v2");