drivers/irqchip/irq-bcm2835.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright 2010 Broadcom
0004  * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
0005  *
0006  * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
0007  *
0008  * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
0009  * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
0010  * to look in the bank 1 status register for more information.
0011  *
0012  * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
0013  * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
0014  * status register, but bank 0 bit 8 is _not_ set.
0015  *
0016  * Quirk 2: You can't mask the register 1/2 pending interrupts
0017  *
0018  * In a proper cascaded interrupt controller, the interrupt lines with
0019  * cascaded interrupt controllers on them are just normal interrupt lines.
0020  * You can mask the interrupts and get on with things. With this controller
0021  * you can't do that.
0022  *
0023  * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
0024  *
0025  * Those interrupts that have shortcuts can only be masked/unmasked in
0026  * their respective banks' enable/disable registers. Doing so in the bank 0
0027  * enable/disable registers has no effect.
0028  *
0029  * The FIQ control register:
0030  *  Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
0031  *  Bit    7: Enable FIQ generation
0032  *  Bits  8+: Unused
0033  *
0034  * An interrupt must be disabled before configuring it for FIQ generation
0035  * otherwise both handlers will fire at the same time!
0036  */
0037
0038 #include <linux/io.h>
0039 #include <linux/slab.h>
0040 #include <linux/of_address.h>
0041 #include <linux/of_irq.h>
0042 #include <linux/irqchip.h>
0043 #include <linux/irqdomain.h>
0044
0045 #include <asm/exception.h>
0046
0047 /* Put the bank and irq (32 bits) into the hwirq */
0048 #define MAKE_HWIRQ(b, n)    ((b << 5) | (n))
0049 #define HWIRQ_BANK(i)       (i >> 5)
0050 #define HWIRQ_BIT(i)        BIT(i & 0x1f)
0051
0052 #define NR_IRQS_BANK0       8
0053 #define BANK0_HWIRQ_MASK    0xff
0054 /* Shortcuts can't be disabled so any unknown new ones need to be masked */
0055 #define SHORTCUT1_MASK      0x00007c00
0056 #define SHORTCUT2_MASK      0x001f8000
0057 #define SHORTCUT_SHIFT      10
0058 #define BANK1_HWIRQ     BIT(8)
0059 #define BANK2_HWIRQ     BIT(9)
0060 #define BANK0_VALID_MASK    (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
0061                     | SHORTCUT1_MASK | SHORTCUT2_MASK)
0062
0063 #define REG_FIQ_CONTROL     0x0c
0064 #define FIQ_CONTROL_ENABLE  BIT(7)
0065
0066 #define NR_BANKS        3
0067 #define IRQS_PER_BANK       32
0068
0069 static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
0070 static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
0071 static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
0072 static const int bank_irqs[] __initconst = { 8, 32, 32 };
0073
0074 static const int shortcuts[] = {
0075     7, 9, 10, 18, 19,       /* Bank 1 */
0076     21, 22, 23, 24, 25, 30      /* Bank 2 */
0077 };
0078
0079 struct armctrl_ic {
0080     void __iomem *base;
0081     void __iomem *pending[NR_BANKS];
0082     void __iomem *enable[NR_BANKS];
0083     void __iomem *disable[NR_BANKS];
0084     struct irq_domain *domain;
0085 };
0086
0087 static struct armctrl_ic intc __read_mostly;
0088 static void __exception_irq_entry bcm2835_handle_irq(
0089     struct pt_regs *regs);
0090 static void bcm2836_chained_handle_irq(struct irq_desc *desc);
0091
0092 static void armctrl_mask_irq(struct irq_data *d)
0093 {
0094     writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
0095 }
0096
0097 static void armctrl_unmask_irq(struct irq_data *d)
0098 {
0099     writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
0100 }
0101
0102 static struct irq_chip armctrl_chip = {
0103     .name = "ARMCTRL-level",
0104     .irq_mask = armctrl_mask_irq,
0105     .irq_unmask = armctrl_unmask_irq
0106 };
0107
0108 static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
0109     const u32 *intspec, unsigned int intsize,
0110     unsigned long *out_hwirq, unsigned int *out_type)
0111 {
0112     if (WARN_ON(intsize != 2))
0113         return -EINVAL;
0114
0115     if (WARN_ON(intspec[0] >= NR_BANKS))
0116         return -EINVAL;
0117
0118     if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
0119         return -EINVAL;
0120
0121     if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
0122         return -EINVAL;
0123
0124     *out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
0125     *out_type = IRQ_TYPE_NONE;
0126     return 0;
0127 }
0128
0129 static const struct irq_domain_ops armctrl_ops = {
0130     .xlate = armctrl_xlate
0131 };
0132
0133 static int __init armctrl_of_init(struct device_node *node,
0134                   struct device_node *parent,
0135                   bool is_2836)
0136 {
0137     void __iomem *base;
0138     int irq, b, i;
0139     u32 reg;
0140
0141     base = of_iomap(node, 0);
0142     if (!base)
0143         panic("%pOF: unable to map IC registers\n", node);
0144
0145     intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
0146             &armctrl_ops, NULL);
0147     if (!intc.domain)
0148         panic("%pOF: unable to create IRQ domain\n", node);
0149
0150     for (b = 0; b < NR_BANKS; b++) {
0151         intc.pending[b] = base + reg_pending[b];
0152         intc.enable[b] = base + reg_enable[b];
0153         intc.disable[b] = base + reg_disable[b];
0154
0155         for (i = 0; i < bank_irqs[b]; i++) {
0156             irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
0157             BUG_ON(irq <= 0);
0158             irq_set_chip_and_handler(irq, &armctrl_chip,
0159                 handle_level_irq);
0160             irq_set_probe(irq);
0161         }
0162
0163         reg = readl_relaxed(intc.enable[b]);
0164         if (reg) {
0165             writel_relaxed(reg, intc.disable[b]);
0166             pr_err(FW_BUG "Bootloader left irq enabled: "
0167                    "bank %d irq %*pbl\n", b, IRQS_PER_BANK, &reg);
0168         }
0169     }
0170
0171     reg = readl_relaxed(base + REG_FIQ_CONTROL);
0172     if (reg & FIQ_CONTROL_ENABLE) {
0173         writel_relaxed(0, base + REG_FIQ_CONTROL);
0174         pr_err(FW_BUG "Bootloader left fiq enabled\n");
0175     }
0176
0177     if (is_2836) {
0178         int parent_irq = irq_of_parse_and_map(node, 0);
0179
0180         if (!parent_irq) {
0181             panic("%pOF: unable to get parent interrupt.\n",
0182                   node);
0183         }
0184         irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
0185     } else {
0186         set_handle_irq(bcm2835_handle_irq);
0187     }
0188
0189     return 0;
0190 }
0191
0192 static int __init bcm2835_armctrl_of_init(struct device_node *node,
0193                       struct device_node *parent)
0194 {
0195     return armctrl_of_init(node, parent, false);
0196 }
0197
0198 static int __init bcm2836_armctrl_of_init(struct device_node *node,
0199                       struct device_node *parent)
0200 {
0201     return armctrl_of_init(node, parent, true);
0202 }
0203
0204
0205 /*
0206  * Handle each interrupt across the entire interrupt controller.  This reads the
0207  * status register before handling each interrupt, which is necessary given that
0208  * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
0209  */
0210
0211 static u32 armctrl_translate_bank(int bank)
0212 {
0213     u32 stat = readl_relaxed(intc.pending[bank]);
0214
0215     return MAKE_HWIRQ(bank, ffs(stat) - 1);
0216 }
0217
0218 static u32 armctrl_translate_shortcut(int bank, u32 stat)
0219 {
0220     return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
0221 }
0222
0223 static u32 get_next_armctrl_hwirq(void)
0224 {
0225     u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;
0226
0227     if (stat == 0)
0228         return ~0;
0229     else if (stat & BANK0_HWIRQ_MASK)
0230         return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
0231     else if (stat & SHORTCUT1_MASK)
0232         return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
0233     else if (stat & SHORTCUT2_MASK)
0234         return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
0235     else if (stat & BANK1_HWIRQ)
0236         return armctrl_translate_bank(1);
0237     else if (stat & BANK2_HWIRQ)
0238         return armctrl_translate_bank(2);
0239     else
0240         BUG();
0241 }
0242
0243 static void __exception_irq_entry bcm2835_handle_irq(
0244     struct pt_regs *regs)
0245 {
0246     u32 hwirq;
0247
0248     while ((hwirq = get_next_armctrl_hwirq()) != ~0)
0249         generic_handle_domain_irq(intc.domain, hwirq);
0250 }
0251
0252 static void bcm2836_chained_handle_irq(struct irq_desc *desc)
0253 {
0254     u32 hwirq;
0255
0256     while ((hwirq = get_next_armctrl_hwirq()) != ~0)
0257         generic_handle_domain_irq(intc.domain, hwirq);
0258 }
0259
0260 IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
0261         bcm2835_armctrl_of_init);
0262 IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
0263         bcm2836_armctrl_of_init);