drivers/irqchip/irq-ath79-misc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Atheros AR71xx/AR724x/AR913x MISC interrupt controller
0004  *
0005  *  Copyright (C) 2015 Alban Bedel <albeu@free.fr>
0006  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
0007  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
0008  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
0009  *
0010  *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
0011  */
0012
0013 #include <linux/irqchip.h>
0014 #include <linux/irqchip/chained_irq.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of_irq.h>
0017
0018 #define AR71XX_RESET_REG_MISC_INT_STATUS    0
0019 #define AR71XX_RESET_REG_MISC_INT_ENABLE    4
0020
0021 #define ATH79_MISC_IRQ_COUNT            32
0022 #define ATH79_MISC_PERF_IRQ         5
0023
0024 static int ath79_perfcount_irq;
0025
0026 int get_c0_perfcount_int(void)
0027 {
0028     return ath79_perfcount_irq;
0029 }
0030 EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
0031
0032 static void ath79_misc_irq_handler(struct irq_desc *desc)
0033 {
0034     struct irq_domain *domain = irq_desc_get_handler_data(desc);
0035     struct irq_chip *chip = irq_desc_get_chip(desc);
0036     void __iomem *base = domain->host_data;
0037     u32 pending;
0038
0039     chained_irq_enter(chip, desc);
0040
0041     pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
0042           __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
0043
0044     if (!pending) {
0045         spurious_interrupt();
0046         chained_irq_exit(chip, desc);
0047         return;
0048     }
0049
0050     while (pending) {
0051         int bit = __ffs(pending);
0052
0053         generic_handle_domain_irq(domain, bit);
0054         pending &= ~BIT(bit);
0055     }
0056
0057     chained_irq_exit(chip, desc);
0058 }
0059
0060 static void ar71xx_misc_irq_unmask(struct irq_data *d)
0061 {
0062     void __iomem *base = irq_data_get_irq_chip_data(d);
0063     unsigned int irq = d->hwirq;
0064     u32 t;
0065
0066     t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
0067     __raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
0068
0069     /* flush write */
0070     __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
0071 }
0072
0073 static void ar71xx_misc_irq_mask(struct irq_data *d)
0074 {
0075     void __iomem *base = irq_data_get_irq_chip_data(d);
0076     unsigned int irq = d->hwirq;
0077     u32 t;
0078
0079     t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
0080     __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
0081
0082     /* flush write */
0083     __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
0084 }
0085
0086 static void ar724x_misc_irq_ack(struct irq_data *d)
0087 {
0088     void __iomem *base = irq_data_get_irq_chip_data(d);
0089     unsigned int irq = d->hwirq;
0090     u32 t;
0091
0092     t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
0093     __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
0094
0095     /* flush write */
0096     __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
0097 }
0098
0099 static struct irq_chip ath79_misc_irq_chip = {
0100     .name       = "MISC",
0101     .irq_unmask = ar71xx_misc_irq_unmask,
0102     .irq_mask   = ar71xx_misc_irq_mask,
0103 };
0104
0105 static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
0106 {
0107     irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);
0108     irq_set_chip_data(irq, d->host_data);
0109     return 0;
0110 }
0111
0112 static const struct irq_domain_ops misc_irq_domain_ops = {
0113     .xlate = irq_domain_xlate_onecell,
0114     .map = misc_map,
0115 };
0116
0117 static void __init ath79_misc_intc_domain_init(
0118     struct irq_domain *domain, int irq)
0119 {
0120     void __iomem *base = domain->host_data;
0121
0122     ath79_perfcount_irq = irq_create_mapping(domain, ATH79_MISC_PERF_IRQ);
0123
0124     /* Disable and clear all interrupts */
0125     __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
0126     __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
0127
0128     irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain);
0129 }
0130
0131 static int __init ath79_misc_intc_of_init(
0132     struct device_node *node, struct device_node *parent)
0133 {
0134     struct irq_domain *domain;
0135     void __iomem *base;
0136     int irq;
0137
0138     irq = irq_of_parse_and_map(node, 0);
0139     if (!irq) {
0140         pr_err("Failed to get MISC IRQ\n");
0141         return -EINVAL;
0142     }
0143
0144     base = of_iomap(node, 0);
0145     if (!base) {
0146         pr_err("Failed to get MISC IRQ registers\n");
0147         return -ENOMEM;
0148     }
0149
0150     domain = irq_domain_add_linear(node, ATH79_MISC_IRQ_COUNT,
0151                 &misc_irq_domain_ops, base);
0152     if (!domain) {
0153         pr_err("Failed to add MISC irqdomain\n");
0154         return -EINVAL;
0155     }
0156
0157     ath79_misc_intc_domain_init(domain, irq);
0158     return 0;
0159 }
0160
0161 static int __init ar7100_misc_intc_of_init(
0162     struct device_node *node, struct device_node *parent)
0163 {
0164     ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
0165     return ath79_misc_intc_of_init(node, parent);
0166 }
0167
0168 IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
0169         ar7100_misc_intc_of_init);
0170
0171 static int __init ar7240_misc_intc_of_init(
0172     struct device_node *node, struct device_node *parent)
0173 {
0174     ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
0175     return ath79_misc_intc_of_init(node, parent);
0176 }
0177
0178 IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
0179         ar7240_misc_intc_of_init);
0180
0181 void __init ath79_misc_irq_init(void __iomem *regs, int irq,
0182                 int irq_base, bool is_ar71xx)
0183 {
0184     struct irq_domain *domain;
0185
0186     if (is_ar71xx)
0187         ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
0188     else
0189         ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
0190
0191     domain = irq_domain_add_legacy(NULL, ATH79_MISC_IRQ_COUNT,
0192             irq_base, 0, &misc_irq_domain_ops, regs);
0193     if (!domain)
0194         panic("Failed to create MISC irqdomain");
0195
0196     ath79_misc_intc_domain_init(domain, irq);
0197 }