drivers/irqchip/irq-ath79-cpu.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Atheros AR71xx/AR724x/AR913x specific interrupt handling
0004  *
0005  *  Copyright (C) 2015 Alban Bedel <albeu@free.fr>
0006  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
0007  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
0008  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
0009  *
0010  *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
0011  */
0012
0013 #include <linux/interrupt.h>
0014 #include <linux/irqchip.h>
0015 #include <linux/of.h>
0016
0017 #include <asm/irq_cpu.h>
0018 #include <asm/mach-ath79/ath79.h>
0019
0020 /*
0021  * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
0022  * these devices typically allocate coherent DMA memory, however the
0023  * DMA controller may still have some unsynchronized data in the FIFO.
0024  * Issue a flush in the handlers to ensure that the driver sees
0025  * the update.
0026  *
0027  * This array map the interrupt lines to the DDR write buffer channels.
0028  */
0029
0030 static unsigned irq_wb_chan[8] = {
0031     -1, -1, -1, -1, -1, -1, -1, -1,
0032 };
0033
0034 asmlinkage void plat_irq_dispatch(void)
0035 {
0036     unsigned long pending;
0037     int irq;
0038
0039     pending = read_c0_status() & read_c0_cause() & ST0_IM;
0040
0041     if (!pending) {
0042         spurious_interrupt();
0043         return;
0044     }
0045
0046     pending >>= CAUSEB_IP;
0047     while (pending) {
0048         irq = fls(pending) - 1;
0049         if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1)
0050             ath79_ddr_wb_flush(irq_wb_chan[irq]);
0051         do_IRQ(MIPS_CPU_IRQ_BASE + irq);
0052         pending &= ~BIT(irq);
0053     }
0054 }
0055
0056 static int __init ar79_cpu_intc_of_init(
0057     struct device_node *node, struct device_node *parent)
0058 {
0059     int err, i, count;
0060
0061     /* Fill the irq_wb_chan table */
0062     count = of_count_phandle_with_args(
0063         node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");
0064
0065     for (i = 0; i < count; i++) {
0066         struct of_phandle_args args;
0067         u32 irq = i;
0068
0069         of_property_read_u32_index(
0070             node, "qca,ddr-wb-channel-interrupts", i, &irq);
0071         if (irq >= ARRAY_SIZE(irq_wb_chan))
0072             continue;
0073
0074         err = of_parse_phandle_with_args(
0075             node, "qca,ddr-wb-channels",
0076             "#qca,ddr-wb-channel-cells",
0077             i, &args);
0078         if (err)
0079             return err;
0080
0081         irq_wb_chan[irq] = args.args[0];
0082     }
0083
0084     return mips_cpu_irq_of_init(node, parent);
0085 }
0086 IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
0087         ar79_cpu_intc_of_init);
0088
0089 void __init ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3)
0090 {
0091     irq_wb_chan[2] = irq_wb_chan2;
0092     irq_wb_chan[3] = irq_wb_chan3;
0093     mips_cpu_irq_init();
0094 }