drivers/irqchip/irq-aspeed-vic.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp.
0004  *
0005  *  Driver for Aspeed "new" VIC as found in SoC generation 3 and later
0006  *
0007  *  Based on irq-vic.c:
0008  *
0009  *  Copyright (C) 1999 - 2003 ARM Limited
0010  *  Copyright (C) 2000 Deep Blue Solutions Ltd
0011  */
0012
0013 #include <linux/export.h>
0014 #include <linux/init.h>
0015 #include <linux/list.h>
0016 #include <linux/io.h>
0017 #include <linux/irq.h>
0018 #include <linux/irqchip.h>
0019 #include <linux/irqchip/chained_irq.h>
0020 #include <linux/irqdomain.h>
0021 #include <linux/of.h>
0022 #include <linux/of_address.h>
0023 #include <linux/of_irq.h>
0024 #include <linux/syscore_ops.h>
0025 #include <linux/device.h>
0026 #include <linux/slab.h>
0027
0028 #include <asm/exception.h>
0029 #include <asm/irq.h>
0030
0031 /* These definitions correspond to the "new mapping" of the
0032  * register set that interleaves "high" and "low". The offsets
0033  * below are for the "low" register, add 4 to get to the high one
0034  */
0035 #define AVIC_IRQ_STATUS     0x00
0036 #define AVIC_FIQ_STATUS     0x08
0037 #define AVIC_RAW_STATUS     0x10
0038 #define AVIC_INT_SELECT     0x18
0039 #define AVIC_INT_ENABLE     0x20
0040 #define AVIC_INT_ENABLE_CLR 0x28
0041 #define AVIC_INT_TRIGGER    0x30
0042 #define AVIC_INT_TRIGGER_CLR    0x38
0043 #define AVIC_INT_SENSE      0x40
0044 #define AVIC_INT_DUAL_EDGE  0x48
0045 #define AVIC_INT_EVENT      0x50
0046 #define AVIC_EDGE_CLR       0x58
0047 #define AVIC_EDGE_STATUS    0x60
0048
0049 #define NUM_IRQS        64
0050
0051 struct aspeed_vic {
0052     void __iomem        *base;
0053     u32         edge_sources[2];
0054     struct irq_domain   *dom;
0055 };
0056 static struct aspeed_vic *system_avic;
0057
0058 static void vic_init_hw(struct aspeed_vic *vic)
0059 {
0060     u32 sense;
0061
0062     /* Disable all interrupts */
0063     writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR);
0064     writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4);
0065
0066     /* Make sure no soft trigger is on */
0067     writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR);
0068     writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4);
0069
0070     /* Set everything to be IRQ */
0071     writel(0, vic->base + AVIC_INT_SELECT);
0072     writel(0, vic->base + AVIC_INT_SELECT + 4);
0073
0074     /* Some interrupts have a programmable high/low level trigger
0075      * (4 GPIO direct inputs), for now we assume this was configured
0076      * by firmware. We read which ones are edge now.
0077      */
0078     sense = readl(vic->base + AVIC_INT_SENSE);
0079     vic->edge_sources[0] = ~sense;
0080     sense = readl(vic->base + AVIC_INT_SENSE + 4);
0081     vic->edge_sources[1] = ~sense;
0082
0083     /* Clear edge detection latches */
0084     writel(0xffffffff, vic->base + AVIC_EDGE_CLR);
0085     writel(0xffffffff, vic->base + AVIC_EDGE_CLR + 4);
0086 }
0087
0088 static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
0089 {
0090     struct aspeed_vic *vic = system_avic;
0091     u32 stat, irq;
0092
0093     for (;;) {
0094         irq = 0;
0095         stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS);
0096         if (!stat) {
0097             stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS + 4);
0098             irq = 32;
0099         }
0100         if (stat == 0)
0101             break;
0102         irq += ffs(stat) - 1;
0103         generic_handle_domain_irq(vic->dom, irq);
0104     }
0105 }
0106
0107 static void avic_ack_irq(struct irq_data *d)
0108 {
0109     struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
0110     unsigned int sidx = d->hwirq >> 5;
0111     unsigned int sbit = 1u << (d->hwirq & 0x1f);
0112
0113     /* Clear edge latch for edge interrupts, nop for level */
0114     if (vic->edge_sources[sidx] & sbit)
0115         writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
0116 }
0117
0118 static void avic_mask_irq(struct irq_data *d)
0119 {
0120     struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
0121     unsigned int sidx = d->hwirq >> 5;
0122     unsigned int sbit = 1u << (d->hwirq & 0x1f);
0123
0124     writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
0125 }
0126
0127 static void avic_unmask_irq(struct irq_data *d)
0128 {
0129     struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
0130     unsigned int sidx = d->hwirq >> 5;
0131     unsigned int sbit = 1u << (d->hwirq & 0x1f);
0132
0133     writel(sbit, vic->base + AVIC_INT_ENABLE + sidx * 4);
0134 }
0135
0136 /* For level irq, faster than going through a nop "ack" and mask */
0137 static void avic_mask_ack_irq(struct irq_data *d)
0138 {
0139     struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
0140     unsigned int sidx = d->hwirq >> 5;
0141     unsigned int sbit = 1u << (d->hwirq & 0x1f);
0142
0143     /* First mask */
0144     writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
0145
0146     /* Then clear edge latch for edge interrupts */
0147     if (vic->edge_sources[sidx] & sbit)
0148         writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
0149 }
0150
0151 static struct irq_chip avic_chip = {
0152     .name       = "AVIC",
0153     .irq_ack    = avic_ack_irq,
0154     .irq_mask   = avic_mask_irq,
0155     .irq_unmask = avic_unmask_irq,
0156     .irq_mask_ack   = avic_mask_ack_irq,
0157 };
0158
0159 static int avic_map(struct irq_domain *d, unsigned int irq,
0160             irq_hw_number_t hwirq)
0161 {
0162     struct aspeed_vic *vic = d->host_data;
0163     unsigned int sidx = hwirq >> 5;
0164     unsigned int sbit = 1u << (hwirq & 0x1f);
0165
0166     /* Check if interrupt exists */
0167     if (sidx > 1)
0168         return -EPERM;
0169
0170     if (vic->edge_sources[sidx] & sbit)
0171         irq_set_chip_and_handler(irq, &avic_chip, handle_edge_irq);
0172     else
0173         irq_set_chip_and_handler(irq, &avic_chip, handle_level_irq);
0174     irq_set_chip_data(irq, vic);
0175     irq_set_probe(irq);
0176     return 0;
0177 }
0178
0179 static const struct irq_domain_ops avic_dom_ops = {
0180     .map = avic_map,
0181     .xlate = irq_domain_xlate_onetwocell,
0182 };
0183
0184 static int __init avic_of_init(struct device_node *node,
0185                    struct device_node *parent)
0186 {
0187     void __iomem *regs;
0188     struct aspeed_vic *vic;
0189
0190     if (WARN(parent, "non-root Aspeed VIC not supported"))
0191         return -EINVAL;
0192     if (WARN(system_avic, "duplicate Aspeed VIC not supported"))
0193         return -EINVAL;
0194
0195     regs = of_iomap(node, 0);
0196     if (WARN_ON(!regs))
0197         return -EIO;
0198
0199     vic = kzalloc(sizeof(struct aspeed_vic), GFP_KERNEL);
0200     if (WARN_ON(!vic)) {
0201         iounmap(regs);
0202         return -ENOMEM;
0203     }
0204     vic->base = regs;
0205
0206     /* Initialize sources, all masked */
0207     vic_init_hw(vic);
0208
0209     /* Ready to receive interrupts */
0210     system_avic = vic;
0211     set_handle_irq(avic_handle_irq);
0212
0213     /* Register our domain */
0214     vic->dom = irq_domain_add_simple(node, NUM_IRQS, 0,
0215                      &avic_dom_ops, vic);
0216
0217     return 0;
0218 }
0219
0220 IRQCHIP_DECLARE(ast2400_vic, "aspeed,ast2400-vic", avic_of_init);
0221 IRQCHIP_DECLARE(ast2500_vic, "aspeed,ast2500-vic", avic_of_init);