drivers/irqchip/irq-aspeed-scu-ic.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Aspeed AST24XX, AST25XX, and AST26XX SCU Interrupt Controller
0004  * Copyright 2019 IBM Corporation
0005  *
0006  * Eddie James <eajames@linux.ibm.com>
0007  */
0008
0009 #include <linux/bitops.h>
0010 #include <linux/irq.h>
0011 #include <linux/irqchip.h>
0012 #include <linux/irqchip/chained_irq.h>
0013 #include <linux/irqdomain.h>
0014 #include <linux/mfd/syscon.h>
0015 #include <linux/of_irq.h>
0016 #include <linux/regmap.h>
0017
0018 #define ASPEED_SCU_IC_REG       0x018
0019 #define ASPEED_SCU_IC_SHIFT     0
0020 #define ASPEED_SCU_IC_ENABLE        GENMASK(6, ASPEED_SCU_IC_SHIFT)
0021 #define ASPEED_SCU_IC_NUM_IRQS      7
0022 #define ASPEED_SCU_IC_STATUS_SHIFT  16
0023
0024 #define ASPEED_AST2600_SCU_IC0_REG  0x560
0025 #define ASPEED_AST2600_SCU_IC0_SHIFT    0
0026 #define ASPEED_AST2600_SCU_IC0_ENABLE   \
0027     GENMASK(5, ASPEED_AST2600_SCU_IC0_SHIFT)
0028 #define ASPEED_AST2600_SCU_IC0_NUM_IRQS 6
0029
0030 #define ASPEED_AST2600_SCU_IC1_REG  0x570
0031 #define ASPEED_AST2600_SCU_IC1_SHIFT    4
0032 #define ASPEED_AST2600_SCU_IC1_ENABLE   \
0033     GENMASK(5, ASPEED_AST2600_SCU_IC1_SHIFT)
0034 #define ASPEED_AST2600_SCU_IC1_NUM_IRQS 2
0035
0036 struct aspeed_scu_ic {
0037     unsigned long irq_enable;
0038     unsigned long irq_shift;
0039     unsigned int num_irqs;
0040     unsigned int reg;
0041     struct regmap *scu;
0042     struct irq_domain *irq_domain;
0043 };
0044
0045 static void aspeed_scu_ic_irq_handler(struct irq_desc *desc)
0046 {
0047     unsigned int sts;
0048     unsigned long bit;
0049     unsigned long enabled;
0050     unsigned long max;
0051     unsigned long status;
0052     struct aspeed_scu_ic *scu_ic = irq_desc_get_handler_data(desc);
0053     struct irq_chip *chip = irq_desc_get_chip(desc);
0054     unsigned int mask = scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT;
0055
0056     chained_irq_enter(chip, desc);
0057
0058     /*
0059      * The SCU IC has just one register to control its operation and read
0060      * status. The interrupt enable bits occupy the lower 16 bits of the
0061      * register, while the interrupt status bits occupy the upper 16 bits.
0062      * The status bit for a given interrupt is always 16 bits shifted from
0063      * the enable bit for the same interrupt.
0064      * Therefore, perform the IRQ operations in the enable bit space by
0065      * shifting the status down to get the mapping and then back up to
0066      * clear the bit.
0067      */
0068     regmap_read(scu_ic->scu, scu_ic->reg, &sts);
0069     enabled = sts & scu_ic->irq_enable;
0070     status = (sts >> ASPEED_SCU_IC_STATUS_SHIFT) & enabled;
0071
0072     bit = scu_ic->irq_shift;
0073     max = scu_ic->num_irqs + bit;
0074
0075     for_each_set_bit_from(bit, &status, max) {
0076         generic_handle_domain_irq(scu_ic->irq_domain,
0077                       bit - scu_ic->irq_shift);
0078
0079         regmap_write_bits(scu_ic->scu, scu_ic->reg, mask,
0080                   BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT));
0081     }
0082
0083     chained_irq_exit(chip, desc);
0084 }
0085
0086 static void aspeed_scu_ic_irq_mask(struct irq_data *data)
0087 {
0088     struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data);
0089     unsigned int mask = BIT(data->hwirq + scu_ic->irq_shift) |
0090         (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);
0091
0092     /*
0093      * Status bits are cleared by writing 1. In order to prevent the mask
0094      * operation from clearing the status bits, they should be under the
0095      * mask and written with 0.
0096      */
0097     regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, 0);
0098 }
0099
0100 static void aspeed_scu_ic_irq_unmask(struct irq_data *data)
0101 {
0102     struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data);
0103     unsigned int bit = BIT(data->hwirq + scu_ic->irq_shift);
0104     unsigned int mask = bit |
0105         (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);
0106
0107     /*
0108      * Status bits are cleared by writing 1. In order to prevent the unmask
0109      * operation from clearing the status bits, they should be under the
0110      * mask and written with 0.
0111      */
0112     regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, bit);
0113 }
0114
0115 static int aspeed_scu_ic_irq_set_affinity(struct irq_data *data,
0116                       const struct cpumask *dest,
0117                       bool force)
0118 {
0119     return -EINVAL;
0120 }
0121
0122 static struct irq_chip aspeed_scu_ic_chip = {
0123     .name           = "aspeed-scu-ic",
0124     .irq_mask       = aspeed_scu_ic_irq_mask,
0125     .irq_unmask     = aspeed_scu_ic_irq_unmask,
0126     .irq_set_affinity   = aspeed_scu_ic_irq_set_affinity,
0127 };
0128
0129 static int aspeed_scu_ic_map(struct irq_domain *domain, unsigned int irq,
0130                  irq_hw_number_t hwirq)
0131 {
0132     irq_set_chip_and_handler(irq, &aspeed_scu_ic_chip, handle_level_irq);
0133     irq_set_chip_data(irq, domain->host_data);
0134
0135     return 0;
0136 }
0137
0138 static const struct irq_domain_ops aspeed_scu_ic_domain_ops = {
0139     .map = aspeed_scu_ic_map,
0140 };
0141
0142 static int aspeed_scu_ic_of_init_common(struct aspeed_scu_ic *scu_ic,
0143                     struct device_node *node)
0144 {
0145     int irq;
0146     int rc = 0;
0147
0148     if (!node->parent) {
0149         rc = -ENODEV;
0150         goto err;
0151     }
0152
0153     scu_ic->scu = syscon_node_to_regmap(node->parent);
0154     if (IS_ERR(scu_ic->scu)) {
0155         rc = PTR_ERR(scu_ic->scu);
0156         goto err;
0157     }
0158
0159     irq = irq_of_parse_and_map(node, 0);
0160     if (!irq) {
0161         rc = -EINVAL;
0162         goto err;
0163     }
0164
0165     scu_ic->irq_domain = irq_domain_add_linear(node, scu_ic->num_irqs,
0166                            &aspeed_scu_ic_domain_ops,
0167                            scu_ic);
0168     if (!scu_ic->irq_domain) {
0169         rc = -ENOMEM;
0170         goto err;
0171     }
0172
0173     irq_set_chained_handler_and_data(irq, aspeed_scu_ic_irq_handler,
0174                      scu_ic);
0175
0176     return 0;
0177
0178 err:
0179     kfree(scu_ic);
0180
0181     return rc;
0182 }
0183
0184 static int __init aspeed_scu_ic_of_init(struct device_node *node,
0185                     struct device_node *parent)
0186 {
0187     struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);
0188
0189     if (!scu_ic)
0190         return -ENOMEM;
0191
0192     scu_ic->irq_enable = ASPEED_SCU_IC_ENABLE;
0193     scu_ic->irq_shift = ASPEED_SCU_IC_SHIFT;
0194     scu_ic->num_irqs = ASPEED_SCU_IC_NUM_IRQS;
0195     scu_ic->reg = ASPEED_SCU_IC_REG;
0196
0197     return aspeed_scu_ic_of_init_common(scu_ic, node);
0198 }
0199
0200 static int __init aspeed_ast2600_scu_ic0_of_init(struct device_node *node,
0201                          struct device_node *parent)
0202 {
0203     struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);
0204
0205     if (!scu_ic)
0206         return -ENOMEM;
0207
0208     scu_ic->irq_enable = ASPEED_AST2600_SCU_IC0_ENABLE;
0209     scu_ic->irq_shift = ASPEED_AST2600_SCU_IC0_SHIFT;
0210     scu_ic->num_irqs = ASPEED_AST2600_SCU_IC0_NUM_IRQS;
0211     scu_ic->reg = ASPEED_AST2600_SCU_IC0_REG;
0212
0213     return aspeed_scu_ic_of_init_common(scu_ic, node);
0214 }
0215
0216 static int __init aspeed_ast2600_scu_ic1_of_init(struct device_node *node,
0217                          struct device_node *parent)
0218 {
0219     struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);
0220
0221     if (!scu_ic)
0222         return -ENOMEM;
0223
0224     scu_ic->irq_enable = ASPEED_AST2600_SCU_IC1_ENABLE;
0225     scu_ic->irq_shift = ASPEED_AST2600_SCU_IC1_SHIFT;
0226     scu_ic->num_irqs = ASPEED_AST2600_SCU_IC1_NUM_IRQS;
0227     scu_ic->reg = ASPEED_AST2600_SCU_IC1_REG;
0228
0229     return aspeed_scu_ic_of_init_common(scu_ic, node);
0230 }
0231
0232 IRQCHIP_DECLARE(ast2400_scu_ic, "aspeed,ast2400-scu-ic", aspeed_scu_ic_of_init);
0233 IRQCHIP_DECLARE(ast2500_scu_ic, "aspeed,ast2500-scu-ic", aspeed_scu_ic_of_init);
0234 IRQCHIP_DECLARE(ast2600_scu_ic0, "aspeed,ast2600-scu-ic0",
0235         aspeed_ast2600_scu_ic0_of_init);
0236 IRQCHIP_DECLARE(ast2600_scu_ic1, "aspeed,ast2600-scu-ic1",
0237         aspeed_ast2600_scu_ic1_of_init);