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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Aspeed 24XX/25XX I2C Interrupt Controller.
0004  *
0005  *  Copyright (C) 2012-2017 ASPEED Technology Inc.
0006  *  Copyright 2017 IBM Corporation
0007  *  Copyright 2017 Google, Inc.
0008  */
0009 
0010 #include <linux/irq.h>
0011 #include <linux/irqchip.h>
0012 #include <linux/irqchip/chained_irq.h>
0013 #include <linux/irqdomain.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_irq.h>
0016 #include <linux/io.h>
0017 
0018 
0019 #define ASPEED_I2C_IC_NUM_BUS 14
0020 
0021 struct aspeed_i2c_ic {
0022     void __iomem        *base;
0023     int         parent_irq;
0024     struct irq_domain   *irq_domain;
0025 };
0026 
0027 /*
0028  * The aspeed chip provides a single hardware interrupt for all of the I2C
0029  * busses, so we use a dummy interrupt chip to translate this single interrupt
0030  * into multiple interrupts, each associated with a single I2C bus.
0031  */
0032 static void aspeed_i2c_ic_irq_handler(struct irq_desc *desc)
0033 {
0034     struct aspeed_i2c_ic *i2c_ic = irq_desc_get_handler_data(desc);
0035     struct irq_chip *chip = irq_desc_get_chip(desc);
0036     unsigned long bit, status;
0037 
0038     chained_irq_enter(chip, desc);
0039     status = readl(i2c_ic->base);
0040     for_each_set_bit(bit, &status, ASPEED_I2C_IC_NUM_BUS)
0041         generic_handle_domain_irq(i2c_ic->irq_domain, bit);
0042 
0043     chained_irq_exit(chip, desc);
0044 }
0045 
0046 /*
0047  * Set simple handler and mark IRQ as valid. Nothing interesting to do here
0048  * since we are using a dummy interrupt chip.
0049  */
0050 static int aspeed_i2c_ic_map_irq_domain(struct irq_domain *domain,
0051                     unsigned int irq, irq_hw_number_t hwirq)
0052 {
0053     irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
0054     irq_set_chip_data(irq, domain->host_data);
0055 
0056     return 0;
0057 }
0058 
0059 static const struct irq_domain_ops aspeed_i2c_ic_irq_domain_ops = {
0060     .map = aspeed_i2c_ic_map_irq_domain,
0061 };
0062 
0063 static int __init aspeed_i2c_ic_of_init(struct device_node *node,
0064                     struct device_node *parent)
0065 {
0066     struct aspeed_i2c_ic *i2c_ic;
0067     int ret = 0;
0068 
0069     i2c_ic = kzalloc(sizeof(*i2c_ic), GFP_KERNEL);
0070     if (!i2c_ic)
0071         return -ENOMEM;
0072 
0073     i2c_ic->base = of_iomap(node, 0);
0074     if (!i2c_ic->base) {
0075         ret = -ENOMEM;
0076         goto err_free_ic;
0077     }
0078 
0079     i2c_ic->parent_irq = irq_of_parse_and_map(node, 0);
0080     if (!i2c_ic->parent_irq) {
0081         ret = -EINVAL;
0082         goto err_iounmap;
0083     }
0084 
0085     i2c_ic->irq_domain = irq_domain_add_linear(node, ASPEED_I2C_IC_NUM_BUS,
0086                            &aspeed_i2c_ic_irq_domain_ops,
0087                            NULL);
0088     if (!i2c_ic->irq_domain) {
0089         ret = -ENOMEM;
0090         goto err_iounmap;
0091     }
0092 
0093     i2c_ic->irq_domain->name = "aspeed-i2c-domain";
0094 
0095     irq_set_chained_handler_and_data(i2c_ic->parent_irq,
0096                      aspeed_i2c_ic_irq_handler, i2c_ic);
0097 
0098     pr_info("i2c controller registered, irq %d\n", i2c_ic->parent_irq);
0099 
0100     return 0;
0101 
0102 err_iounmap:
0103     iounmap(i2c_ic->base);
0104 err_free_ic:
0105     kfree(i2c_ic);
0106     return ret;
0107 }
0108 
0109 IRQCHIP_DECLARE(ast2400_i2c_ic, "aspeed,ast2400-i2c-ic", aspeed_i2c_ic_of_init);
0110 IRQCHIP_DECLARE(ast2500_i2c_ic, "aspeed,ast2500-i2c-ic", aspeed_i2c_ic_of_init);