drivers/irqchip/irq-al-fic.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
0004  */
0005
0006 #include <linux/bitfield.h>
0007 #include <linux/irq.h>
0008 #include <linux/irqchip.h>
0009 #include <linux/irqchip/chained_irq.h>
0010 #include <linux/irqdomain.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_irq.h>
0015
0016 /* FIC Registers */
0017 #define AL_FIC_CAUSE        0x00
0018 #define AL_FIC_SET_CAUSE    0x08
0019 #define AL_FIC_MASK     0x10
0020 #define AL_FIC_CONTROL      0x28
0021
0022 #define CONTROL_TRIGGER_RISING  BIT(3)
0023 #define CONTROL_MASK_MSI_X  BIT(5)
0024
0025 #define NR_FIC_IRQS 32
0026
0027 MODULE_AUTHOR("Talel Shenhar");
0028 MODULE_DESCRIPTION("Amazon's Annapurna Labs Interrupt Controller Driver");
0029 MODULE_LICENSE("GPL v2");
0030
0031 enum al_fic_state {
0032     AL_FIC_UNCONFIGURED = 0,
0033     AL_FIC_CONFIGURED_LEVEL,
0034     AL_FIC_CONFIGURED_RISING_EDGE,
0035 };
0036
0037 struct al_fic {
0038     void __iomem *base;
0039     struct irq_domain *domain;
0040     const char *name;
0041     unsigned int parent_irq;
0042     enum al_fic_state state;
0043 };
0044
0045 static void al_fic_set_trigger(struct al_fic *fic,
0046                    struct irq_chip_generic *gc,
0047                    enum al_fic_state new_state)
0048 {
0049     irq_flow_handler_t handler;
0050     u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL);
0051
0052     if (new_state == AL_FIC_CONFIGURED_LEVEL) {
0053         handler = handle_level_irq;
0054         control &= ~CONTROL_TRIGGER_RISING;
0055     } else {
0056         handler = handle_edge_irq;
0057         control |= CONTROL_TRIGGER_RISING;
0058     }
0059     gc->chip_types->handler = handler;
0060     fic->state = new_state;
0061     writel_relaxed(control, fic->base + AL_FIC_CONTROL);
0062 }
0063
0064 static int al_fic_irq_set_type(struct irq_data *data, unsigned int flow_type)
0065 {
0066     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
0067     struct al_fic *fic = gc->private;
0068     enum al_fic_state new_state;
0069     int ret = 0;
0070
0071     irq_gc_lock(gc);
0072
0073     if (((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_HIGH) &&
0074         ((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_EDGE_RISING)) {
0075         pr_debug("fic doesn't support flow type %d\n", flow_type);
0076         ret = -EINVAL;
0077         goto err;
0078     }
0079
0080     new_state = (flow_type & IRQ_TYPE_LEVEL_HIGH) ?
0081         AL_FIC_CONFIGURED_LEVEL : AL_FIC_CONFIGURED_RISING_EDGE;
0082
0083     /*
0084      * A given FIC instance can be either all level or all edge triggered.
0085      * This is generally fixed depending on what pieces of HW it's wired up
0086      * to.
0087      *
0088      * We configure it based on the sensitivity of the first source
0089      * being setup, and reject any subsequent attempt at configuring it in a
0090      * different way.
0091      */
0092     if (fic->state == AL_FIC_UNCONFIGURED) {
0093         al_fic_set_trigger(fic, gc, new_state);
0094     } else if (fic->state != new_state) {
0095         pr_debug("fic %s state already configured to %d\n",
0096              fic->name, fic->state);
0097         ret = -EINVAL;
0098         goto err;
0099     }
0100
0101 err:
0102     irq_gc_unlock(gc);
0103
0104     return ret;
0105 }
0106
0107 static void al_fic_irq_handler(struct irq_desc *desc)
0108 {
0109     struct al_fic *fic = irq_desc_get_handler_data(desc);
0110     struct irq_domain *domain = fic->domain;
0111     struct irq_chip *irqchip = irq_desc_get_chip(desc);
0112     struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);
0113     unsigned long pending;
0114     u32 hwirq;
0115
0116     chained_irq_enter(irqchip, desc);
0117
0118     pending = readl_relaxed(fic->base + AL_FIC_CAUSE);
0119     pending &= ~gc->mask_cache;
0120
0121     for_each_set_bit(hwirq, &pending, NR_FIC_IRQS)
0122         generic_handle_domain_irq(domain, hwirq);
0123
0124     chained_irq_exit(irqchip, desc);
0125 }
0126
0127 static int al_fic_irq_retrigger(struct irq_data *data)
0128 {
0129     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
0130     struct al_fic *fic = gc->private;
0131
0132     writel_relaxed(BIT(data->hwirq), fic->base + AL_FIC_SET_CAUSE);
0133
0134     return 1;
0135 }
0136
0137 static int al_fic_register(struct device_node *node,
0138                struct al_fic *fic)
0139 {
0140     struct irq_chip_generic *gc;
0141     int ret;
0142
0143     fic->domain = irq_domain_add_linear(node,
0144                         NR_FIC_IRQS,
0145                         &irq_generic_chip_ops,
0146                         fic);
0147     if (!fic->domain) {
0148         pr_err("fail to add irq domain\n");
0149         return -ENOMEM;
0150     }
0151
0152     ret = irq_alloc_domain_generic_chips(fic->domain,
0153                          NR_FIC_IRQS,
0154                          1, fic->name,
0155                          handle_level_irq,
0156                          0, 0, IRQ_GC_INIT_MASK_CACHE);
0157     if (ret) {
0158         pr_err("fail to allocate generic chip (%d)\n", ret);
0159         goto err_domain_remove;
0160     }
0161
0162     gc = irq_get_domain_generic_chip(fic->domain, 0);
0163     gc->reg_base = fic->base;
0164     gc->chip_types->regs.mask = AL_FIC_MASK;
0165     gc->chip_types->regs.ack = AL_FIC_CAUSE;
0166     gc->chip_types->chip.irq_mask = irq_gc_mask_set_bit;
0167     gc->chip_types->chip.irq_unmask = irq_gc_mask_clr_bit;
0168     gc->chip_types->chip.irq_ack = irq_gc_ack_clr_bit;
0169     gc->chip_types->chip.irq_set_type = al_fic_irq_set_type;
0170     gc->chip_types->chip.irq_retrigger = al_fic_irq_retrigger;
0171     gc->chip_types->chip.flags = IRQCHIP_SKIP_SET_WAKE;
0172     gc->private = fic;
0173
0174     irq_set_chained_handler_and_data(fic->parent_irq,
0175                      al_fic_irq_handler,
0176                      fic);
0177     return 0;
0178
0179 err_domain_remove:
0180     irq_domain_remove(fic->domain);
0181
0182     return ret;
0183 }
0184
0185 /*
0186  * al_fic_wire_init() - initialize and configure fic in wire mode
0187  * @of_node: optional pointer to interrupt controller's device tree node.
0188  * @base: mmio to fic register
0189  * @name: name of the fic
0190  * @parent_irq: interrupt of parent
0191  *
0192  * This API will configure the fic hardware to to work in wire mode.
0193  * In wire mode, fic hardware is generating a wire ("wired") interrupt.
0194  * Interrupt can be generated based on positive edge or level - configuration is
0195  * to be determined based on connected hardware to this fic.
0196  */
0197 static struct al_fic *al_fic_wire_init(struct device_node *node,
0198                        void __iomem *base,
0199                        const char *name,
0200                        unsigned int parent_irq)
0201 {
0202     struct al_fic *fic;
0203     int ret;
0204     u32 control = CONTROL_MASK_MSI_X;
0205
0206     fic = kzalloc(sizeof(*fic), GFP_KERNEL);
0207     if (!fic)
0208         return ERR_PTR(-ENOMEM);
0209
0210     fic->base = base;
0211     fic->parent_irq = parent_irq;
0212     fic->name = name;
0213
0214     /* mask out all interrupts */
0215     writel_relaxed(0xFFFFFFFF, fic->base + AL_FIC_MASK);
0216
0217     /* clear any pending interrupt */
0218     writel_relaxed(0, fic->base + AL_FIC_CAUSE);
0219
0220     writel_relaxed(control, fic->base + AL_FIC_CONTROL);
0221
0222     ret = al_fic_register(node, fic);
0223     if (ret) {
0224         pr_err("fail to register irqchip\n");
0225         goto err_free;
0226     }
0227
0228     pr_debug("%s initialized successfully in Legacy mode (parent-irq=%u)\n",
0229          fic->name, parent_irq);
0230
0231     return fic;
0232
0233 err_free:
0234     kfree(fic);
0235     return ERR_PTR(ret);
0236 }
0237
0238 static int __init al_fic_init_dt(struct device_node *node,
0239                  struct device_node *parent)
0240 {
0241     int ret;
0242     void __iomem *base;
0243     unsigned int parent_irq;
0244     struct al_fic *fic;
0245
0246     if (!parent) {
0247         pr_err("%s: unsupported - device require a parent\n",
0248                node->name);
0249         return -EINVAL;
0250     }
0251
0252     base = of_iomap(node, 0);
0253     if (!base) {
0254         pr_err("%s: fail to map memory\n", node->name);
0255         return -ENOMEM;
0256     }
0257
0258     parent_irq = irq_of_parse_and_map(node, 0);
0259     if (!parent_irq) {
0260         pr_err("%s: fail to map irq\n", node->name);
0261         ret = -EINVAL;
0262         goto err_unmap;
0263     }
0264
0265     fic = al_fic_wire_init(node,
0266                    base,
0267                    node->name,
0268                    parent_irq);
0269     if (IS_ERR(fic)) {
0270         pr_err("%s: fail to initialize irqchip (%lu)\n",
0271                node->name,
0272                PTR_ERR(fic));
0273         ret = PTR_ERR(fic);
0274         goto err_irq_dispose;
0275     }
0276
0277     return 0;
0278
0279 err_irq_dispose:
0280     irq_dispose_mapping(parent_irq);
0281 err_unmap:
0282     iounmap(base);
0283
0284     return ret;
0285 }
0286
0287 IRQCHIP_DECLARE(al_fic, "amazon,al-fic", al_fic_init_dt);