drivers/irqchip/alphascale_asm9260-icoll.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
0004  */
0005
0006 #ifndef _ALPHASCALE_ASM9260_ICOLL_H
0007 #define _ALPHASCALE_ASM9260_ICOLL_H
0008
0009 #define ASM9260_NUM_IRQS        64
0010 /*
0011  * this device provide 4 offsets for each register:
0012  * 0x0 - plain read write mode
0013  * 0x4 - set mode, OR logic.
0014  * 0x8 - clr mode, XOR logic.
0015  * 0xc - togle mode.
0016  */
0017
0018 #define ASM9260_HW_ICOLL_VECTOR             0x0000
0019 /*
0020  * bits 31:2
0021  * This register presents the vector address for the interrupt currently
0022  * active on the CPU IRQ input. Writing to this register notifies the
0023  * interrupt collector that the interrupt service routine for the current
0024  * interrupt has been entered.
0025  * The exception trap should have a LDPC instruction from this address:
0026  * LDPC ASM9260_HW_ICOLL_VECTOR_ADDR; IRQ exception at 0xffff0018
0027  */
0028
0029 /*
0030  * The Interrupt Collector Level Acknowledge Register is used by software to
0031  * indicate the completion of an interrupt on a specific level.
0032  * This register is written at the very end of an interrupt service routine. If
0033  * nesting is used then the CPU irq must be turned on before writing to this
0034  * register to avoid a race condition in the CPU interrupt hardware.
0035  */
0036 #define ASM9260_HW_ICOLL_LEVELACK           0x0010
0037 #define ASM9260_BM_LEVELn(nr)               BIT(nr)
0038
0039 #define ASM9260_HW_ICOLL_CTRL               0x0020
0040 /*
0041  * ASM9260_BM_CTRL_SFTRST and ASM9260_BM_CTRL_CLKGATE are not available on
0042  * asm9260.
0043  */
0044 #define ASM9260_BM_CTRL_SFTRST              BIT(31)
0045 #define ASM9260_BM_CTRL_CLKGATE             BIT(30)
0046 /* disable interrupt level nesting */
0047 #define ASM9260_BM_CTRL_NO_NESTING          BIT(19)
0048 /*
0049  * Set this bit to one enable the RISC32-style read side effect associated with
0050  * the vector address register. In this mode, interrupt in-service is signaled
0051  * by the read of the ASM9260_HW_ICOLL_VECTOR register to acquire the interrupt
0052  * vector address. Set this bit to zero for normal operation, in which the ISR
0053  * signals in-service explicitly by means of a write to the
0054  * ASM9260_HW_ICOLL_VECTOR register.
0055  * 0 - Must Write to Vector register to go in-service.
0056  * 1 - Go in-service as a read side effect
0057  */
0058 #define ASM9260_BM_CTRL_ARM_RSE_MODE            BIT(18)
0059 #define ASM9260_BM_CTRL_IRQ_ENABLE          BIT(16)
0060
0061 #define ASM9260_HW_ICOLL_STAT_OFFSET            0x0030
0062 /*
0063  * bits 5:0
0064  * Vector number of current interrupt. Multiply by 4 and add to vector base
0065  * address to obtain the value in ASM9260_HW_ICOLL_VECTOR.
0066  */
0067
0068 /*
0069  * RAW0 and RAW1 provides a read-only view of the raw interrupt request lines
0070  * coming from various parts of the chip. Its purpose is to improve diagnostic
0071  * observability.
0072  */
0073 #define ASM9260_HW_ICOLL_RAW0               0x0040
0074 #define ASM9260_HW_ICOLL_RAW1               0x0050
0075
0076 #define ASM9260_HW_ICOLL_INTERRUPT0         0x0060
0077 #define ASM9260_HW_ICOLL_INTERRUPTn(n)      (0x0060 + ((n) >> 2) * 0x10)
0078 /*
0079  * WARNING: Modifying the priority of an enabled interrupt may result in
0080  * undefined behavior.
0081  */
0082 #define ASM9260_BM_INT_PRIORITY_MASK            0x3
0083 #define ASM9260_BM_INT_ENABLE               BIT(2)
0084 #define ASM9260_BM_INT_SOFTIRQ              BIT(3)
0085
0086 #define ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n)        (((n) & 0x3) << 3)
0087 #define ASM9260_BM_ICOLL_INTERRUPTn_ENABLE(n)       (1 << (2 + \
0088             ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n)))
0089
0090 #define ASM9260_HW_ICOLL_VBASE              0x0160
0091 /*
0092  * bits 31:2
0093  * This bitfield holds the upper 30 bits of the base address of the vector
0094  * table.
0095  */
0096
0097 #define ASM9260_HW_ICOLL_CLEAR0             0x01d0
0098 #define ASM9260_HW_ICOLL_CLEAR1             0x01e0
0099 #define ASM9260_HW_ICOLL_CLEARn(n)          (((n >> 5) * 0x10) \
0100                             + SET_REG)
0101 #define ASM9260_BM_CLEAR_BIT(n)             BIT(n & 0x1f)
0102
0103 /* Scratchpad */
0104 #define ASM9260_HW_ICOLL_UNDEF_VECTOR           0x01f0
0105 #endif