ipack/devices/scc2698.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * scc2698.h
0004  *
0005  * driver for the IPOCTAL boards
0006  *
0007  * Copyright (C) 2009-2012 CERN (www.cern.ch)
0008  * Author: Nicolas Serafini, EIC2 SA
0009  * Author: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
0010  */
0011
0012 #ifndef SCC2698_H_
0013 #define SCC2698_H_
0014
0015 /*
0016  * union scc2698_channel - Channel access to scc2698 IO
0017  *
0018  * dn value are only spacer.
0019  *
0020  */
0021 union scc2698_channel {
0022     struct {
0023         u8 d0, mr;  /* Mode register 1/2*/
0024         u8 d1, sr;  /* Status register */
0025         u8 d2, r1;  /* reserved */
0026         u8 d3, rhr; /* Receive holding register (R) */
0027         u8 junk[8]; /* other crap for block control */
0028     } __packed r; /* Read access */
0029     struct {
0030         u8 d0, mr;  /* Mode register 1/2 */
0031         u8 d1, csr; /* Clock select register */
0032         u8 d2, cr;  /* Command register */
0033         u8 d3, thr; /* Transmit holding register */
0034         u8 junk[8]; /* other crap for block control */
0035     } __packed w; /* Write access */
0036 };
0037
0038 /*
0039  * union scc2698_block - Block access to scc2698 IO
0040  *
0041  * The scc2698 contain 4 block.
0042  * Each block containt two channel a and b.
0043  * dn value are only spacer.
0044  *
0045  */
0046 union scc2698_block {
0047     struct {
0048         u8 d0, mra;  /* Mode register 1/2 (a) */
0049         u8 d1, sra;  /* Status register (a) */
0050         u8 d2, r1;   /* reserved */
0051         u8 d3, rhra; /* Receive holding register (a) */
0052         u8 d4, ipcr; /* Input port change register of block */
0053         u8 d5, isr;  /* Interrupt status register of block */
0054         u8 d6, ctur; /* Counter timer upper register of block */
0055         u8 d7, ctlr; /* Counter timer lower register of block */
0056         u8 d8, mrb;  /* Mode register 1/2 (b) */
0057         u8 d9, srb;  /* Status register (b) */
0058         u8 da, r2;   /* reserved */
0059         u8 db, rhrb; /* Receive holding register (b) */
0060         u8 dc, r3;   /* reserved */
0061         u8 dd, ip;   /* Input port register of block */
0062         u8 de, ctg;  /* Start counter timer of block */
0063         u8 df, cts;  /* Stop counter timer of block */
0064     } __packed r; /* Read access */
0065     struct {
0066         u8 d0, mra;  /* Mode register 1/2 (a) */
0067         u8 d1, csra; /* Clock select register (a) */
0068         u8 d2, cra;  /* Command register (a) */
0069         u8 d3, thra; /* Transmit holding register (a) */
0070         u8 d4, acr;  /* Auxiliary control register of block */
0071         u8 d5, imr;  /* Interrupt mask register of block  */
0072         u8 d6, ctu;  /* Counter timer upper register of block */
0073         u8 d7, ctl;  /* Counter timer lower register of block */
0074         u8 d8, mrb;  /* Mode register 1/2 (b) */
0075         u8 d9, csrb; /* Clock select register (a) */
0076         u8 da, crb;  /* Command register (b) */
0077         u8 db, thrb; /* Transmit holding register (b) */
0078         u8 dc, r1;   /* reserved */
0079         u8 dd, opcr; /* Output port configuration register of block */
0080         u8 de, r2;   /* reserved */
0081         u8 df, r3;   /* reserved */
0082     } __packed w; /* Write access */
0083 };
0084
0085 #define MR1_CHRL_5_BITS             (0x0 << 0)
0086 #define MR1_CHRL_6_BITS             (0x1 << 0)
0087 #define MR1_CHRL_7_BITS             (0x2 << 0)
0088 #define MR1_CHRL_8_BITS             (0x3 << 0)
0089 #define MR1_PARITY_EVEN             (0x1 << 2)
0090 #define MR1_PARITY_ODD              (0x0 << 2)
0091 #define MR1_PARITY_ON               (0x0 << 3)
0092 #define MR1_PARITY_FORCE            (0x1 << 3)
0093 #define MR1_PARITY_OFF              (0x2 << 3)
0094 #define MR1_PARITY_SPECIAL          (0x3 << 3)
0095 #define MR1_ERROR_CHAR              (0x0 << 5)
0096 #define MR1_ERROR_BLOCK             (0x1 << 5)
0097 #define MR1_RxINT_RxRDY             (0x0 << 6)
0098 #define MR1_RxINT_FFULL             (0x1 << 6)
0099 #define MR1_RxRTS_CONTROL_ON        (0x1 << 7)
0100 #define MR1_RxRTS_CONTROL_OFF       (0x0 << 7)
0101
0102 #define MR2_STOP_BITS_LENGTH_1      (0x7 << 0)
0103 #define MR2_STOP_BITS_LENGTH_2      (0xF << 0)
0104 #define MR2_CTS_ENABLE_TX_ON        (0x1 << 4)
0105 #define MR2_CTS_ENABLE_TX_OFF       (0x0 << 4)
0106 #define MR2_TxRTS_CONTROL_ON        (0x1 << 5)
0107 #define MR2_TxRTS_CONTROL_OFF       (0x0 << 5)
0108 #define MR2_CH_MODE_NORMAL          (0x0 << 6)
0109 #define MR2_CH_MODE_ECHO            (0x1 << 6)
0110 #define MR2_CH_MODE_LOCAL           (0x2 << 6)
0111 #define MR2_CH_MODE_REMOTE          (0x3 << 6)
0112
0113 #define CR_ENABLE_RX                (0x1 << 0)
0114 #define CR_DISABLE_RX               (0x1 << 1)
0115 #define CR_ENABLE_TX                (0x1 << 2)
0116 #define CR_DISABLE_TX               (0x1 << 3)
0117 #define CR_CMD_RESET_MR             (0x1 << 4)
0118 #define CR_CMD_RESET_RX             (0x2 << 4)
0119 #define CR_CMD_RESET_TX             (0x3 << 4)
0120 #define CR_CMD_RESET_ERR_STATUS     (0x4 << 4)
0121 #define CR_CMD_RESET_BREAK_CHANGE   (0x5 << 4)
0122 #define CR_CMD_START_BREAK          (0x6 << 4)
0123 #define CR_CMD_STOP_BREAK           (0x7 << 4)
0124 #define CR_CMD_ASSERT_RTSN          (0x8 << 4)
0125 #define CR_CMD_NEGATE_RTSN          (0x9 << 4)
0126 #define CR_CMD_SET_TIMEOUT_MODE     (0xA << 4)
0127 #define CR_CMD_DISABLE_TIMEOUT_MODE (0xC << 4)
0128
0129 #define SR_RX_READY                 (0x1 << 0)
0130 #define SR_FIFO_FULL                (0x1 << 1)
0131 #define SR_TX_READY                 (0x1 << 2)
0132 #define SR_TX_EMPTY                 (0x1 << 3)
0133 #define SR_OVERRUN_ERROR            (0x1 << 4)
0134 #define SR_PARITY_ERROR             (0x1 << 5)
0135 #define SR_FRAMING_ERROR            (0x1 << 6)
0136 #define SR_RECEIVED_BREAK           (0x1 << 7)
0137
0138 #define SR_ERROR                    (0xF0)
0139
0140 #define ACR_DELTA_IP0_IRQ_EN        (0x1 << 0)
0141 #define ACR_DELTA_IP1_IRQ_EN        (0x1 << 1)
0142 #define ACR_DELTA_IP2_IRQ_EN        (0x1 << 2)
0143 #define ACR_DELTA_IP3_IRQ_EN        (0x1 << 3)
0144 #define ACR_CT_Mask                 (0x7 << 4)
0145 #define ACR_CExt                    (0x0 << 4)
0146 #define ACR_CTxCA                   (0x1 << 4)
0147 #define ACR_CTxCB                   (0x2 << 4)
0148 #define ACR_CClk16                  (0x3 << 4)
0149 #define ACR_TExt                    (0x4 << 4)
0150 #define ACR_TExt16                  (0x5 << 4)
0151 #define ACR_TClk                    (0x6 << 4)
0152 #define ACR_TClk16                  (0x7 << 4)
0153 #define ACR_BRG_SET1                (0x0 << 7)
0154 #define ACR_BRG_SET2                (0x1 << 7)
0155
0156 #define TX_CLK_75                   (0x0 << 0)
0157 #define TX_CLK_110                  (0x1 << 0)
0158 #define TX_CLK_38400                (0x2 << 0)
0159 #define TX_CLK_150                  (0x3 << 0)
0160 #define TX_CLK_300                  (0x4 << 0)
0161 #define TX_CLK_600                  (0x5 << 0)
0162 #define TX_CLK_1200                 (0x6 << 0)
0163 #define TX_CLK_2000                 (0x7 << 0)
0164 #define TX_CLK_2400                 (0x8 << 0)
0165 #define TX_CLK_4800                 (0x9 << 0)
0166 #define TX_CLK_1800                 (0xA << 0)
0167 #define TX_CLK_9600                 (0xB << 0)
0168 #define TX_CLK_19200                (0xC << 0)
0169 #define RX_CLK_75                   (0x0 << 4)
0170 #define RX_CLK_110                  (0x1 << 4)
0171 #define RX_CLK_38400                (0x2 << 4)
0172 #define RX_CLK_150                  (0x3 << 4)
0173 #define RX_CLK_300                  (0x4 << 4)
0174 #define RX_CLK_600                  (0x5 << 4)
0175 #define RX_CLK_1200                 (0x6 << 4)
0176 #define RX_CLK_2000                 (0x7 << 4)
0177 #define RX_CLK_2400                 (0x8 << 4)
0178 #define RX_CLK_4800                 (0x9 << 4)
0179 #define RX_CLK_1800                 (0xA << 4)
0180 #define RX_CLK_9600                 (0xB << 4)
0181 #define RX_CLK_19200                (0xC << 4)
0182
0183 #define OPCR_MPOa_RTSN              (0x0 << 0)
0184 #define OPCR_MPOa_C_TO              (0x1 << 0)
0185 #define OPCR_MPOa_TxC1X             (0x2 << 0)
0186 #define OPCR_MPOa_TxC16X            (0x3 << 0)
0187 #define OPCR_MPOa_RxC1X             (0x4 << 0)
0188 #define OPCR_MPOa_RxC16X            (0x5 << 0)
0189 #define OPCR_MPOa_TxRDY             (0x6 << 0)
0190 #define OPCR_MPOa_RxRDY_FF          (0x7 << 0)
0191
0192 #define OPCR_MPOb_RTSN              (0x0 << 4)
0193 #define OPCR_MPOb_C_TO              (0x1 << 4)
0194 #define OPCR_MPOb_TxC1X             (0x2 << 4)
0195 #define OPCR_MPOb_TxC16X            (0x3 << 4)
0196 #define OPCR_MPOb_RxC1X             (0x4 << 4)
0197 #define OPCR_MPOb_RxC16X            (0x5 << 4)
0198 #define OPCR_MPOb_TxRDY             (0x6 << 4)
0199 #define OPCR_MPOb_RxRDY_FF          (0x7 << 4)
0200
0201 #define OPCR_MPP_INPUT              (0x0 << 7)
0202 #define OPCR_MPP_OUTPUT             (0x1 << 7)
0203
0204 #define IMR_TxRDY_A                 (0x1 << 0)
0205 #define IMR_RxRDY_FFULL_A           (0x1 << 1)
0206 #define IMR_DELTA_BREAK_A           (0x1 << 2)
0207 #define IMR_COUNTER_READY           (0x1 << 3)
0208 #define IMR_TxRDY_B                 (0x1 << 4)
0209 #define IMR_RxRDY_FFULL_B           (0x1 << 5)
0210 #define IMR_DELTA_BREAK_B           (0x1 << 6)
0211 #define IMR_INPUT_PORT_CHANGE       (0x1 << 7)
0212
0213 #define ISR_TxRDY_A                 (0x1 << 0)
0214 #define ISR_RxRDY_FFULL_A           (0x1 << 1)
0215 #define ISR_DELTA_BREAK_A           (0x1 << 2)
0216 #define ISR_COUNTER_READY           (0x1 << 3)
0217 #define ISR_TxRDY_B                 (0x1 << 4)
0218 #define ISR_RxRDY_FFULL_B           (0x1 << 5)
0219 #define ISR_DELTA_BREAK_B           (0x1 << 6)
0220 #define ISR_INPUT_PORT_CHANGE       (0x1 << 7)
0221
0222 #define ACK_INT_REQ0            0
0223 #define ACK_INT_REQ1            2
0224
0225 #endif /* SCC2698_H_ */