ipack/carriers/tpci200.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * driver for the carrier TEWS TPCI-200
0004  *
0005  * Copyright (C) 2009-2012 CERN (www.cern.ch)
0006  * Author: Nicolas Serafini, EIC2 SA
0007  * Author: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
0008  */
0009
0010 #ifndef _TPCI200_H_
0011 #define _TPCI200_H_
0012
0013 #include <linux/limits.h>
0014 #include <linux/pci.h>
0015 #include <linux/spinlock.h>
0016 #include <linux/swab.h>
0017 #include <linux/io.h>
0018 #include <linux/ipack.h>
0019
0020 #define TPCI200_NB_SLOT               0x4
0021 #define TPCI200_NB_BAR                0x6
0022
0023 #define TPCI200_VENDOR_ID             0x1498
0024 #define TPCI200_DEVICE_ID             0x30C8
0025 #define TPCI200_SUBVENDOR_ID          0x1498
0026 #define TPCI200_SUBDEVICE_ID          0x300A
0027
0028 #define TPCI200_CFG_MEM_BAR           0
0029 #define TPCI200_IP_INTERFACE_BAR      2
0030 #define TPCI200_IO_ID_INT_SPACES_BAR  3
0031 #define TPCI200_MEM16_SPACE_BAR       4
0032 #define TPCI200_MEM8_SPACE_BAR        5
0033
0034 struct tpci200_regs {
0035     __le16  revision;
0036     /* writes to control should occur with the mutex held to protect
0037      * read-modify-write operations */
0038     __le16  control[4];
0039     __le16  reset;
0040     __le16  status;
0041     u8  reserved[242];
0042 } __packed;
0043
0044 #define TPCI200_IFACE_SIZE            0x100
0045
0046 #define TPCI200_IO_SPACE_OFF          0x0000
0047 #define TPCI200_IO_SPACE_INTERVAL     0x0100
0048 #define TPCI200_IO_SPACE_SIZE         0x0080
0049 #define TPCI200_ID_SPACE_OFF          0x0080
0050 #define TPCI200_ID_SPACE_INTERVAL     0x0100
0051 #define TPCI200_ID_SPACE_SIZE         0x0040
0052 #define TPCI200_INT_SPACE_OFF         0x00C0
0053 #define TPCI200_INT_SPACE_INTERVAL    0x0100
0054 #define TPCI200_INT_SPACE_SIZE        0x0040
0055 #define TPCI200_IOIDINT_SIZE          0x0400
0056
0057 #define TPCI200_MEM8_SPACE_INTERVAL   0x00400000
0058 #define TPCI200_MEM8_SPACE_SIZE       0x00400000
0059 #define TPCI200_MEM16_SPACE_INTERVAL  0x00800000
0060 #define TPCI200_MEM16_SPACE_SIZE      0x00800000
0061
0062 /* control field in tpci200_regs */
0063 #define TPCI200_INT0_EN               0x0040
0064 #define TPCI200_INT1_EN               0x0080
0065 #define TPCI200_INT0_EDGE             0x0010
0066 #define TPCI200_INT1_EDGE             0x0020
0067 #define TPCI200_ERR_INT_EN            0x0008
0068 #define TPCI200_TIME_INT_EN           0x0004
0069 #define TPCI200_RECOVER_EN            0x0002
0070 #define TPCI200_CLK32                 0x0001
0071
0072 /* reset field in tpci200_regs */
0073 #define TPCI200_A_RESET               0x0001
0074 #define TPCI200_B_RESET               0x0002
0075 #define TPCI200_C_RESET               0x0004
0076 #define TPCI200_D_RESET               0x0008
0077
0078 /* status field in tpci200_regs */
0079 #define TPCI200_A_TIMEOUT             0x1000
0080 #define TPCI200_B_TIMEOUT             0x2000
0081 #define TPCI200_C_TIMEOUT             0x4000
0082 #define TPCI200_D_TIMEOUT             0x8000
0083
0084 #define TPCI200_A_ERROR               0x0100
0085 #define TPCI200_B_ERROR               0x0200
0086 #define TPCI200_C_ERROR               0x0400
0087 #define TPCI200_D_ERROR               0x0800
0088
0089 #define TPCI200_A_INT0                0x0001
0090 #define TPCI200_A_INT1                0x0002
0091 #define TPCI200_B_INT0                0x0004
0092 #define TPCI200_B_INT1                0x0008
0093 #define TPCI200_C_INT0                0x0010
0094 #define TPCI200_C_INT1                0x0020
0095 #define TPCI200_D_INT0                0x0040
0096 #define TPCI200_D_INT1                0x0080
0097
0098 #define TPCI200_SLOT_INT_MASK         0x00FF
0099
0100 /* PCI Configuration registers. The PCI bridge is a PLX Technology PCI9030. */
0101 #define LAS1_DESC             0x2C
0102 #define LAS2_DESC             0x30
0103
0104 /* Bits in the LAS?_DESC registers */
0105 #define LAS_BIT_BIGENDIAN         24
0106
0107 #define VME_IOID_SPACE  "IOID"
0108 #define VME_MEM_SPACE  "MEM"
0109
0110 /**
0111  * struct slot_irq - slot IRQ definition.
0112  * @vector  Vector number
0113  * @handler Handler called when IRQ arrives
0114  * @arg     Handler argument
0115  *
0116  */
0117 struct slot_irq {
0118     struct ipack_device *holder;
0119     int     vector;
0120     irqreturn_t (*handler)(void *);
0121     void        *arg;
0122 };
0123
0124 /**
0125  * struct tpci200_slot - data specific to the tpci200 slot.
0126  * @slot_id Slot identification gived to external interface
0127  * @irq     Slot IRQ infos
0128  * @io_phys IO physical base address register of the slot
0129  * @id_phys ID physical base address register of the slot
0130  * @int_phys    INT physical base address register of the slot
0131  * @mem_phys    MEM physical base address register of the slot
0132  *
0133  */
0134 struct tpci200_slot {
0135     struct slot_irq     *irq;
0136 };
0137
0138 /**
0139  * struct tpci200_infos - informations specific of the TPCI200 tpci200.
0140  * @pci_dev     PCI device
0141  * @interface_regs  Pointer to IP interface space (Bar 2)
0142  * @ioidint_space   Pointer to IP ID, IO and INT space (Bar 3)
0143  * @mem8_space      Pointer to MEM space (Bar 4)
0144  *
0145  */
0146 struct tpci200_infos {
0147     struct pci_dev          *pdev;
0148     struct pci_device_id        *id_table;
0149     struct tpci200_regs __iomem *interface_regs;
0150     void __iomem            *cfg_regs;
0151     struct ipack_bus_device     *ipack_bus;
0152 };
0153 struct tpci200_board {
0154     unsigned int        number;
0155     struct mutex        mutex;
0156     spinlock_t      regs_lock;
0157     struct tpci200_slot *slots;
0158     struct tpci200_infos    *info;
0159     phys_addr_t             mod_mem[IPACK_SPACE_COUNT];
0160 };
0161
0162 #endif /* _TPCI200_H_ */