drivers/iommu/omap-iommu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * omap iommu: main structures
0004  *
0005  * Copyright (C) 2008-2009 Nokia Corporation
0006  *
0007  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
0008  */
0009
0010 #ifndef _OMAP_IOMMU_H
0011 #define _OMAP_IOMMU_H
0012
0013 #include <linux/bitops.h>
0014 #include <linux/iommu.h>
0015
0016 #define for_each_iotlb_cr(obj, n, __i, cr)              \
0017     for (__i = 0;                           \
0018          (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true);   \
0019          __i++)
0020
0021 struct iotlb_entry {
0022     u32 da;
0023     u32 pa;
0024     u32 pgsz, prsvd, valid;
0025     u32 endian, elsz, mixed;
0026 };
0027
0028 /**
0029  * struct omap_iommu_device - omap iommu device data
0030  * @pgtable:    page table used by an omap iommu attached to a domain
0031  * @iommu_dev:  pointer to store an omap iommu instance attached to a domain
0032  */
0033 struct omap_iommu_device {
0034     u32 *pgtable;
0035     struct omap_iommu *iommu_dev;
0036 };
0037
0038 /**
0039  * struct omap_iommu_domain - omap iommu domain
0040  * @num_iommus: number of iommus in this domain
0041  * @iommus: omap iommu device data for all iommus in this domain
0042  * @dev:    Device using this domain.
0043  * @lock:   domain lock, should be taken when attaching/detaching
0044  * @domain: generic domain handle used by iommu core code
0045  */
0046 struct omap_iommu_domain {
0047     u32 num_iommus;
0048     struct omap_iommu_device *iommus;
0049     struct device *dev;
0050     spinlock_t lock;
0051     struct iommu_domain domain;
0052 };
0053
0054 struct omap_iommu {
0055     const char  *name;
0056     void __iomem    *regbase;
0057     struct regmap   *syscfg;
0058     struct device   *dev;
0059     struct iommu_domain *domain;
0060     struct dentry   *debug_dir;
0061
0062     spinlock_t  iommu_lock; /* global for this whole object */
0063
0064     /*
0065      * We don't change iopgd for a situation like pgd for a task,
0066      * but share it globally for each iommu.
0067      */
0068     u32     *iopgd;
0069     spinlock_t  page_table_lock; /* protect iopgd */
0070     dma_addr_t  pd_dma;
0071
0072     int     nr_tlb_entries;
0073
0074     void *ctx; /* iommu context: registres saved area */
0075
0076     struct cr_regs *cr_ctx;
0077     u32 num_cr_ctx;
0078
0079     int has_bus_err_back;
0080     u32 id;
0081
0082     struct iommu_device iommu;
0083     struct iommu_group *group;
0084
0085     u8 pwrst;
0086 };
0087
0088 /**
0089  * struct omap_iommu_arch_data - omap iommu private data
0090  * @iommu_dev: handle of the OMAP iommu device
0091  * @dev: handle of the iommu device
0092  *
0093  * This is an omap iommu private data object, which binds an iommu user
0094  * to its iommu device. This object should be placed at the iommu user's
0095  * dev_archdata so generic IOMMU API can be used without having to
0096  * utilize omap-specific plumbing anymore.
0097  */
0098 struct omap_iommu_arch_data {
0099     struct omap_iommu *iommu_dev;
0100     struct device *dev;
0101 };
0102
0103 struct cr_regs {
0104     u32 cam;
0105     u32 ram;
0106 };
0107
0108 struct iotlb_lock {
0109     short base;
0110     short vict;
0111 };
0112
0113 /*
0114  * MMU Register offsets
0115  */
0116 #define MMU_REVISION        0x00
0117 #define MMU_IRQSTATUS       0x18
0118 #define MMU_IRQENABLE       0x1c
0119 #define MMU_WALKING_ST      0x40
0120 #define MMU_CNTL        0x44
0121 #define MMU_FAULT_AD        0x48
0122 #define MMU_TTB         0x4c
0123 #define MMU_LOCK        0x50
0124 #define MMU_LD_TLB      0x54
0125 #define MMU_CAM         0x58
0126 #define MMU_RAM         0x5c
0127 #define MMU_GFLUSH      0x60
0128 #define MMU_FLUSH_ENTRY     0x64
0129 #define MMU_READ_CAM        0x68
0130 #define MMU_READ_RAM        0x6c
0131 #define MMU_EMU_FAULT_AD    0x70
0132 #define MMU_GP_REG      0x88
0133
0134 #define MMU_REG_SIZE        256
0135
0136 /*
0137  * MMU Register bit definitions
0138  */
0139 /* IRQSTATUS & IRQENABLE */
0140 #define MMU_IRQ_MULTIHITFAULT   BIT(4)
0141 #define MMU_IRQ_TABLEWALKFAULT  BIT(3)
0142 #define MMU_IRQ_EMUMISS     BIT(2)
0143 #define MMU_IRQ_TRANSLATIONFAULT    BIT(1)
0144 #define MMU_IRQ_TLBMISS     BIT(0)
0145
0146 #define __MMU_IRQ_FAULT     \
0147     (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
0148 #define MMU_IRQ_MASK        \
0149     (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
0150 #define MMU_IRQ_TWL_MASK    (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
0151 #define MMU_IRQ_TLB_MISS_MASK   (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
0152
0153 /* MMU_CNTL */
0154 #define MMU_CNTL_SHIFT      1
0155 #define MMU_CNTL_MASK       (7 << MMU_CNTL_SHIFT)
0156 #define MMU_CNTL_EML_TLB    BIT(3)
0157 #define MMU_CNTL_TWL_EN     BIT(2)
0158 #define MMU_CNTL_MMU_EN     BIT(1)
0159
0160 /* CAM */
0161 #define MMU_CAM_VATAG_SHIFT 12
0162 #define MMU_CAM_VATAG_MASK \
0163     ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
0164 #define MMU_CAM_P       BIT(3)
0165 #define MMU_CAM_V       BIT(2)
0166 #define MMU_CAM_PGSZ_MASK   3
0167 #define MMU_CAM_PGSZ_1M     (0 << 0)
0168 #define MMU_CAM_PGSZ_64K    (1 << 0)
0169 #define MMU_CAM_PGSZ_4K     (2 << 0)
0170 #define MMU_CAM_PGSZ_16M    (3 << 0)
0171
0172 /* RAM */
0173 #define MMU_RAM_PADDR_SHIFT 12
0174 #define MMU_RAM_PADDR_MASK \
0175     ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
0176
0177 #define MMU_RAM_ENDIAN_SHIFT    9
0178 #define MMU_RAM_ENDIAN_MASK BIT(MMU_RAM_ENDIAN_SHIFT)
0179 #define MMU_RAM_ENDIAN_LITTLE   (0 << MMU_RAM_ENDIAN_SHIFT)
0180 #define MMU_RAM_ENDIAN_BIG  BIT(MMU_RAM_ENDIAN_SHIFT)
0181
0182 #define MMU_RAM_ELSZ_SHIFT  7
0183 #define MMU_RAM_ELSZ_MASK   (3 << MMU_RAM_ELSZ_SHIFT)
0184 #define MMU_RAM_ELSZ_8      (0 << MMU_RAM_ELSZ_SHIFT)
0185 #define MMU_RAM_ELSZ_16     (1 << MMU_RAM_ELSZ_SHIFT)
0186 #define MMU_RAM_ELSZ_32     (2 << MMU_RAM_ELSZ_SHIFT)
0187 #define MMU_RAM_ELSZ_NONE   (3 << MMU_RAM_ELSZ_SHIFT)
0188 #define MMU_RAM_MIXED_SHIFT 6
0189 #define MMU_RAM_MIXED_MASK  BIT(MMU_RAM_MIXED_SHIFT)
0190 #define MMU_RAM_MIXED       MMU_RAM_MIXED_MASK
0191
0192 #define MMU_GP_REG_BUS_ERR_BACK_EN  0x1
0193
0194 #define get_cam_va_mask(pgsz)               \
0195     (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :    \
0196      ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :    \
0197      ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :    \
0198      ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
0199
0200 /*
0201  * DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP)
0202  */
0203 #define DSP_SYS_REVISION        0x00
0204 #define DSP_SYS_MMU_CONFIG      0x18
0205 #define DSP_SYS_MMU_CONFIG_EN_SHIFT 4
0206
0207 /*
0208  * utilities for super page(16MB, 1MB, 64KB and 4KB)
0209  */
0210
0211 #define iopgsz_max(bytes)           \
0212     (((bytes) >= SZ_16M) ? SZ_16M :     \
0213      ((bytes) >= SZ_1M)  ? SZ_1M  :     \
0214      ((bytes) >= SZ_64K) ? SZ_64K :     \
0215      ((bytes) >= SZ_4K)  ? SZ_4K  : 0)
0216
0217 #define bytes_to_iopgsz(bytes)              \
0218     (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M :   \
0219      ((bytes) == SZ_1M)  ? MMU_CAM_PGSZ_1M  :   \
0220      ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K :   \
0221      ((bytes) == SZ_4K)  ? MMU_CAM_PGSZ_4K  : -1)
0222
0223 #define iopgsz_to_bytes(iopgsz)             \
0224     (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M :  \
0225      ((iopgsz) == MMU_CAM_PGSZ_1M)  ? SZ_1M  :  \
0226      ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K :  \
0227      ((iopgsz) == MMU_CAM_PGSZ_4K)  ? SZ_4K  : 0)
0228
0229 #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
0230
0231 /*
0232  * global functions
0233  */
0234
0235 struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n);
0236 void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l);
0237 void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l);
0238
0239 #ifdef CONFIG_OMAP_IOMMU_DEBUG
0240 void omap_iommu_debugfs_init(void);
0241 void omap_iommu_debugfs_exit(void);
0242
0243 void omap_iommu_debugfs_add(struct omap_iommu *obj);
0244 void omap_iommu_debugfs_remove(struct omap_iommu *obj);
0245 #else
0246 static inline void omap_iommu_debugfs_init(void) { }
0247 static inline void omap_iommu_debugfs_exit(void) { }
0248
0249 static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
0250 static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
0251 #endif
0252
0253 /*
0254  * register accessors
0255  */
0256 static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
0257 {
0258     return __raw_readl(obj->regbase + offs);
0259 }
0260
0261 static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
0262 {
0263     __raw_writel(val, obj->regbase + offs);
0264 }
0265
0266 static inline int iotlb_cr_valid(struct cr_regs *cr)
0267 {
0268     if (!cr)
0269         return -EINVAL;
0270
0271     return cr->cam & MMU_CAM_V;
0272 }
0273
0274 #endif /* _OMAP_IOMMU_H */