drivers/iommu/msm_iommu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
0003  */
0004
0005 #ifndef MSM_IOMMU_H
0006 #define MSM_IOMMU_H
0007
0008 #include <linux/interrupt.h>
0009 #include <linux/iommu.h>
0010 #include <linux/clk.h>
0011
0012 /* Sharability attributes of MSM IOMMU mappings */
0013 #define MSM_IOMMU_ATTR_NON_SH       0x0
0014 #define MSM_IOMMU_ATTR_SH       0x4
0015
0016 /* Cacheability attributes of MSM IOMMU mappings */
0017 #define MSM_IOMMU_ATTR_NONCACHED    0x0
0018 #define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
0019 #define MSM_IOMMU_ATTR_CACHED_WB_NWA    0x2
0020 #define MSM_IOMMU_ATTR_CACHED_WT    0x3
0021
0022 /* Mask for the cache policy attribute */
0023 #define MSM_IOMMU_CP_MASK       0x03
0024
0025 /* Maximum number of Machine IDs that we are allowing to be mapped to the same
0026  * context bank. The number of MIDs mapped to the same CB does not affect
0027  * performance, but there is a practical limit on how many distinct MIDs may
0028  * be present. These mappings are typically determined at design time and are
0029  * not expected to change at run time.
0030  */
0031 #define MAX_NUM_MIDS    32
0032
0033 /* Maximum number of context banks that can be present in IOMMU */
0034 #define IOMMU_MAX_CBS   128
0035
0036 /**
0037  * struct msm_iommu_dev - a single IOMMU hardware instance
0038  * ncb      Number of context banks present on this IOMMU HW instance
0039  * dev:     IOMMU device
0040  * irq:     Interrupt number
0041  * clk:     The bus clock for this IOMMU hardware instance
0042  * pclk:    The clock for the IOMMU bus interconnect
0043  * dev_node:    list head in qcom_iommu_device_list
0044  * dom_node:    list head for domain
0045  * ctx_list:    list of 'struct msm_iommu_ctx_dev'
0046  * context_map: Bitmap to track allocated context banks
0047  */
0048 struct msm_iommu_dev {
0049     void __iomem *base;
0050     int ncb;
0051     struct device *dev;
0052     int irq;
0053     struct clk *clk;
0054     struct clk *pclk;
0055     struct list_head dev_node;
0056     struct list_head dom_node;
0057     struct list_head ctx_list;
0058     DECLARE_BITMAP(context_map, IOMMU_MAX_CBS);
0059
0060     struct iommu_device iommu;
0061 };
0062
0063 /**
0064  * struct msm_iommu_ctx_dev - an IOMMU context bank instance
0065  * of_node  node ptr of client device
0066  * num      Index of this context bank within the hardware
0067  * mids     List of Machine IDs that are to be mapped into this context
0068  *      bank, terminated by -1. The MID is a set of signals on the
0069  *      AXI bus that identifies the function associated with a specific
0070  *      memory request. (See ARM spec).
0071  * num_mids Total number of mids
0072  * node     list head in ctx_list
0073  */
0074 struct msm_iommu_ctx_dev {
0075     struct device_node *of_node;
0076     int num;
0077     int mids[MAX_NUM_MIDS];
0078     int num_mids;
0079     struct list_head list;
0080 };
0081
0082 /*
0083  * Interrupt handler for the IOMMU context fault interrupt. Hooking the
0084  * interrupt is not supported in the API yet, but this will print an error
0085  * message and dump useful IOMMU registers.
0086  */
0087 irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
0088
0089 #endif