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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
0003  *
0004  * Author: Stepan Moskovchenko <stepanm@codeaurora.org>
0005  */
0006 
0007 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0008 #include <linux/kernel.h>
0009 #include <linux/init.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/errno.h>
0012 #include <linux/io.h>
0013 #include <linux/io-pgtable.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/list.h>
0016 #include <linux/spinlock.h>
0017 #include <linux/slab.h>
0018 #include <linux/iommu.h>
0019 #include <linux/clk.h>
0020 #include <linux/err.h>
0021 
0022 #include <asm/cacheflush.h>
0023 #include <linux/sizes.h>
0024 
0025 #include "msm_iommu_hw-8xxx.h"
0026 #include "msm_iommu.h"
0027 
0028 #define MRC(reg, processor, op1, crn, crm, op2)             \
0029 __asm__ __volatile__ (                          \
0030 "   mrc   "   #processor "," #op1 ", %0,"  #crn "," #crm "," #op2 "\n"  \
0031 : "=r" (reg))
0032 
0033 /* bitmap of the page sizes currently supported */
0034 #define MSM_IOMMU_PGSIZES   (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
0035 
0036 static DEFINE_SPINLOCK(msm_iommu_lock);
0037 static LIST_HEAD(qcom_iommu_devices);
0038 static struct iommu_ops msm_iommu_ops;
0039 
0040 struct msm_priv {
0041     struct list_head list_attached;
0042     struct iommu_domain domain;
0043     struct io_pgtable_cfg   cfg;
0044     struct io_pgtable_ops   *iop;
0045     struct device       *dev;
0046     spinlock_t      pgtlock; /* pagetable lock */
0047 };
0048 
0049 static struct msm_priv *to_msm_priv(struct iommu_domain *dom)
0050 {
0051     return container_of(dom, struct msm_priv, domain);
0052 }
0053 
0054 static int __enable_clocks(struct msm_iommu_dev *iommu)
0055 {
0056     int ret;
0057 
0058     ret = clk_enable(iommu->pclk);
0059     if (ret)
0060         goto fail;
0061 
0062     if (iommu->clk) {
0063         ret = clk_enable(iommu->clk);
0064         if (ret)
0065             clk_disable(iommu->pclk);
0066     }
0067 fail:
0068     return ret;
0069 }
0070 
0071 static void __disable_clocks(struct msm_iommu_dev *iommu)
0072 {
0073     if (iommu->clk)
0074         clk_disable(iommu->clk);
0075     clk_disable(iommu->pclk);
0076 }
0077 
0078 static void msm_iommu_reset(void __iomem *base, int ncb)
0079 {
0080     int ctx;
0081 
0082     SET_RPUE(base, 0);
0083     SET_RPUEIE(base, 0);
0084     SET_ESRRESTORE(base, 0);
0085     SET_TBE(base, 0);
0086     SET_CR(base, 0);
0087     SET_SPDMBE(base, 0);
0088     SET_TESTBUSCR(base, 0);
0089     SET_TLBRSW(base, 0);
0090     SET_GLOBAL_TLBIALL(base, 0);
0091     SET_RPU_ACR(base, 0);
0092     SET_TLBLKCRWE(base, 1);
0093 
0094     for (ctx = 0; ctx < ncb; ctx++) {
0095         SET_BPRCOSH(base, ctx, 0);
0096         SET_BPRCISH(base, ctx, 0);
0097         SET_BPRCNSH(base, ctx, 0);
0098         SET_BPSHCFG(base, ctx, 0);
0099         SET_BPMTCFG(base, ctx, 0);
0100         SET_ACTLR(base, ctx, 0);
0101         SET_SCTLR(base, ctx, 0);
0102         SET_FSRRESTORE(base, ctx, 0);
0103         SET_TTBR0(base, ctx, 0);
0104         SET_TTBR1(base, ctx, 0);
0105         SET_TTBCR(base, ctx, 0);
0106         SET_BFBCR(base, ctx, 0);
0107         SET_PAR(base, ctx, 0);
0108         SET_FAR(base, ctx, 0);
0109         SET_CTX_TLBIALL(base, ctx, 0);
0110         SET_TLBFLPTER(base, ctx, 0);
0111         SET_TLBSLPTER(base, ctx, 0);
0112         SET_TLBLKCR(base, ctx, 0);
0113         SET_CONTEXTIDR(base, ctx, 0);
0114     }
0115 }
0116 
0117 static void __flush_iotlb(void *cookie)
0118 {
0119     struct msm_priv *priv = cookie;
0120     struct msm_iommu_dev *iommu = NULL;
0121     struct msm_iommu_ctx_dev *master;
0122     int ret = 0;
0123 
0124     list_for_each_entry(iommu, &priv->list_attached, dom_node) {
0125         ret = __enable_clocks(iommu);
0126         if (ret)
0127             goto fail;
0128 
0129         list_for_each_entry(master, &iommu->ctx_list, list)
0130             SET_CTX_TLBIALL(iommu->base, master->num, 0);
0131 
0132         __disable_clocks(iommu);
0133     }
0134 fail:
0135     return;
0136 }
0137 
0138 static void __flush_iotlb_range(unsigned long iova, size_t size,
0139                 size_t granule, bool leaf, void *cookie)
0140 {
0141     struct msm_priv *priv = cookie;
0142     struct msm_iommu_dev *iommu = NULL;
0143     struct msm_iommu_ctx_dev *master;
0144     int ret = 0;
0145     int temp_size;
0146 
0147     list_for_each_entry(iommu, &priv->list_attached, dom_node) {
0148         ret = __enable_clocks(iommu);
0149         if (ret)
0150             goto fail;
0151 
0152         list_for_each_entry(master, &iommu->ctx_list, list) {
0153             temp_size = size;
0154             do {
0155                 iova &= TLBIVA_VA;
0156                 iova |= GET_CONTEXTIDR_ASID(iommu->base,
0157                                 master->num);
0158                 SET_TLBIVA(iommu->base, master->num, iova);
0159                 iova += granule;
0160             } while (temp_size -= granule);
0161         }
0162 
0163         __disable_clocks(iommu);
0164     }
0165 
0166 fail:
0167     return;
0168 }
0169 
0170 static void __flush_iotlb_walk(unsigned long iova, size_t size,
0171                    size_t granule, void *cookie)
0172 {
0173     __flush_iotlb_range(iova, size, granule, false, cookie);
0174 }
0175 
0176 static void __flush_iotlb_page(struct iommu_iotlb_gather *gather,
0177                    unsigned long iova, size_t granule, void *cookie)
0178 {
0179     __flush_iotlb_range(iova, granule, granule, true, cookie);
0180 }
0181 
0182 static const struct iommu_flush_ops msm_iommu_flush_ops = {
0183     .tlb_flush_all = __flush_iotlb,
0184     .tlb_flush_walk = __flush_iotlb_walk,
0185     .tlb_add_page = __flush_iotlb_page,
0186 };
0187 
0188 static int msm_iommu_alloc_ctx(unsigned long *map, int start, int end)
0189 {
0190     int idx;
0191 
0192     do {
0193         idx = find_next_zero_bit(map, end, start);
0194         if (idx == end)
0195             return -ENOSPC;
0196     } while (test_and_set_bit(idx, map));
0197 
0198     return idx;
0199 }
0200 
0201 static void msm_iommu_free_ctx(unsigned long *map, int idx)
0202 {
0203     clear_bit(idx, map);
0204 }
0205 
0206 static void config_mids(struct msm_iommu_dev *iommu,
0207             struct msm_iommu_ctx_dev *master)
0208 {
0209     int mid, ctx, i;
0210 
0211     for (i = 0; i < master->num_mids; i++) {
0212         mid = master->mids[i];
0213         ctx = master->num;
0214 
0215         SET_M2VCBR_N(iommu->base, mid, 0);
0216         SET_CBACR_N(iommu->base, ctx, 0);
0217 
0218         /* Set VMID = 0 */
0219         SET_VMID(iommu->base, mid, 0);
0220 
0221         /* Set the context number for that MID to this context */
0222         SET_CBNDX(iommu->base, mid, ctx);
0223 
0224         /* Set MID associated with this context bank to 0*/
0225         SET_CBVMID(iommu->base, ctx, 0);
0226 
0227         /* Set the ASID for TLB tagging for this context */
0228         SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);
0229 
0230         /* Set security bit override to be Non-secure */
0231         SET_NSCFG(iommu->base, mid, 3);
0232     }
0233 }
0234 
0235 static void __reset_context(void __iomem *base, int ctx)
0236 {
0237     SET_BPRCOSH(base, ctx, 0);
0238     SET_BPRCISH(base, ctx, 0);
0239     SET_BPRCNSH(base, ctx, 0);
0240     SET_BPSHCFG(base, ctx, 0);
0241     SET_BPMTCFG(base, ctx, 0);
0242     SET_ACTLR(base, ctx, 0);
0243     SET_SCTLR(base, ctx, 0);
0244     SET_FSRRESTORE(base, ctx, 0);
0245     SET_TTBR0(base, ctx, 0);
0246     SET_TTBR1(base, ctx, 0);
0247     SET_TTBCR(base, ctx, 0);
0248     SET_BFBCR(base, ctx, 0);
0249     SET_PAR(base, ctx, 0);
0250     SET_FAR(base, ctx, 0);
0251     SET_CTX_TLBIALL(base, ctx, 0);
0252     SET_TLBFLPTER(base, ctx, 0);
0253     SET_TLBSLPTER(base, ctx, 0);
0254     SET_TLBLKCR(base, ctx, 0);
0255 }
0256 
0257 static void __program_context(void __iomem *base, int ctx,
0258                   struct msm_priv *priv)
0259 {
0260     __reset_context(base, ctx);
0261 
0262     /* Turn on TEX Remap */
0263     SET_TRE(base, ctx, 1);
0264     SET_AFE(base, ctx, 1);
0265 
0266     /* Set up HTW mode */
0267     /* TLB miss configuration: perform HTW on miss */
0268     SET_TLBMCFG(base, ctx, 0x3);
0269 
0270     /* V2P configuration: HTW for access */
0271     SET_V2PCFG(base, ctx, 0x3);
0272 
0273     SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr);
0274     SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr);
0275     SET_TTBR1(base, ctx, 0);
0276 
0277     /* Set prrr and nmrr */
0278     SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr);
0279     SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr);
0280 
0281     /* Invalidate the TLB for this context */
0282     SET_CTX_TLBIALL(base, ctx, 0);
0283 
0284     /* Set interrupt number to "secure" interrupt */
0285     SET_IRPTNDX(base, ctx, 0);
0286 
0287     /* Enable context fault interrupt */
0288     SET_CFEIE(base, ctx, 1);
0289 
0290     /* Stall access on a context fault and let the handler deal with it */
0291     SET_CFCFG(base, ctx, 1);
0292 
0293     /* Redirect all cacheable requests to L2 slave port. */
0294     SET_RCISH(base, ctx, 1);
0295     SET_RCOSH(base, ctx, 1);
0296     SET_RCNSH(base, ctx, 1);
0297 
0298     /* Turn on BFB prefetch */
0299     SET_BFBDFE(base, ctx, 1);
0300 
0301     /* Enable the MMU */
0302     SET_M(base, ctx, 1);
0303 }
0304 
0305 static struct iommu_domain *msm_iommu_domain_alloc(unsigned type)
0306 {
0307     struct msm_priv *priv;
0308 
0309     if (type != IOMMU_DOMAIN_UNMANAGED)
0310         return NULL;
0311 
0312     priv = kzalloc(sizeof(*priv), GFP_KERNEL);
0313     if (!priv)
0314         goto fail_nomem;
0315 
0316     INIT_LIST_HEAD(&priv->list_attached);
0317 
0318     priv->domain.geometry.aperture_start = 0;
0319     priv->domain.geometry.aperture_end   = (1ULL << 32) - 1;
0320     priv->domain.geometry.force_aperture = true;
0321 
0322     return &priv->domain;
0323 
0324 fail_nomem:
0325     kfree(priv);
0326     return NULL;
0327 }
0328 
0329 static void msm_iommu_domain_free(struct iommu_domain *domain)
0330 {
0331     struct msm_priv *priv;
0332     unsigned long flags;
0333 
0334     spin_lock_irqsave(&msm_iommu_lock, flags);
0335     priv = to_msm_priv(domain);
0336     kfree(priv);
0337     spin_unlock_irqrestore(&msm_iommu_lock, flags);
0338 }
0339 
0340 static int msm_iommu_domain_config(struct msm_priv *priv)
0341 {
0342     spin_lock_init(&priv->pgtlock);
0343 
0344     priv->cfg = (struct io_pgtable_cfg) {
0345         .pgsize_bitmap = msm_iommu_ops.pgsize_bitmap,
0346         .ias = 32,
0347         .oas = 32,
0348         .tlb = &msm_iommu_flush_ops,
0349         .iommu_dev = priv->dev,
0350     };
0351 
0352     priv->iop = alloc_io_pgtable_ops(ARM_V7S, &priv->cfg, priv);
0353     if (!priv->iop) {
0354         dev_err(priv->dev, "Failed to allocate pgtable\n");
0355         return -EINVAL;
0356     }
0357 
0358     msm_iommu_ops.pgsize_bitmap = priv->cfg.pgsize_bitmap;
0359 
0360     return 0;
0361 }
0362 
0363 /* Must be called under msm_iommu_lock */
0364 static struct msm_iommu_dev *find_iommu_for_dev(struct device *dev)
0365 {
0366     struct msm_iommu_dev *iommu, *ret = NULL;
0367     struct msm_iommu_ctx_dev *master;
0368 
0369     list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
0370         master = list_first_entry(&iommu->ctx_list,
0371                       struct msm_iommu_ctx_dev,
0372                       list);
0373         if (master->of_node == dev->of_node) {
0374             ret = iommu;
0375             break;
0376         }
0377     }
0378 
0379     return ret;
0380 }
0381 
0382 static struct iommu_device *msm_iommu_probe_device(struct device *dev)
0383 {
0384     struct msm_iommu_dev *iommu;
0385     unsigned long flags;
0386 
0387     spin_lock_irqsave(&msm_iommu_lock, flags);
0388     iommu = find_iommu_for_dev(dev);
0389     spin_unlock_irqrestore(&msm_iommu_lock, flags);
0390 
0391     if (!iommu)
0392         return ERR_PTR(-ENODEV);
0393 
0394     return &iommu->iommu;
0395 }
0396 
0397 static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
0398 {
0399     int ret = 0;
0400     unsigned long flags;
0401     struct msm_iommu_dev *iommu;
0402     struct msm_priv *priv = to_msm_priv(domain);
0403     struct msm_iommu_ctx_dev *master;
0404 
0405     priv->dev = dev;
0406     msm_iommu_domain_config(priv);
0407 
0408     spin_lock_irqsave(&msm_iommu_lock, flags);
0409     list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
0410         master = list_first_entry(&iommu->ctx_list,
0411                       struct msm_iommu_ctx_dev,
0412                       list);
0413         if (master->of_node == dev->of_node) {
0414             ret = __enable_clocks(iommu);
0415             if (ret)
0416                 goto fail;
0417 
0418             list_for_each_entry(master, &iommu->ctx_list, list) {
0419                 if (master->num) {
0420                     dev_err(dev, "domain already attached");
0421                     ret = -EEXIST;
0422                     goto fail;
0423                 }
0424                 master->num =
0425                     msm_iommu_alloc_ctx(iommu->context_map,
0426                                 0, iommu->ncb);
0427                 if (IS_ERR_VALUE(master->num)) {
0428                     ret = -ENODEV;
0429                     goto fail;
0430                 }
0431                 config_mids(iommu, master);
0432                 __program_context(iommu->base, master->num,
0433                           priv);
0434             }
0435             __disable_clocks(iommu);
0436             list_add(&iommu->dom_node, &priv->list_attached);
0437         }
0438     }
0439 
0440 fail:
0441     spin_unlock_irqrestore(&msm_iommu_lock, flags);
0442 
0443     return ret;
0444 }
0445 
0446 static void msm_iommu_detach_dev(struct iommu_domain *domain,
0447                  struct device *dev)
0448 {
0449     struct msm_priv *priv = to_msm_priv(domain);
0450     unsigned long flags;
0451     struct msm_iommu_dev *iommu;
0452     struct msm_iommu_ctx_dev *master;
0453     int ret;
0454 
0455     free_io_pgtable_ops(priv->iop);
0456 
0457     spin_lock_irqsave(&msm_iommu_lock, flags);
0458     list_for_each_entry(iommu, &priv->list_attached, dom_node) {
0459         ret = __enable_clocks(iommu);
0460         if (ret)
0461             goto fail;
0462 
0463         list_for_each_entry(master, &iommu->ctx_list, list) {
0464             msm_iommu_free_ctx(iommu->context_map, master->num);
0465             __reset_context(iommu->base, master->num);
0466         }
0467         __disable_clocks(iommu);
0468     }
0469 fail:
0470     spin_unlock_irqrestore(&msm_iommu_lock, flags);
0471 }
0472 
0473 static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova,
0474              phys_addr_t pa, size_t len, int prot, gfp_t gfp)
0475 {
0476     struct msm_priv *priv = to_msm_priv(domain);
0477     unsigned long flags;
0478     int ret;
0479 
0480     spin_lock_irqsave(&priv->pgtlock, flags);
0481     ret = priv->iop->map(priv->iop, iova, pa, len, prot, GFP_ATOMIC);
0482     spin_unlock_irqrestore(&priv->pgtlock, flags);
0483 
0484     return ret;
0485 }
0486 
0487 static void msm_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
0488                    size_t size)
0489 {
0490     struct msm_priv *priv = to_msm_priv(domain);
0491 
0492     __flush_iotlb_range(iova, size, SZ_4K, false, priv);
0493 }
0494 
0495 static size_t msm_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
0496                   size_t len, struct iommu_iotlb_gather *gather)
0497 {
0498     struct msm_priv *priv = to_msm_priv(domain);
0499     unsigned long flags;
0500 
0501     spin_lock_irqsave(&priv->pgtlock, flags);
0502     len = priv->iop->unmap(priv->iop, iova, len, gather);
0503     spin_unlock_irqrestore(&priv->pgtlock, flags);
0504 
0505     return len;
0506 }
0507 
0508 static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
0509                       dma_addr_t va)
0510 {
0511     struct msm_priv *priv;
0512     struct msm_iommu_dev *iommu;
0513     struct msm_iommu_ctx_dev *master;
0514     unsigned int par;
0515     unsigned long flags;
0516     phys_addr_t ret = 0;
0517 
0518     spin_lock_irqsave(&msm_iommu_lock, flags);
0519 
0520     priv = to_msm_priv(domain);
0521     iommu = list_first_entry(&priv->list_attached,
0522                  struct msm_iommu_dev, dom_node);
0523 
0524     if (list_empty(&iommu->ctx_list))
0525         goto fail;
0526 
0527     master = list_first_entry(&iommu->ctx_list,
0528                   struct msm_iommu_ctx_dev, list);
0529     if (!master)
0530         goto fail;
0531 
0532     ret = __enable_clocks(iommu);
0533     if (ret)
0534         goto fail;
0535 
0536     /* Invalidate context TLB */
0537     SET_CTX_TLBIALL(iommu->base, master->num, 0);
0538     SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);
0539 
0540     par = GET_PAR(iommu->base, master->num);
0541 
0542     /* We are dealing with a supersection */
0543     if (GET_NOFAULT_SS(iommu->base, master->num))
0544         ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
0545     else    /* Upper 20 bits from PAR, lower 12 from VA */
0546         ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
0547 
0548     if (GET_FAULT(iommu->base, master->num))
0549         ret = 0;
0550 
0551     __disable_clocks(iommu);
0552 fail:
0553     spin_unlock_irqrestore(&msm_iommu_lock, flags);
0554     return ret;
0555 }
0556 
0557 static void print_ctx_regs(void __iomem *base, int ctx)
0558 {
0559     unsigned int fsr = GET_FSR(base, ctx);
0560     pr_err("FAR    = %08x    PAR    = %08x\n",
0561            GET_FAR(base, ctx), GET_PAR(base, ctx));
0562     pr_err("FSR    = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
0563             (fsr & 0x02) ? "TF " : "",
0564             (fsr & 0x04) ? "AFF " : "",
0565             (fsr & 0x08) ? "APF " : "",
0566             (fsr & 0x10) ? "TLBMF " : "",
0567             (fsr & 0x20) ? "HTWDEEF " : "",
0568             (fsr & 0x40) ? "HTWSEEF " : "",
0569             (fsr & 0x80) ? "MHF " : "",
0570             (fsr & 0x10000) ? "SL " : "",
0571             (fsr & 0x40000000) ? "SS " : "",
0572             (fsr & 0x80000000) ? "MULTI " : "");
0573 
0574     pr_err("FSYNR0 = %08x    FSYNR1 = %08x\n",
0575            GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
0576     pr_err("TTBR0  = %08x    TTBR1  = %08x\n",
0577            GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
0578     pr_err("SCTLR  = %08x    ACTLR  = %08x\n",
0579            GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
0580 }
0581 
0582 static int insert_iommu_master(struct device *dev,
0583                 struct msm_iommu_dev **iommu,
0584                 struct of_phandle_args *spec)
0585 {
0586     struct msm_iommu_ctx_dev *master = dev_iommu_priv_get(dev);
0587     int sid;
0588 
0589     if (list_empty(&(*iommu)->ctx_list)) {
0590         master = kzalloc(sizeof(*master), GFP_ATOMIC);
0591         if (!master) {
0592             dev_err(dev, "Failed to allocate iommu_master\n");
0593             return -ENOMEM;
0594         }
0595         master->of_node = dev->of_node;
0596         list_add(&master->list, &(*iommu)->ctx_list);
0597         dev_iommu_priv_set(dev, master);
0598     }
0599 
0600     for (sid = 0; sid < master->num_mids; sid++)
0601         if (master->mids[sid] == spec->args[0]) {
0602             dev_warn(dev, "Stream ID 0x%x repeated; ignoring\n",
0603                  sid);
0604             return 0;
0605         }
0606 
0607     master->mids[master->num_mids++] = spec->args[0];
0608     return 0;
0609 }
0610 
0611 static int qcom_iommu_of_xlate(struct device *dev,
0612                    struct of_phandle_args *spec)
0613 {
0614     struct msm_iommu_dev *iommu = NULL, *iter;
0615     unsigned long flags;
0616     int ret = 0;
0617 
0618     spin_lock_irqsave(&msm_iommu_lock, flags);
0619     list_for_each_entry(iter, &qcom_iommu_devices, dev_node) {
0620         if (iter->dev->of_node == spec->np) {
0621             iommu = iter;
0622             break;
0623         }
0624     }
0625 
0626     if (!iommu) {
0627         ret = -ENODEV;
0628         goto fail;
0629     }
0630 
0631     ret = insert_iommu_master(dev, &iommu, spec);
0632 fail:
0633     spin_unlock_irqrestore(&msm_iommu_lock, flags);
0634 
0635     return ret;
0636 }
0637 
0638 irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
0639 {
0640     struct msm_iommu_dev *iommu = dev_id;
0641     unsigned int fsr;
0642     int i, ret;
0643 
0644     spin_lock(&msm_iommu_lock);
0645 
0646     if (!iommu) {
0647         pr_err("Invalid device ID in context interrupt handler\n");
0648         goto fail;
0649     }
0650 
0651     pr_err("Unexpected IOMMU page fault!\n");
0652     pr_err("base = %08x\n", (unsigned int)iommu->base);
0653 
0654     ret = __enable_clocks(iommu);
0655     if (ret)
0656         goto fail;
0657 
0658     for (i = 0; i < iommu->ncb; i++) {
0659         fsr = GET_FSR(iommu->base, i);
0660         if (fsr) {
0661             pr_err("Fault occurred in context %d.\n", i);
0662             pr_err("Interesting registers:\n");
0663             print_ctx_regs(iommu->base, i);
0664             SET_FSR(iommu->base, i, 0x4000000F);
0665         }
0666     }
0667     __disable_clocks(iommu);
0668 fail:
0669     spin_unlock(&msm_iommu_lock);
0670     return 0;
0671 }
0672 
0673 static struct iommu_ops msm_iommu_ops = {
0674     .domain_alloc = msm_iommu_domain_alloc,
0675     .probe_device = msm_iommu_probe_device,
0676     .device_group = generic_device_group,
0677     .pgsize_bitmap = MSM_IOMMU_PGSIZES,
0678     .of_xlate = qcom_iommu_of_xlate,
0679     .default_domain_ops = &(const struct iommu_domain_ops) {
0680         .attach_dev = msm_iommu_attach_dev,
0681         .detach_dev = msm_iommu_detach_dev,
0682         .map        = msm_iommu_map,
0683         .unmap      = msm_iommu_unmap,
0684         /*
0685          * Nothing is needed here, the barrier to guarantee
0686          * completion of the tlb sync operation is implicitly
0687          * taken care when the iommu client does a writel before
0688          * kick starting the other master.
0689          */
0690         .iotlb_sync = NULL,
0691         .iotlb_sync_map = msm_iommu_sync_map,
0692         .iova_to_phys   = msm_iommu_iova_to_phys,
0693         .free       = msm_iommu_domain_free,
0694     }
0695 };
0696 
0697 static int msm_iommu_probe(struct platform_device *pdev)
0698 {
0699     struct resource *r;
0700     resource_size_t ioaddr;
0701     struct msm_iommu_dev *iommu;
0702     int ret, par, val;
0703 
0704     iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);
0705     if (!iommu)
0706         return -ENODEV;
0707 
0708     iommu->dev = &pdev->dev;
0709     INIT_LIST_HEAD(&iommu->ctx_list);
0710 
0711     iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk");
0712     if (IS_ERR(iommu->pclk))
0713         return dev_err_probe(iommu->dev, PTR_ERR(iommu->pclk),
0714                      "could not get smmu_pclk\n");
0715 
0716     ret = clk_prepare(iommu->pclk);
0717     if (ret)
0718         return dev_err_probe(iommu->dev, ret,
0719                      "could not prepare smmu_pclk\n");
0720 
0721     iommu->clk = devm_clk_get(iommu->dev, "iommu_clk");
0722     if (IS_ERR(iommu->clk)) {
0723         clk_unprepare(iommu->pclk);
0724         return dev_err_probe(iommu->dev, PTR_ERR(iommu->clk),
0725                      "could not get iommu_clk\n");
0726     }
0727 
0728     ret = clk_prepare(iommu->clk);
0729     if (ret) {
0730         clk_unprepare(iommu->pclk);
0731         return dev_err_probe(iommu->dev, ret, "could not prepare iommu_clk\n");
0732     }
0733 
0734     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0735     iommu->base = devm_ioremap_resource(iommu->dev, r);
0736     if (IS_ERR(iommu->base)) {
0737         ret = dev_err_probe(iommu->dev, PTR_ERR(iommu->base), "could not get iommu base\n");
0738         goto fail;
0739     }
0740     ioaddr = r->start;
0741 
0742     iommu->irq = platform_get_irq(pdev, 0);
0743     if (iommu->irq < 0) {
0744         ret = -ENODEV;
0745         goto fail;
0746     }
0747 
0748     ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val);
0749     if (ret) {
0750         dev_err(iommu->dev, "could not get ncb\n");
0751         goto fail;
0752     }
0753     iommu->ncb = val;
0754 
0755     msm_iommu_reset(iommu->base, iommu->ncb);
0756     SET_M(iommu->base, 0, 1);
0757     SET_PAR(iommu->base, 0, 0);
0758     SET_V2PCFG(iommu->base, 0, 1);
0759     SET_V2PPR(iommu->base, 0, 0);
0760     par = GET_PAR(iommu->base, 0);
0761     SET_V2PCFG(iommu->base, 0, 0);
0762     SET_M(iommu->base, 0, 0);
0763 
0764     if (!par) {
0765         pr_err("Invalid PAR value detected\n");
0766         ret = -ENODEV;
0767         goto fail;
0768     }
0769 
0770     ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL,
0771                     msm_iommu_fault_handler,
0772                     IRQF_ONESHOT | IRQF_SHARED,
0773                     "msm_iommu_secure_irpt_handler",
0774                     iommu);
0775     if (ret) {
0776         pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret);
0777         goto fail;
0778     }
0779 
0780     list_add(&iommu->dev_node, &qcom_iommu_devices);
0781 
0782     ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL,
0783                      "msm-smmu.%pa", &ioaddr);
0784     if (ret) {
0785         pr_err("Could not add msm-smmu at %pa to sysfs\n", &ioaddr);
0786         goto fail;
0787     }
0788 
0789     ret = iommu_device_register(&iommu->iommu, &msm_iommu_ops, &pdev->dev);
0790     if (ret) {
0791         pr_err("Could not register msm-smmu at %pa\n", &ioaddr);
0792         goto fail;
0793     }
0794 
0795     bus_set_iommu(&platform_bus_type, &msm_iommu_ops);
0796 
0797     pr_info("device mapped at %p, irq %d with %d ctx banks\n",
0798         iommu->base, iommu->irq, iommu->ncb);
0799 
0800     return ret;
0801 fail:
0802     clk_unprepare(iommu->clk);
0803     clk_unprepare(iommu->pclk);
0804     return ret;
0805 }
0806 
0807 static const struct of_device_id msm_iommu_dt_match[] = {
0808     { .compatible = "qcom,apq8064-iommu" },
0809     {}
0810 };
0811 
0812 static int msm_iommu_remove(struct platform_device *pdev)
0813 {
0814     struct msm_iommu_dev *iommu = platform_get_drvdata(pdev);
0815 
0816     clk_unprepare(iommu->clk);
0817     clk_unprepare(iommu->pclk);
0818     return 0;
0819 }
0820 
0821 static struct platform_driver msm_iommu_driver = {
0822     .driver = {
0823         .name   = "msm_iommu",
0824         .of_match_table = msm_iommu_dt_match,
0825     },
0826     .probe      = msm_iommu_probe,
0827     .remove     = msm_iommu_remove,
0828 };
0829 builtin_platform_driver(msm_iommu_driver);
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