drivers/iommu/io-pgtable-arm-v7s.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * CPU-agnostic ARM page table allocator.
0004  *
0005  * ARMv7 Short-descriptor format, supporting
0006  * - Basic memory attributes
0007  * - Simplified access permissions (AP[2:1] model)
0008  * - Backwards-compatible TEX remap
0009  * - Large pages/supersections (if indicated by the caller)
0010  *
0011  * Not supporting:
0012  * - Legacy access permissions (AP[2:0] model)
0013  *
0014  * Almost certainly never supporting:
0015  * - PXN
0016  * - Domains
0017  *
0018  * Copyright (C) 2014-2015 ARM Limited
0019  * Copyright (c) 2014-2015 MediaTek Inc.
0020  */
0021
0022 #define pr_fmt(fmt) "arm-v7s io-pgtable: " fmt
0023
0024 #include <linux/atomic.h>
0025 #include <linux/dma-mapping.h>
0026 #include <linux/gfp.h>
0027 #include <linux/io-pgtable.h>
0028 #include <linux/iommu.h>
0029 #include <linux/kernel.h>
0030 #include <linux/kmemleak.h>
0031 #include <linux/sizes.h>
0032 #include <linux/slab.h>
0033 #include <linux/spinlock.h>
0034 #include <linux/types.h>
0035
0036 #include <asm/barrier.h>
0037
0038 /* Struct accessors */
0039 #define io_pgtable_to_data(x)                       \
0040     container_of((x), struct arm_v7s_io_pgtable, iop)
0041
0042 #define io_pgtable_ops_to_data(x)                   \
0043     io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
0044
0045 /*
0046  * We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2,
0047  * and 12 bits in a page.
0048  * MediaTek extend 2 bits to reach 34bits, 14 bits at lvl1 and 8 bits at lvl2.
0049  */
0050 #define ARM_V7S_ADDR_BITS       32
0051 #define _ARM_V7S_LVL_BITS(lvl, cfg) ((lvl) == 1 ? ((cfg)->ias - 20) : 8)
0052 #define ARM_V7S_LVL_SHIFT(lvl)      ((lvl) == 1 ? 20 : 12)
0053 #define ARM_V7S_TABLE_SHIFT     10
0054
0055 #define ARM_V7S_PTES_PER_LVL(lvl, cfg)  (1 << _ARM_V7S_LVL_BITS(lvl, cfg))
0056 #define ARM_V7S_TABLE_SIZE(lvl, cfg)                        \
0057     (ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
0058
0059 #define ARM_V7S_BLOCK_SIZE(lvl)     (1UL << ARM_V7S_LVL_SHIFT(lvl))
0060 #define ARM_V7S_LVL_MASK(lvl)       ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl)))
0061 #define ARM_V7S_TABLE_MASK      ((u32)(~0U << ARM_V7S_TABLE_SHIFT))
0062 #define _ARM_V7S_IDX_MASK(lvl, cfg) (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
0063 #define ARM_V7S_LVL_IDX(addr, lvl, cfg) ({              \
0064     int _l = lvl;                           \
0065     ((addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
0066 })
0067
0068 /*
0069  * Large page/supersection entries are effectively a block of 16 page/section
0070  * entries, along the lines of the LPAE contiguous hint, but all with the
0071  * same output address. For want of a better common name we'll call them
0072  * "contiguous" versions of their respective page/section entries here, but
0073  * noting the distinction (WRT to TLB maintenance) that they represent *one*
0074  * entry repeated 16 times, not 16 separate entries (as in the LPAE case).
0075  */
0076 #define ARM_V7S_CONT_PAGES      16
0077
0078 /* PTE type bits: these are all mixed up with XN/PXN bits in most cases */
0079 #define ARM_V7S_PTE_TYPE_TABLE      0x1
0080 #define ARM_V7S_PTE_TYPE_PAGE       0x2
0081 #define ARM_V7S_PTE_TYPE_CONT_PAGE  0x1
0082
0083 #define ARM_V7S_PTE_IS_VALID(pte)   (((pte) & 0x3) != 0)
0084 #define ARM_V7S_PTE_IS_TABLE(pte, lvl) \
0085     ((lvl) == 1 && (((pte) & 0x3) == ARM_V7S_PTE_TYPE_TABLE))
0086
0087 /* Page table bits */
0088 #define ARM_V7S_ATTR_XN(lvl)        BIT(4 * (2 - (lvl)))
0089 #define ARM_V7S_ATTR_B          BIT(2)
0090 #define ARM_V7S_ATTR_C          BIT(3)
0091 #define ARM_V7S_ATTR_NS_TABLE       BIT(3)
0092 #define ARM_V7S_ATTR_NS_SECTION     BIT(19)
0093
0094 #define ARM_V7S_CONT_SECTION        BIT(18)
0095 #define ARM_V7S_CONT_PAGE_XN_SHIFT  15
0096
0097 /*
0098  * The attribute bits are consistently ordered*, but occupy bits [17:10] of
0099  * a level 1 PTE vs. bits [11:4] at level 2. Thus we define the individual
0100  * fields relative to that 8-bit block, plus a total shift relative to the PTE.
0101  */
0102 #define ARM_V7S_ATTR_SHIFT(lvl)     (16 - (lvl) * 6)
0103
0104 #define ARM_V7S_ATTR_MASK       0xff
0105 #define ARM_V7S_ATTR_AP0        BIT(0)
0106 #define ARM_V7S_ATTR_AP1        BIT(1)
0107 #define ARM_V7S_ATTR_AP2        BIT(5)
0108 #define ARM_V7S_ATTR_S          BIT(6)
0109 #define ARM_V7S_ATTR_NG         BIT(7)
0110 #define ARM_V7S_TEX_SHIFT       2
0111 #define ARM_V7S_TEX_MASK        0x7
0112 #define ARM_V7S_ATTR_TEX(val)       (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
0113
0114 /* MediaTek extend the bits below for PA 32bit/33bit/34bit */
0115 #define ARM_V7S_ATTR_MTK_PA_BIT32   BIT(9)
0116 #define ARM_V7S_ATTR_MTK_PA_BIT33   BIT(4)
0117 #define ARM_V7S_ATTR_MTK_PA_BIT34   BIT(5)
0118
0119 /* *well, except for TEX on level 2 large pages, of course :( */
0120 #define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
0121 #define ARM_V7S_CONT_PAGE_TEX_MASK  (ARM_V7S_TEX_MASK << ARM_V7S_CONT_PAGE_TEX_SHIFT)
0122
0123 /* Simplified access permissions */
0124 #define ARM_V7S_PTE_AF          ARM_V7S_ATTR_AP0
0125 #define ARM_V7S_PTE_AP_UNPRIV       ARM_V7S_ATTR_AP1
0126 #define ARM_V7S_PTE_AP_RDONLY       ARM_V7S_ATTR_AP2
0127
0128 /* Register bits */
0129 #define ARM_V7S_RGN_NC          0
0130 #define ARM_V7S_RGN_WBWA        1
0131 #define ARM_V7S_RGN_WT          2
0132 #define ARM_V7S_RGN_WB          3
0133
0134 #define ARM_V7S_PRRR_TYPE_DEVICE    1
0135 #define ARM_V7S_PRRR_TYPE_NORMAL    2
0136 #define ARM_V7S_PRRR_TR(n, type)    (((type) & 0x3) << ((n) * 2))
0137 #define ARM_V7S_PRRR_DS0        BIT(16)
0138 #define ARM_V7S_PRRR_DS1        BIT(17)
0139 #define ARM_V7S_PRRR_NS0        BIT(18)
0140 #define ARM_V7S_PRRR_NS1        BIT(19)
0141 #define ARM_V7S_PRRR_NOS(n)     BIT((n) + 24)
0142
0143 #define ARM_V7S_NMRR_IR(n, attr)    (((attr) & 0x3) << ((n) * 2))
0144 #define ARM_V7S_NMRR_OR(n, attr)    (((attr) & 0x3) << ((n) * 2 + 16))
0145
0146 #define ARM_V7S_TTBR_S          BIT(1)
0147 #define ARM_V7S_TTBR_NOS        BIT(5)
0148 #define ARM_V7S_TTBR_ORGN_ATTR(attr)    (((attr) & 0x3) << 3)
0149 #define ARM_V7S_TTBR_IRGN_ATTR(attr)                    \
0150     ((((attr) & 0x1) << 6) | (((attr) & 0x2) >> 1))
0151
0152 #ifdef CONFIG_ZONE_DMA32
0153 #define ARM_V7S_TABLE_GFP_DMA GFP_DMA32
0154 #define ARM_V7S_TABLE_SLAB_FLAGS SLAB_CACHE_DMA32
0155 #else
0156 #define ARM_V7S_TABLE_GFP_DMA GFP_DMA
0157 #define ARM_V7S_TABLE_SLAB_FLAGS SLAB_CACHE_DMA
0158 #endif
0159
0160 typedef u32 arm_v7s_iopte;
0161
0162 static bool selftest_running;
0163
0164 struct arm_v7s_io_pgtable {
0165     struct io_pgtable   iop;
0166
0167     arm_v7s_iopte       *pgd;
0168     struct kmem_cache   *l2_tables;
0169     spinlock_t      split_lock;
0170 };
0171
0172 static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl);
0173
0174 static dma_addr_t __arm_v7s_dma_addr(void *pages)
0175 {
0176     return (dma_addr_t)virt_to_phys(pages);
0177 }
0178
0179 static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg)
0180 {
0181     return IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
0182         (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT);
0183 }
0184
0185 static arm_v7s_iopte to_mtk_iopte(phys_addr_t paddr, arm_v7s_iopte pte)
0186 {
0187     if (paddr & BIT_ULL(32))
0188         pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
0189     if (paddr & BIT_ULL(33))
0190         pte |= ARM_V7S_ATTR_MTK_PA_BIT33;
0191     if (paddr & BIT_ULL(34))
0192         pte |= ARM_V7S_ATTR_MTK_PA_BIT34;
0193     return pte;
0194 }
0195
0196 static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
0197                     struct io_pgtable_cfg *cfg)
0198 {
0199     arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl);
0200
0201     if (arm_v7s_is_mtk_enabled(cfg))
0202         return to_mtk_iopte(paddr, pte);
0203
0204     return pte;
0205 }
0206
0207 static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl,
0208                   struct io_pgtable_cfg *cfg)
0209 {
0210     arm_v7s_iopte mask;
0211     phys_addr_t paddr;
0212
0213     if (ARM_V7S_PTE_IS_TABLE(pte, lvl))
0214         mask = ARM_V7S_TABLE_MASK;
0215     else if (arm_v7s_pte_is_cont(pte, lvl))
0216         mask = ARM_V7S_LVL_MASK(lvl) * ARM_V7S_CONT_PAGES;
0217     else
0218         mask = ARM_V7S_LVL_MASK(lvl);
0219
0220     paddr = pte & mask;
0221     if (!arm_v7s_is_mtk_enabled(cfg))
0222         return paddr;
0223
0224     if (pte & ARM_V7S_ATTR_MTK_PA_BIT32)
0225         paddr |= BIT_ULL(32);
0226     if (pte & ARM_V7S_ATTR_MTK_PA_BIT33)
0227         paddr |= BIT_ULL(33);
0228     if (pte & ARM_V7S_ATTR_MTK_PA_BIT34)
0229         paddr |= BIT_ULL(34);
0230     return paddr;
0231 }
0232
0233 static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl,
0234                   struct arm_v7s_io_pgtable *data)
0235 {
0236     return phys_to_virt(iopte_to_paddr(pte, lvl, &data->iop.cfg));
0237 }
0238
0239 static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
0240                    struct arm_v7s_io_pgtable *data)
0241 {
0242     struct io_pgtable_cfg *cfg = &data->iop.cfg;
0243     struct device *dev = cfg->iommu_dev;
0244     phys_addr_t phys;
0245     dma_addr_t dma;
0246     size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
0247     void *table = NULL;
0248     gfp_t gfp_l1;
0249
0250     /*
0251      * ARM_MTK_TTBR_EXT extend the translation table base support larger
0252      * memory address.
0253      */
0254     gfp_l1 = cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
0255          GFP_KERNEL : ARM_V7S_TABLE_GFP_DMA;
0256
0257     if (lvl == 1)
0258         table = (void *)__get_free_pages(gfp_l1 | __GFP_ZERO, get_order(size));
0259     else if (lvl == 2)
0260         table = kmem_cache_zalloc(data->l2_tables, gfp);
0261
0262     if (!table)
0263         return NULL;
0264
0265     phys = virt_to_phys(table);
0266     if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
0267         phys >= (1ULL << cfg->oas) : phys != (arm_v7s_iopte)phys) {
0268         /* Doesn't fit in PTE */
0269         dev_err(dev, "Page table does not fit in PTE: %pa", &phys);
0270         goto out_free;
0271     }
0272     if (!cfg->coherent_walk) {
0273         dma = dma_map_single(dev, table, size, DMA_TO_DEVICE);
0274         if (dma_mapping_error(dev, dma))
0275             goto out_free;
0276         /*
0277          * We depend on the IOMMU being able to work with any physical
0278          * address directly, so if the DMA layer suggests otherwise by
0279          * translating or truncating them, that bodes very badly...
0280          */
0281         if (dma != phys)
0282             goto out_unmap;
0283     }
0284     if (lvl == 2)
0285         kmemleak_ignore(table);
0286     return table;
0287
0288 out_unmap:
0289     dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
0290     dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
0291 out_free:
0292     if (lvl == 1)
0293         free_pages((unsigned long)table, get_order(size));
0294     else
0295         kmem_cache_free(data->l2_tables, table);
0296     return NULL;
0297 }
0298
0299 static void __arm_v7s_free_table(void *table, int lvl,
0300                  struct arm_v7s_io_pgtable *data)
0301 {
0302     struct io_pgtable_cfg *cfg = &data->iop.cfg;
0303     struct device *dev = cfg->iommu_dev;
0304     size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
0305
0306     if (!cfg->coherent_walk)
0307         dma_unmap_single(dev, __arm_v7s_dma_addr(table), size,
0308                  DMA_TO_DEVICE);
0309     if (lvl == 1)
0310         free_pages((unsigned long)table, get_order(size));
0311     else
0312         kmem_cache_free(data->l2_tables, table);
0313 }
0314
0315 static void __arm_v7s_pte_sync(arm_v7s_iopte *ptep, int num_entries,
0316                    struct io_pgtable_cfg *cfg)
0317 {
0318     if (cfg->coherent_walk)
0319         return;
0320
0321     dma_sync_single_for_device(cfg->iommu_dev, __arm_v7s_dma_addr(ptep),
0322                    num_entries * sizeof(*ptep), DMA_TO_DEVICE);
0323 }
0324 static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
0325                   int num_entries, struct io_pgtable_cfg *cfg)
0326 {
0327     int i;
0328
0329     for (i = 0; i < num_entries; i++)
0330         ptep[i] = pte;
0331
0332     __arm_v7s_pte_sync(ptep, num_entries, cfg);
0333 }
0334
0335 static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
0336                      struct io_pgtable_cfg *cfg)
0337 {
0338     bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
0339     arm_v7s_iopte pte = ARM_V7S_ATTR_NG | ARM_V7S_ATTR_S;
0340
0341     if (!(prot & IOMMU_MMIO))
0342         pte |= ARM_V7S_ATTR_TEX(1);
0343     if (ap) {
0344         pte |= ARM_V7S_PTE_AF;
0345         if (!(prot & IOMMU_PRIV))
0346             pte |= ARM_V7S_PTE_AP_UNPRIV;
0347         if (!(prot & IOMMU_WRITE))
0348             pte |= ARM_V7S_PTE_AP_RDONLY;
0349     }
0350     pte <<= ARM_V7S_ATTR_SHIFT(lvl);
0351
0352     if ((prot & IOMMU_NOEXEC) && ap)
0353         pte |= ARM_V7S_ATTR_XN(lvl);
0354     if (prot & IOMMU_MMIO)
0355         pte |= ARM_V7S_ATTR_B;
0356     else if (prot & IOMMU_CACHE)
0357         pte |= ARM_V7S_ATTR_B | ARM_V7S_ATTR_C;
0358
0359     pte |= ARM_V7S_PTE_TYPE_PAGE;
0360     if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
0361         pte |= ARM_V7S_ATTR_NS_SECTION;
0362
0363     return pte;
0364 }
0365
0366 static int arm_v7s_pte_to_prot(arm_v7s_iopte pte, int lvl)
0367 {
0368     int prot = IOMMU_READ;
0369     arm_v7s_iopte attr = pte >> ARM_V7S_ATTR_SHIFT(lvl);
0370
0371     if (!(attr & ARM_V7S_PTE_AP_RDONLY))
0372         prot |= IOMMU_WRITE;
0373     if (!(attr & ARM_V7S_PTE_AP_UNPRIV))
0374         prot |= IOMMU_PRIV;
0375     if ((attr & (ARM_V7S_TEX_MASK << ARM_V7S_TEX_SHIFT)) == 0)
0376         prot |= IOMMU_MMIO;
0377     else if (pte & ARM_V7S_ATTR_C)
0378         prot |= IOMMU_CACHE;
0379     if (pte & ARM_V7S_ATTR_XN(lvl))
0380         prot |= IOMMU_NOEXEC;
0381
0382     return prot;
0383 }
0384
0385 static arm_v7s_iopte arm_v7s_pte_to_cont(arm_v7s_iopte pte, int lvl)
0386 {
0387     if (lvl == 1) {
0388         pte |= ARM_V7S_CONT_SECTION;
0389     } else if (lvl == 2) {
0390         arm_v7s_iopte xn = pte & ARM_V7S_ATTR_XN(lvl);
0391         arm_v7s_iopte tex = pte & ARM_V7S_CONT_PAGE_TEX_MASK;
0392
0393         pte ^= xn | tex | ARM_V7S_PTE_TYPE_PAGE;
0394         pte |= (xn << ARM_V7S_CONT_PAGE_XN_SHIFT) |
0395                (tex << ARM_V7S_CONT_PAGE_TEX_SHIFT) |
0396                ARM_V7S_PTE_TYPE_CONT_PAGE;
0397     }
0398     return pte;
0399 }
0400
0401 static arm_v7s_iopte arm_v7s_cont_to_pte(arm_v7s_iopte pte, int lvl)
0402 {
0403     if (lvl == 1) {
0404         pte &= ~ARM_V7S_CONT_SECTION;
0405     } else if (lvl == 2) {
0406         arm_v7s_iopte xn = pte & BIT(ARM_V7S_CONT_PAGE_XN_SHIFT);
0407         arm_v7s_iopte tex = pte & (ARM_V7S_CONT_PAGE_TEX_MASK <<
0408                        ARM_V7S_CONT_PAGE_TEX_SHIFT);
0409
0410         pte ^= xn | tex | ARM_V7S_PTE_TYPE_CONT_PAGE;
0411         pte |= (xn >> ARM_V7S_CONT_PAGE_XN_SHIFT) |
0412                (tex >> ARM_V7S_CONT_PAGE_TEX_SHIFT) |
0413                ARM_V7S_PTE_TYPE_PAGE;
0414     }
0415     return pte;
0416 }
0417
0418 static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl)
0419 {
0420     if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte, lvl))
0421         return pte & ARM_V7S_CONT_SECTION;
0422     else if (lvl == 2)
0423         return !(pte & ARM_V7S_PTE_TYPE_PAGE);
0424     return false;
0425 }
0426
0427 static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *,
0428                   struct iommu_iotlb_gather *, unsigned long,
0429                   size_t, int, arm_v7s_iopte *);
0430
0431 static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
0432                 unsigned long iova, phys_addr_t paddr, int prot,
0433                 int lvl, int num_entries, arm_v7s_iopte *ptep)
0434 {
0435     struct io_pgtable_cfg *cfg = &data->iop.cfg;
0436     arm_v7s_iopte pte;
0437     int i;
0438
0439     for (i = 0; i < num_entries; i++)
0440         if (ARM_V7S_PTE_IS_TABLE(ptep[i], lvl)) {
0441             /*
0442              * We need to unmap and free the old table before
0443              * overwriting it with a block entry.
0444              */
0445             arm_v7s_iopte *tblp;
0446             size_t sz = ARM_V7S_BLOCK_SIZE(lvl);
0447
0448             tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl, cfg);
0449             if (WARN_ON(__arm_v7s_unmap(data, NULL, iova + i * sz,
0450                             sz, lvl, tblp) != sz))
0451                 return -EINVAL;
0452         } else if (ptep[i]) {
0453             /* We require an unmap first */
0454             WARN_ON(!selftest_running);
0455             return -EEXIST;
0456         }
0457
0458     pte = arm_v7s_prot_to_pte(prot, lvl, cfg);
0459     if (num_entries > 1)
0460         pte = arm_v7s_pte_to_cont(pte, lvl);
0461
0462     pte |= paddr_to_iopte(paddr, lvl, cfg);
0463
0464     __arm_v7s_set_pte(ptep, pte, num_entries, cfg);
0465     return 0;
0466 }
0467
0468 static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table,
0469                        arm_v7s_iopte *ptep,
0470                        arm_v7s_iopte curr,
0471                        struct io_pgtable_cfg *cfg)
0472 {
0473     phys_addr_t phys = virt_to_phys(table);
0474     arm_v7s_iopte old, new;
0475
0476     new = phys | ARM_V7S_PTE_TYPE_TABLE;
0477
0478     if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)
0479         new = to_mtk_iopte(phys, new);
0480
0481     if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
0482         new |= ARM_V7S_ATTR_NS_TABLE;
0483
0484     /*
0485      * Ensure the table itself is visible before its PTE can be.
0486      * Whilst we could get away with cmpxchg64_release below, this
0487      * doesn't have any ordering semantics when !CONFIG_SMP.
0488      */
0489     dma_wmb();
0490
0491     old = cmpxchg_relaxed(ptep, curr, new);
0492     __arm_v7s_pte_sync(ptep, 1, cfg);
0493
0494     return old;
0495 }
0496
0497 static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova,
0498              phys_addr_t paddr, size_t size, int prot,
0499              int lvl, arm_v7s_iopte *ptep, gfp_t gfp)
0500 {
0501     struct io_pgtable_cfg *cfg = &data->iop.cfg;
0502     arm_v7s_iopte pte, *cptep;
0503     int num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
0504
0505     /* Find our entry at the current level */
0506     ptep += ARM_V7S_LVL_IDX(iova, lvl, cfg);
0507
0508     /* If we can install a leaf entry at this level, then do so */
0509     if (num_entries)
0510         return arm_v7s_init_pte(data, iova, paddr, prot,
0511                     lvl, num_entries, ptep);
0512
0513     /* We can't allocate tables at the final level */
0514     if (WARN_ON(lvl == 2))
0515         return -EINVAL;
0516
0517     /* Grab a pointer to the next level */
0518     pte = READ_ONCE(*ptep);
0519     if (!pte) {
0520         cptep = __arm_v7s_alloc_table(lvl + 1, gfp, data);
0521         if (!cptep)
0522             return -ENOMEM;
0523
0524         pte = arm_v7s_install_table(cptep, ptep, 0, cfg);
0525         if (pte)
0526             __arm_v7s_free_table(cptep, lvl + 1, data);
0527     } else {
0528         /* We've no easy way of knowing if it's synced yet, so... */
0529         __arm_v7s_pte_sync(ptep, 1, cfg);
0530     }
0531
0532     if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) {
0533         cptep = iopte_deref(pte, lvl, data);
0534     } else if (pte) {
0535         /* We require an unmap first */
0536         WARN_ON(!selftest_running);
0537         return -EEXIST;
0538     }
0539
0540     /* Rinse, repeat */
0541     return __arm_v7s_map(data, iova, paddr, size, prot, lvl + 1, cptep, gfp);
0542 }
0543
0544 static int arm_v7s_map_pages(struct io_pgtable_ops *ops, unsigned long iova,
0545                  phys_addr_t paddr, size_t pgsize, size_t pgcount,
0546                  int prot, gfp_t gfp, size_t *mapped)
0547 {
0548     struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
0549     int ret = -EINVAL;
0550
0551     if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias) ||
0552             paddr >= (1ULL << data->iop.cfg.oas)))
0553         return -ERANGE;
0554
0555     /* If no access, then nothing to do */
0556     if (!(prot & (IOMMU_READ | IOMMU_WRITE)))
0557         return 0;
0558
0559     while (pgcount--) {
0560         ret = __arm_v7s_map(data, iova, paddr, pgsize, prot, 1, data->pgd,
0561                     gfp);
0562         if (ret)
0563             break;
0564
0565         iova += pgsize;
0566         paddr += pgsize;
0567         if (mapped)
0568             *mapped += pgsize;
0569     }
0570     /*
0571      * Synchronise all PTE updates for the new mapping before there's
0572      * a chance for anything to kick off a table walk for the new iova.
0573      */
0574     wmb();
0575
0576     return ret;
0577 }
0578
0579 static int arm_v7s_map(struct io_pgtable_ops *ops, unsigned long iova,
0580                phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
0581 {
0582     return arm_v7s_map_pages(ops, iova, paddr, size, 1, prot, gfp, NULL);
0583 }
0584
0585 static void arm_v7s_free_pgtable(struct io_pgtable *iop)
0586 {
0587     struct arm_v7s_io_pgtable *data = io_pgtable_to_data(iop);
0588     int i;
0589
0590     for (i = 0; i < ARM_V7S_PTES_PER_LVL(1, &data->iop.cfg); i++) {
0591         arm_v7s_iopte pte = data->pgd[i];
0592
0593         if (ARM_V7S_PTE_IS_TABLE(pte, 1))
0594             __arm_v7s_free_table(iopte_deref(pte, 1, data),
0595                          2, data);
0596     }
0597     __arm_v7s_free_table(data->pgd, 1, data);
0598     kmem_cache_destroy(data->l2_tables);
0599     kfree(data);
0600 }
0601
0602 static arm_v7s_iopte arm_v7s_split_cont(struct arm_v7s_io_pgtable *data,
0603                     unsigned long iova, int idx, int lvl,
0604                     arm_v7s_iopte *ptep)
0605 {
0606     struct io_pgtable *iop = &data->iop;
0607     arm_v7s_iopte pte;
0608     size_t size = ARM_V7S_BLOCK_SIZE(lvl);
0609     int i;
0610
0611     /* Check that we didn't lose a race to get the lock */
0612     pte = *ptep;
0613     if (!arm_v7s_pte_is_cont(pte, lvl))
0614         return pte;
0615
0616     ptep -= idx & (ARM_V7S_CONT_PAGES - 1);
0617     pte = arm_v7s_cont_to_pte(pte, lvl);
0618     for (i = 0; i < ARM_V7S_CONT_PAGES; i++)
0619         ptep[i] = pte + i * size;
0620
0621     __arm_v7s_pte_sync(ptep, ARM_V7S_CONT_PAGES, &iop->cfg);
0622
0623     size *= ARM_V7S_CONT_PAGES;
0624     io_pgtable_tlb_flush_walk(iop, iova, size, size);
0625     return pte;
0626 }
0627
0628 static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
0629                       struct iommu_iotlb_gather *gather,
0630                       unsigned long iova, size_t size,
0631                       arm_v7s_iopte blk_pte,
0632                       arm_v7s_iopte *ptep)
0633 {
0634     struct io_pgtable_cfg *cfg = &data->iop.cfg;
0635     arm_v7s_iopte pte, *tablep;
0636     int i, unmap_idx, num_entries, num_ptes;
0637
0638     tablep = __arm_v7s_alloc_table(2, GFP_ATOMIC, data);
0639     if (!tablep)
0640         return 0; /* Bytes unmapped */
0641
0642     num_ptes = ARM_V7S_PTES_PER_LVL(2, cfg);
0643     num_entries = size >> ARM_V7S_LVL_SHIFT(2);
0644     unmap_idx = ARM_V7S_LVL_IDX(iova, 2, cfg);
0645
0646     pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
0647     if (num_entries > 1)
0648         pte = arm_v7s_pte_to_cont(pte, 2);
0649
0650     for (i = 0; i < num_ptes; i += num_entries, pte += size) {
0651         /* Unmap! */
0652         if (i == unmap_idx)
0653             continue;
0654
0655         __arm_v7s_set_pte(&tablep[i], pte, num_entries, cfg);
0656     }
0657
0658     pte = arm_v7s_install_table(tablep, ptep, blk_pte, cfg);
0659     if (pte != blk_pte) {
0660         __arm_v7s_free_table(tablep, 2, data);
0661
0662         if (!ARM_V7S_PTE_IS_TABLE(pte, 1))
0663             return 0;
0664
0665         tablep = iopte_deref(pte, 1, data);
0666         return __arm_v7s_unmap(data, gather, iova, size, 2, tablep);
0667     }
0668
0669     io_pgtable_tlb_add_page(&data->iop, gather, iova, size);
0670     return size;
0671 }
0672
0673 static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *data,
0674                   struct iommu_iotlb_gather *gather,
0675                   unsigned long iova, size_t size, int lvl,
0676                   arm_v7s_iopte *ptep)
0677 {
0678     arm_v7s_iopte pte[ARM_V7S_CONT_PAGES];
0679     struct io_pgtable *iop = &data->iop;
0680     int idx, i = 0, num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
0681
0682     /* Something went horribly wrong and we ran out of page table */
0683     if (WARN_ON(lvl > 2))
0684         return 0;
0685
0686     idx = ARM_V7S_LVL_IDX(iova, lvl, &iop->cfg);
0687     ptep += idx;
0688     do {
0689         pte[i] = READ_ONCE(ptep[i]);
0690         if (WARN_ON(!ARM_V7S_PTE_IS_VALID(pte[i])))
0691             return 0;
0692     } while (++i < num_entries);
0693
0694     /*
0695      * If we've hit a contiguous 'large page' entry at this level, it
0696      * needs splitting first, unless we're unmapping the whole lot.
0697      *
0698      * For splitting, we can't rewrite 16 PTEs atomically, and since we
0699      * can't necessarily assume TEX remap we don't have a software bit to
0700      * mark live entries being split. In practice (i.e. DMA API code), we
0701      * will never be splitting large pages anyway, so just wrap this edge
0702      * case in a lock for the sake of correctness and be done with it.
0703      */
0704     if (num_entries <= 1 && arm_v7s_pte_is_cont(pte[0], lvl)) {
0705         unsigned long flags;
0706
0707         spin_lock_irqsave(&data->split_lock, flags);
0708         pte[0] = arm_v7s_split_cont(data, iova, idx, lvl, ptep);
0709         spin_unlock_irqrestore(&data->split_lock, flags);
0710     }
0711
0712     /* If the size matches this level, we're in the right place */
0713     if (num_entries) {
0714         size_t blk_size = ARM_V7S_BLOCK_SIZE(lvl);
0715
0716         __arm_v7s_set_pte(ptep, 0, num_entries, &iop->cfg);
0717
0718         for (i = 0; i < num_entries; i++) {
0719             if (ARM_V7S_PTE_IS_TABLE(pte[i], lvl)) {
0720                 /* Also flush any partial walks */
0721                 io_pgtable_tlb_flush_walk(iop, iova, blk_size,
0722                         ARM_V7S_BLOCK_SIZE(lvl + 1));
0723                 ptep = iopte_deref(pte[i], lvl, data);
0724                 __arm_v7s_free_table(ptep, lvl + 1, data);
0725             } else if (!iommu_iotlb_gather_queued(gather)) {
0726                 io_pgtable_tlb_add_page(iop, gather, iova, blk_size);
0727             }
0728             iova += blk_size;
0729         }
0730         return size;
0731     } else if (lvl == 1 && !ARM_V7S_PTE_IS_TABLE(pte[0], lvl)) {
0732         /*
0733          * Insert a table at the next level to map the old region,
0734          * minus the part we want to unmap
0735          */
0736         return arm_v7s_split_blk_unmap(data, gather, iova, size, pte[0],
0737                            ptep);
0738     }
0739
0740     /* Keep on walkin' */
0741     ptep = iopte_deref(pte[0], lvl, data);
0742     return __arm_v7s_unmap(data, gather, iova, size, lvl + 1, ptep);
0743 }
0744
0745 static size_t arm_v7s_unmap_pages(struct io_pgtable_ops *ops, unsigned long iova,
0746                   size_t pgsize, size_t pgcount,
0747                   struct iommu_iotlb_gather *gather)
0748 {
0749     struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
0750     size_t unmapped = 0, ret;
0751
0752     if (WARN_ON(iova >= (1ULL << data->iop.cfg.ias)))
0753         return 0;
0754
0755     while (pgcount--) {
0756         ret = __arm_v7s_unmap(data, gather, iova, pgsize, 1, data->pgd);
0757         if (!ret)
0758             break;
0759
0760         unmapped += pgsize;
0761         iova += pgsize;
0762     }
0763
0764     return unmapped;
0765 }
0766
0767 static size_t arm_v7s_unmap(struct io_pgtable_ops *ops, unsigned long iova,
0768                 size_t size, struct iommu_iotlb_gather *gather)
0769 {
0770     return arm_v7s_unmap_pages(ops, iova, size, 1, gather);
0771 }
0772
0773 static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
0774                     unsigned long iova)
0775 {
0776     struct arm_v7s_io_pgtable *data = io_pgtable_ops_to_data(ops);
0777     arm_v7s_iopte *ptep = data->pgd, pte;
0778     int lvl = 0;
0779     u32 mask;
0780
0781     do {
0782         ptep += ARM_V7S_LVL_IDX(iova, ++lvl, &data->iop.cfg);
0783         pte = READ_ONCE(*ptep);
0784         ptep = iopte_deref(pte, lvl, data);
0785     } while (ARM_V7S_PTE_IS_TABLE(pte, lvl));
0786
0787     if (!ARM_V7S_PTE_IS_VALID(pte))
0788         return 0;
0789
0790     mask = ARM_V7S_LVL_MASK(lvl);
0791     if (arm_v7s_pte_is_cont(pte, lvl))
0792         mask *= ARM_V7S_CONT_PAGES;
0793     return iopte_to_paddr(pte, lvl, &data->iop.cfg) | (iova & ~mask);
0794 }
0795
0796 static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
0797                         void *cookie)
0798 {
0799     struct arm_v7s_io_pgtable *data;
0800     slab_flags_t slab_flag;
0801     phys_addr_t paddr;
0802
0803     if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
0804         return NULL;
0805
0806     if (cfg->oas > (arm_v7s_is_mtk_enabled(cfg) ? 35 : ARM_V7S_ADDR_BITS))
0807         return NULL;
0808
0809     if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
0810                 IO_PGTABLE_QUIRK_NO_PERMS |
0811                 IO_PGTABLE_QUIRK_ARM_MTK_EXT |
0812                 IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT))
0813         return NULL;
0814
0815     /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
0816     if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT &&
0817         !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
0818             return NULL;
0819
0820     if ((cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) &&
0821         !arm_v7s_is_mtk_enabled(cfg))
0822         return NULL;
0823
0824     data = kmalloc(sizeof(*data), GFP_KERNEL);
0825     if (!data)
0826         return NULL;
0827
0828     spin_lock_init(&data->split_lock);
0829
0830     /*
0831      * ARM_MTK_TTBR_EXT extend the translation table base support larger
0832      * memory address.
0833      */
0834     slab_flag = cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
0835             0 : ARM_V7S_TABLE_SLAB_FLAGS;
0836
0837     data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
0838                         ARM_V7S_TABLE_SIZE(2, cfg),
0839                         ARM_V7S_TABLE_SIZE(2, cfg),
0840                         slab_flag, NULL);
0841     if (!data->l2_tables)
0842         goto out_free_data;
0843
0844     data->iop.ops = (struct io_pgtable_ops) {
0845         .map        = arm_v7s_map,
0846         .map_pages  = arm_v7s_map_pages,
0847         .unmap      = arm_v7s_unmap,
0848         .unmap_pages    = arm_v7s_unmap_pages,
0849         .iova_to_phys   = arm_v7s_iova_to_phys,
0850     };
0851
0852     /* We have to do this early for __arm_v7s_alloc_table to work... */
0853     data->iop.cfg = *cfg;
0854
0855     /*
0856      * Unless the IOMMU driver indicates supersection support by
0857      * having SZ_16M set in the initial bitmap, they won't be used.
0858      */
0859     cfg->pgsize_bitmap &= SZ_4K | SZ_64K | SZ_1M | SZ_16M;
0860
0861     /* TCR: T0SZ=0, EAE=0 (if applicable) */
0862     cfg->arm_v7s_cfg.tcr = 0;
0863
0864     /*
0865      * TEX remap: the indices used map to the closest equivalent types
0866      * under the non-TEX-remap interpretation of those attribute bits,
0867      * excepting various implementation-defined aspects of shareability.
0868      */
0869     cfg->arm_v7s_cfg.prrr = ARM_V7S_PRRR_TR(1, ARM_V7S_PRRR_TYPE_DEVICE) |
0870                 ARM_V7S_PRRR_TR(4, ARM_V7S_PRRR_TYPE_NORMAL) |
0871                 ARM_V7S_PRRR_TR(7, ARM_V7S_PRRR_TYPE_NORMAL) |
0872                 ARM_V7S_PRRR_DS0 | ARM_V7S_PRRR_DS1 |
0873                 ARM_V7S_PRRR_NS1 | ARM_V7S_PRRR_NOS(7);
0874     cfg->arm_v7s_cfg.nmrr = ARM_V7S_NMRR_IR(7, ARM_V7S_RGN_WBWA) |
0875                 ARM_V7S_NMRR_OR(7, ARM_V7S_RGN_WBWA);
0876
0877     /* Looking good; allocate a pgd */
0878     data->pgd = __arm_v7s_alloc_table(1, GFP_KERNEL, data);
0879     if (!data->pgd)
0880         goto out_free_data;
0881
0882     /* Ensure the empty pgd is visible before any actual TTBR write */
0883     wmb();
0884
0885     /* TTBR */
0886     paddr = virt_to_phys(data->pgd);
0887     if (arm_v7s_is_mtk_enabled(cfg))
0888         cfg->arm_v7s_cfg.ttbr = paddr | upper_32_bits(paddr);
0889     else
0890         cfg->arm_v7s_cfg.ttbr = paddr | ARM_V7S_TTBR_S |
0891                     (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS |
0892                      ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
0893                      ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
0894                     (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
0895                      ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
0896     return &data->iop;
0897
0898 out_free_data:
0899     kmem_cache_destroy(data->l2_tables);
0900     kfree(data);
0901     return NULL;
0902 }
0903
0904 struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns = {
0905     .alloc  = arm_v7s_alloc_pgtable,
0906     .free   = arm_v7s_free_pgtable,
0907 };
0908
0909 #ifdef CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST
0910
0911 static struct io_pgtable_cfg *cfg_cookie __initdata;
0912
0913 static void __init dummy_tlb_flush_all(void *cookie)
0914 {
0915     WARN_ON(cookie != cfg_cookie);
0916 }
0917
0918 static void __init dummy_tlb_flush(unsigned long iova, size_t size,
0919                    size_t granule, void *cookie)
0920 {
0921     WARN_ON(cookie != cfg_cookie);
0922     WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
0923 }
0924
0925 static void __init dummy_tlb_add_page(struct iommu_iotlb_gather *gather,
0926                       unsigned long iova, size_t granule,
0927                       void *cookie)
0928 {
0929     dummy_tlb_flush(iova, granule, granule, cookie);
0930 }
0931
0932 static const struct iommu_flush_ops dummy_tlb_ops __initconst = {
0933     .tlb_flush_all  = dummy_tlb_flush_all,
0934     .tlb_flush_walk = dummy_tlb_flush,
0935     .tlb_add_page   = dummy_tlb_add_page,
0936 };
0937
0938 #define __FAIL(ops) ({              \
0939         WARN(1, "selftest: test failed\n"); \
0940         selftest_running = false;       \
0941         -EFAULT;                \
0942 })
0943
0944 static int __init arm_v7s_do_selftests(void)
0945 {
0946     struct io_pgtable_ops *ops;
0947     struct io_pgtable_cfg cfg = {
0948         .tlb = &dummy_tlb_ops,
0949         .oas = 32,
0950         .ias = 32,
0951         .coherent_walk = true,
0952         .quirks = IO_PGTABLE_QUIRK_ARM_NS,
0953         .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
0954     };
0955     unsigned int iova, size, iova_start;
0956     unsigned int i, loopnr = 0;
0957
0958     selftest_running = true;
0959
0960     cfg_cookie = &cfg;
0961
0962     ops = alloc_io_pgtable_ops(ARM_V7S, &cfg, &cfg);
0963     if (!ops) {
0964         pr_err("selftest: failed to allocate io pgtable ops\n");
0965         return -EINVAL;
0966     }
0967
0968     /*
0969      * Initial sanity checks.
0970      * Empty page tables shouldn't provide any translations.
0971      */
0972     if (ops->iova_to_phys(ops, 42))
0973         return __FAIL(ops);
0974
0975     if (ops->iova_to_phys(ops, SZ_1G + 42))
0976         return __FAIL(ops);
0977
0978     if (ops->iova_to_phys(ops, SZ_2G + 42))
0979         return __FAIL(ops);
0980
0981     /*
0982      * Distinct mappings of different granule sizes.
0983      */
0984     iova = 0;
0985     for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) {
0986         size = 1UL << i;
0987         if (ops->map(ops, iova, iova, size, IOMMU_READ |
0988                             IOMMU_WRITE |
0989                             IOMMU_NOEXEC |
0990                             IOMMU_CACHE, GFP_KERNEL))
0991             return __FAIL(ops);
0992
0993         /* Overlapping mappings */
0994         if (!ops->map(ops, iova, iova + size, size,
0995                   IOMMU_READ | IOMMU_NOEXEC, GFP_KERNEL))
0996             return __FAIL(ops);
0997
0998         if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
0999             return __FAIL(ops);
1000
1001         iova += SZ_16M;
1002         loopnr++;
1003     }
1004
1005     /* Partial unmap */
1006     i = 1;
1007     size = 1UL << __ffs(cfg.pgsize_bitmap);
1008     while (i < loopnr) {
1009         iova_start = i * SZ_16M;
1010         if (ops->unmap(ops, iova_start + size, size, NULL) != size)
1011             return __FAIL(ops);
1012
1013         /* Remap of partial unmap */
1014         if (ops->map(ops, iova_start + size, size, size, IOMMU_READ, GFP_KERNEL))
1015             return __FAIL(ops);
1016
1017         if (ops->iova_to_phys(ops, iova_start + size + 42)
1018             != (size + 42))
1019             return __FAIL(ops);
1020         i++;
1021     }
1022
1023     /* Full unmap */
1024     iova = 0;
1025     for_each_set_bit(i, &cfg.pgsize_bitmap, BITS_PER_LONG) {
1026         size = 1UL << i;
1027
1028         if (ops->unmap(ops, iova, size, NULL) != size)
1029             return __FAIL(ops);
1030
1031         if (ops->iova_to_phys(ops, iova + 42))
1032             return __FAIL(ops);
1033
1034         /* Remap full block */
1035         if (ops->map(ops, iova, iova, size, IOMMU_WRITE, GFP_KERNEL))
1036             return __FAIL(ops);
1037
1038         if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1039             return __FAIL(ops);
1040
1041         iova += SZ_16M;
1042     }
1043
1044     free_io_pgtable_ops(ops);
1045
1046     selftest_running = false;
1047
1048     pr_info("self test ok\n");
1049     return 0;
1050 }
1051 subsys_initcall(arm_v7s_do_selftests);
1052 #endif