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0001 // SPDX-License-Identifier: GPL-2.0
0002 
0003 #define pr_fmt(fmt)     "DMAR-IR: " fmt
0004 
0005 #include <linux/interrupt.h>
0006 #include <linux/dmar.h>
0007 #include <linux/spinlock.h>
0008 #include <linux/slab.h>
0009 #include <linux/jiffies.h>
0010 #include <linux/hpet.h>
0011 #include <linux/pci.h>
0012 #include <linux/irq.h>
0013 #include <linux/acpi.h>
0014 #include <linux/irqdomain.h>
0015 #include <linux/crash_dump.h>
0016 #include <asm/io_apic.h>
0017 #include <asm/apic.h>
0018 #include <asm/smp.h>
0019 #include <asm/cpu.h>
0020 #include <asm/irq_remapping.h>
0021 #include <asm/pci-direct.h>
0022 
0023 #include "iommu.h"
0024 #include "../irq_remapping.h"
0025 #include "cap_audit.h"
0026 
0027 enum irq_mode {
0028     IRQ_REMAPPING,
0029     IRQ_POSTING,
0030 };
0031 
0032 struct ioapic_scope {
0033     struct intel_iommu *iommu;
0034     unsigned int id;
0035     unsigned int bus;   /* PCI bus number */
0036     unsigned int devfn; /* PCI devfn number */
0037 };
0038 
0039 struct hpet_scope {
0040     struct intel_iommu *iommu;
0041     u8 id;
0042     unsigned int bus;
0043     unsigned int devfn;
0044 };
0045 
0046 struct irq_2_iommu {
0047     struct intel_iommu *iommu;
0048     u16 irte_index;
0049     u16 sub_handle;
0050     u8  irte_mask;
0051     enum irq_mode mode;
0052 };
0053 
0054 struct intel_ir_data {
0055     struct irq_2_iommu          irq_2_iommu;
0056     struct irte             irte_entry;
0057     union {
0058         struct msi_msg          msi_entry;
0059     };
0060 };
0061 
0062 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
0063 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
0064 
0065 static int __read_mostly eim_mode;
0066 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
0067 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
0068 
0069 /*
0070  * Lock ordering:
0071  * ->dmar_global_lock
0072  *  ->irq_2_ir_lock
0073  *      ->qi->q_lock
0074  *  ->iommu->register_lock
0075  * Note:
0076  * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
0077  * in single-threaded environment with interrupt disabled, so no need to tabke
0078  * the dmar_global_lock.
0079  */
0080 DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
0081 static const struct irq_domain_ops intel_ir_domain_ops;
0082 
0083 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
0084 static int __init parse_ioapics_under_ir(void);
0085 
0086 static bool ir_pre_enabled(struct intel_iommu *iommu)
0087 {
0088     return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
0089 }
0090 
0091 static void clear_ir_pre_enabled(struct intel_iommu *iommu)
0092 {
0093     iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
0094 }
0095 
0096 static void init_ir_status(struct intel_iommu *iommu)
0097 {
0098     u32 gsts;
0099 
0100     gsts = readl(iommu->reg + DMAR_GSTS_REG);
0101     if (gsts & DMA_GSTS_IRES)
0102         iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
0103 }
0104 
0105 static int alloc_irte(struct intel_iommu *iommu,
0106               struct irq_2_iommu *irq_iommu, u16 count)
0107 {
0108     struct ir_table *table = iommu->ir_table;
0109     unsigned int mask = 0;
0110     unsigned long flags;
0111     int index;
0112 
0113     if (!count || !irq_iommu)
0114         return -1;
0115 
0116     if (count > 1) {
0117         count = __roundup_pow_of_two(count);
0118         mask = ilog2(count);
0119     }
0120 
0121     if (mask > ecap_max_handle_mask(iommu->ecap)) {
0122         pr_err("Requested mask %x exceeds the max invalidation handle"
0123                " mask value %Lx\n", mask,
0124                ecap_max_handle_mask(iommu->ecap));
0125         return -1;
0126     }
0127 
0128     raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
0129     index = bitmap_find_free_region(table->bitmap,
0130                     INTR_REMAP_TABLE_ENTRIES, mask);
0131     if (index < 0) {
0132         pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
0133     } else {
0134         irq_iommu->iommu = iommu;
0135         irq_iommu->irte_index =  index;
0136         irq_iommu->sub_handle = 0;
0137         irq_iommu->irte_mask = mask;
0138         irq_iommu->mode = IRQ_REMAPPING;
0139     }
0140     raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
0141 
0142     return index;
0143 }
0144 
0145 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
0146 {
0147     struct qi_desc desc;
0148 
0149     desc.qw0 = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
0150            | QI_IEC_SELECTIVE;
0151     desc.qw1 = 0;
0152     desc.qw2 = 0;
0153     desc.qw3 = 0;
0154 
0155     return qi_submit_sync(iommu, &desc, 1, 0);
0156 }
0157 
0158 static int modify_irte(struct irq_2_iommu *irq_iommu,
0159                struct irte *irte_modified)
0160 {
0161     struct intel_iommu *iommu;
0162     unsigned long flags;
0163     struct irte *irte;
0164     int rc, index;
0165 
0166     if (!irq_iommu)
0167         return -1;
0168 
0169     raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
0170 
0171     iommu = irq_iommu->iommu;
0172 
0173     index = irq_iommu->irte_index + irq_iommu->sub_handle;
0174     irte = &iommu->ir_table->base[index];
0175 
0176 #if defined(CONFIG_HAVE_CMPXCHG_DOUBLE)
0177     if ((irte->pst == 1) || (irte_modified->pst == 1)) {
0178         bool ret;
0179 
0180         ret = cmpxchg_double(&irte->low, &irte->high,
0181                      irte->low, irte->high,
0182                      irte_modified->low, irte_modified->high);
0183         /*
0184          * We use cmpxchg16 to atomically update the 128-bit IRTE,
0185          * and it cannot be updated by the hardware or other processors
0186          * behind us, so the return value of cmpxchg16 should be the
0187          * same as the old value.
0188          */
0189         WARN_ON(!ret);
0190     } else
0191 #endif
0192     {
0193         set_64bit(&irte->low, irte_modified->low);
0194         set_64bit(&irte->high, irte_modified->high);
0195     }
0196     __iommu_flush_cache(iommu, irte, sizeof(*irte));
0197 
0198     rc = qi_flush_iec(iommu, index, 0);
0199 
0200     /* Update iommu mode according to the IRTE mode */
0201     irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
0202     raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
0203 
0204     return rc;
0205 }
0206 
0207 static struct intel_iommu *map_hpet_to_iommu(u8 hpet_id)
0208 {
0209     int i;
0210 
0211     for (i = 0; i < MAX_HPET_TBS; i++) {
0212         if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
0213             return ir_hpet[i].iommu;
0214     }
0215     return NULL;
0216 }
0217 
0218 static struct intel_iommu *map_ioapic_to_iommu(int apic)
0219 {
0220     int i;
0221 
0222     for (i = 0; i < MAX_IO_APICS; i++) {
0223         if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
0224             return ir_ioapic[i].iommu;
0225     }
0226     return NULL;
0227 }
0228 
0229 static struct irq_domain *map_dev_to_ir(struct pci_dev *dev)
0230 {
0231     struct dmar_drhd_unit *drhd = dmar_find_matched_drhd_unit(dev);
0232 
0233     return drhd ? drhd->iommu->ir_msi_domain : NULL;
0234 }
0235 
0236 static int clear_entries(struct irq_2_iommu *irq_iommu)
0237 {
0238     struct irte *start, *entry, *end;
0239     struct intel_iommu *iommu;
0240     int index;
0241 
0242     if (irq_iommu->sub_handle)
0243         return 0;
0244 
0245     iommu = irq_iommu->iommu;
0246     index = irq_iommu->irte_index;
0247 
0248     start = iommu->ir_table->base + index;
0249     end = start + (1 << irq_iommu->irte_mask);
0250 
0251     for (entry = start; entry < end; entry++) {
0252         set_64bit(&entry->low, 0);
0253         set_64bit(&entry->high, 0);
0254     }
0255     bitmap_release_region(iommu->ir_table->bitmap, index,
0256                   irq_iommu->irte_mask);
0257 
0258     return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
0259 }
0260 
0261 /*
0262  * source validation type
0263  */
0264 #define SVT_NO_VERIFY       0x0  /* no verification is required */
0265 #define SVT_VERIFY_SID_SQ   0x1  /* verify using SID and SQ fields */
0266 #define SVT_VERIFY_BUS      0x2  /* verify bus of request-id */
0267 
0268 /*
0269  * source-id qualifier
0270  */
0271 #define SQ_ALL_16   0x0  /* verify all 16 bits of request-id */
0272 #define SQ_13_IGNORE_1  0x1  /* verify most significant 13 bits, ignore
0273                   * the third least significant bit
0274                   */
0275 #define SQ_13_IGNORE_2  0x2  /* verify most significant 13 bits, ignore
0276                   * the second and third least significant bits
0277                   */
0278 #define SQ_13_IGNORE_3  0x3  /* verify most significant 13 bits, ignore
0279                   * the least three significant bits
0280                   */
0281 
0282 /*
0283  * set SVT, SQ and SID fields of irte to verify
0284  * source ids of interrupt requests
0285  */
0286 static void set_irte_sid(struct irte *irte, unsigned int svt,
0287              unsigned int sq, unsigned int sid)
0288 {
0289     if (disable_sourceid_checking)
0290         svt = SVT_NO_VERIFY;
0291     irte->svt = svt;
0292     irte->sq = sq;
0293     irte->sid = sid;
0294 }
0295 
0296 /*
0297  * Set an IRTE to match only the bus number. Interrupt requests that reference
0298  * this IRTE must have a requester-id whose bus number is between or equal
0299  * to the start_bus and end_bus arguments.
0300  */
0301 static void set_irte_verify_bus(struct irte *irte, unsigned int start_bus,
0302                 unsigned int end_bus)
0303 {
0304     set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
0305              (start_bus << 8) | end_bus);
0306 }
0307 
0308 static int set_ioapic_sid(struct irte *irte, int apic)
0309 {
0310     int i;
0311     u16 sid = 0;
0312 
0313     if (!irte)
0314         return -1;
0315 
0316     down_read(&dmar_global_lock);
0317     for (i = 0; i < MAX_IO_APICS; i++) {
0318         if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
0319             sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
0320             break;
0321         }
0322     }
0323     up_read(&dmar_global_lock);
0324 
0325     if (sid == 0) {
0326         pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
0327         return -1;
0328     }
0329 
0330     set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
0331 
0332     return 0;
0333 }
0334 
0335 static int set_hpet_sid(struct irte *irte, u8 id)
0336 {
0337     int i;
0338     u16 sid = 0;
0339 
0340     if (!irte)
0341         return -1;
0342 
0343     down_read(&dmar_global_lock);
0344     for (i = 0; i < MAX_HPET_TBS; i++) {
0345         if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
0346             sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
0347             break;
0348         }
0349     }
0350     up_read(&dmar_global_lock);
0351 
0352     if (sid == 0) {
0353         pr_warn("Failed to set source-id of HPET block (%d)\n", id);
0354         return -1;
0355     }
0356 
0357     /*
0358      * Should really use SQ_ALL_16. Some platforms are broken.
0359      * While we figure out the right quirks for these broken platforms, use
0360      * SQ_13_IGNORE_3 for now.
0361      */
0362     set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
0363 
0364     return 0;
0365 }
0366 
0367 struct set_msi_sid_data {
0368     struct pci_dev *pdev;
0369     u16 alias;
0370     int count;
0371     int busmatch_count;
0372 };
0373 
0374 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
0375 {
0376     struct set_msi_sid_data *data = opaque;
0377 
0378     if (data->count == 0 || PCI_BUS_NUM(alias) == PCI_BUS_NUM(data->alias))
0379         data->busmatch_count++;
0380 
0381     data->pdev = pdev;
0382     data->alias = alias;
0383     data->count++;
0384 
0385     return 0;
0386 }
0387 
0388 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
0389 {
0390     struct set_msi_sid_data data;
0391 
0392     if (!irte || !dev)
0393         return -1;
0394 
0395     data.count = 0;
0396     data.busmatch_count = 0;
0397     pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
0398 
0399     /*
0400      * DMA alias provides us with a PCI device and alias.  The only case
0401      * where the it will return an alias on a different bus than the
0402      * device is the case of a PCIe-to-PCI bridge, where the alias is for
0403      * the subordinate bus.  In this case we can only verify the bus.
0404      *
0405      * If there are multiple aliases, all with the same bus number,
0406      * then all we can do is verify the bus. This is typical in NTB
0407      * hardware which use proxy IDs where the device will generate traffic
0408      * from multiple devfn numbers on the same bus.
0409      *
0410      * If the alias device is on a different bus than our source device
0411      * then we have a topology based alias, use it.
0412      *
0413      * Otherwise, the alias is for a device DMA quirk and we cannot
0414      * assume that MSI uses the same requester ID.  Therefore use the
0415      * original device.
0416      */
0417     if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
0418         set_irte_verify_bus(irte, PCI_BUS_NUM(data.alias),
0419                     dev->bus->number);
0420     else if (data.count >= 2 && data.busmatch_count == data.count)
0421         set_irte_verify_bus(irte, dev->bus->number, dev->bus->number);
0422     else if (data.pdev->bus->number != dev->bus->number)
0423         set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
0424     else
0425         set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
0426                  pci_dev_id(dev));
0427 
0428     return 0;
0429 }
0430 
0431 static int iommu_load_old_irte(struct intel_iommu *iommu)
0432 {
0433     struct irte *old_ir_table;
0434     phys_addr_t irt_phys;
0435     unsigned int i;
0436     size_t size;
0437     u64 irta;
0438 
0439     /* Check whether the old ir-table has the same size as ours */
0440     irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
0441     if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
0442          != INTR_REMAP_TABLE_REG_SIZE)
0443         return -EINVAL;
0444 
0445     irt_phys = irta & VTD_PAGE_MASK;
0446     size     = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
0447 
0448     /* Map the old IR table */
0449     old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
0450     if (!old_ir_table)
0451         return -ENOMEM;
0452 
0453     /* Copy data over */
0454     memcpy(iommu->ir_table->base, old_ir_table, size);
0455 
0456     __iommu_flush_cache(iommu, iommu->ir_table->base, size);
0457 
0458     /*
0459      * Now check the table for used entries and mark those as
0460      * allocated in the bitmap
0461      */
0462     for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
0463         if (iommu->ir_table->base[i].present)
0464             bitmap_set(iommu->ir_table->bitmap, i, 1);
0465     }
0466 
0467     memunmap(old_ir_table);
0468 
0469     return 0;
0470 }
0471 
0472 
0473 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
0474 {
0475     unsigned long flags;
0476     u64 addr;
0477     u32 sts;
0478 
0479     addr = virt_to_phys((void *)iommu->ir_table->base);
0480 
0481     raw_spin_lock_irqsave(&iommu->register_lock, flags);
0482 
0483     dmar_writeq(iommu->reg + DMAR_IRTA_REG,
0484             (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
0485 
0486     /* Set interrupt-remapping table pointer */
0487     writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
0488 
0489     IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
0490               readl, (sts & DMA_GSTS_IRTPS), sts);
0491     raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
0492 
0493     /*
0494      * Global invalidation of interrupt entry cache to make sure the
0495      * hardware uses the new irq remapping table.
0496      */
0497     qi_global_iec(iommu);
0498 }
0499 
0500 static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
0501 {
0502     unsigned long flags;
0503     u32 sts;
0504 
0505     raw_spin_lock_irqsave(&iommu->register_lock, flags);
0506 
0507     /* Enable interrupt-remapping */
0508     iommu->gcmd |= DMA_GCMD_IRE;
0509     writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
0510     IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
0511               readl, (sts & DMA_GSTS_IRES), sts);
0512 
0513     /* Block compatibility-format MSIs */
0514     if (sts & DMA_GSTS_CFIS) {
0515         iommu->gcmd &= ~DMA_GCMD_CFI;
0516         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
0517         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
0518                   readl, !(sts & DMA_GSTS_CFIS), sts);
0519     }
0520 
0521     /*
0522      * With CFI clear in the Global Command register, we should be
0523      * protected from dangerous (i.e. compatibility) interrupts
0524      * regardless of x2apic status.  Check just to be sure.
0525      */
0526     if (sts & DMA_GSTS_CFIS)
0527         WARN(1, KERN_WARNING
0528             "Compatibility-format IRQs enabled despite intr remapping;\n"
0529             "you are vulnerable to IRQ injection.\n");
0530 
0531     raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
0532 }
0533 
0534 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
0535 {
0536     struct ir_table *ir_table;
0537     struct fwnode_handle *fn;
0538     unsigned long *bitmap;
0539     struct page *pages;
0540 
0541     if (iommu->ir_table)
0542         return 0;
0543 
0544     ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
0545     if (!ir_table)
0546         return -ENOMEM;
0547 
0548     pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
0549                  INTR_REMAP_PAGE_ORDER);
0550     if (!pages) {
0551         pr_err("IR%d: failed to allocate pages of order %d\n",
0552                iommu->seq_id, INTR_REMAP_PAGE_ORDER);
0553         goto out_free_table;
0554     }
0555 
0556     bitmap = bitmap_zalloc(INTR_REMAP_TABLE_ENTRIES, GFP_ATOMIC);
0557     if (bitmap == NULL) {
0558         pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
0559         goto out_free_pages;
0560     }
0561 
0562     fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id);
0563     if (!fn)
0564         goto out_free_bitmap;
0565 
0566     iommu->ir_domain =
0567         irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
0568                         0, INTR_REMAP_TABLE_ENTRIES,
0569                         fn, &intel_ir_domain_ops,
0570                         iommu);
0571     if (!iommu->ir_domain) {
0572         pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
0573         goto out_free_fwnode;
0574     }
0575     iommu->ir_msi_domain =
0576         arch_create_remap_msi_irq_domain(iommu->ir_domain,
0577                          "INTEL-IR-MSI",
0578                          iommu->seq_id);
0579 
0580     ir_table->base = page_address(pages);
0581     ir_table->bitmap = bitmap;
0582     iommu->ir_table = ir_table;
0583 
0584     /*
0585      * If the queued invalidation is already initialized,
0586      * shouldn't disable it.
0587      */
0588     if (!iommu->qi) {
0589         /*
0590          * Clear previous faults.
0591          */
0592         dmar_fault(-1, iommu);
0593         dmar_disable_qi(iommu);
0594 
0595         if (dmar_enable_qi(iommu)) {
0596             pr_err("Failed to enable queued invalidation\n");
0597             goto out_free_ir_domain;
0598         }
0599     }
0600 
0601     init_ir_status(iommu);
0602 
0603     if (ir_pre_enabled(iommu)) {
0604         if (!is_kdump_kernel()) {
0605             pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
0606                 iommu->name);
0607             clear_ir_pre_enabled(iommu);
0608             iommu_disable_irq_remapping(iommu);
0609         } else if (iommu_load_old_irte(iommu))
0610             pr_err("Failed to copy IR table for %s from previous kernel\n",
0611                    iommu->name);
0612         else
0613             pr_info("Copied IR table for %s from previous kernel\n",
0614                 iommu->name);
0615     }
0616 
0617     iommu_set_irq_remapping(iommu, eim_mode);
0618 
0619     return 0;
0620 
0621 out_free_ir_domain:
0622     if (iommu->ir_msi_domain)
0623         irq_domain_remove(iommu->ir_msi_domain);
0624     iommu->ir_msi_domain = NULL;
0625     irq_domain_remove(iommu->ir_domain);
0626     iommu->ir_domain = NULL;
0627 out_free_fwnode:
0628     irq_domain_free_fwnode(fn);
0629 out_free_bitmap:
0630     bitmap_free(bitmap);
0631 out_free_pages:
0632     __free_pages(pages, INTR_REMAP_PAGE_ORDER);
0633 out_free_table:
0634     kfree(ir_table);
0635 
0636     iommu->ir_table  = NULL;
0637 
0638     return -ENOMEM;
0639 }
0640 
0641 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
0642 {
0643     struct fwnode_handle *fn;
0644 
0645     if (iommu && iommu->ir_table) {
0646         if (iommu->ir_msi_domain) {
0647             fn = iommu->ir_msi_domain->fwnode;
0648 
0649             irq_domain_remove(iommu->ir_msi_domain);
0650             irq_domain_free_fwnode(fn);
0651             iommu->ir_msi_domain = NULL;
0652         }
0653         if (iommu->ir_domain) {
0654             fn = iommu->ir_domain->fwnode;
0655 
0656             irq_domain_remove(iommu->ir_domain);
0657             irq_domain_free_fwnode(fn);
0658             iommu->ir_domain = NULL;
0659         }
0660         free_pages((unsigned long)iommu->ir_table->base,
0661                INTR_REMAP_PAGE_ORDER);
0662         bitmap_free(iommu->ir_table->bitmap);
0663         kfree(iommu->ir_table);
0664         iommu->ir_table = NULL;
0665     }
0666 }
0667 
0668 /*
0669  * Disable Interrupt Remapping.
0670  */
0671 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
0672 {
0673     unsigned long flags;
0674     u32 sts;
0675 
0676     if (!ecap_ir_support(iommu->ecap))
0677         return;
0678 
0679     /*
0680      * global invalidation of interrupt entry cache before disabling
0681      * interrupt-remapping.
0682      */
0683     qi_global_iec(iommu);
0684 
0685     raw_spin_lock_irqsave(&iommu->register_lock, flags);
0686 
0687     sts = readl(iommu->reg + DMAR_GSTS_REG);
0688     if (!(sts & DMA_GSTS_IRES))
0689         goto end;
0690 
0691     iommu->gcmd &= ~DMA_GCMD_IRE;
0692     writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
0693 
0694     IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
0695               readl, !(sts & DMA_GSTS_IRES), sts);
0696 
0697 end:
0698     raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
0699 }
0700 
0701 static int __init dmar_x2apic_optout(void)
0702 {
0703     struct acpi_table_dmar *dmar;
0704     dmar = (struct acpi_table_dmar *)dmar_tbl;
0705     if (!dmar || no_x2apic_optout)
0706         return 0;
0707     return dmar->flags & DMAR_X2APIC_OPT_OUT;
0708 }
0709 
0710 static void __init intel_cleanup_irq_remapping(void)
0711 {
0712     struct dmar_drhd_unit *drhd;
0713     struct intel_iommu *iommu;
0714 
0715     for_each_iommu(iommu, drhd) {
0716         if (ecap_ir_support(iommu->ecap)) {
0717             iommu_disable_irq_remapping(iommu);
0718             intel_teardown_irq_remapping(iommu);
0719         }
0720     }
0721 
0722     if (x2apic_supported())
0723         pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
0724 }
0725 
0726 static int __init intel_prepare_irq_remapping(void)
0727 {
0728     struct dmar_drhd_unit *drhd;
0729     struct intel_iommu *iommu;
0730     int eim = 0;
0731 
0732     if (irq_remap_broken) {
0733         pr_warn("This system BIOS has enabled interrupt remapping\n"
0734             "on a chipset that contains an erratum making that\n"
0735             "feature unstable.  To maintain system stability\n"
0736             "interrupt remapping is being disabled.  Please\n"
0737             "contact your BIOS vendor for an update\n");
0738         add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
0739         return -ENODEV;
0740     }
0741 
0742     if (dmar_table_init() < 0)
0743         return -ENODEV;
0744 
0745     if (intel_cap_audit(CAP_AUDIT_STATIC_IRQR, NULL))
0746         return -ENODEV;
0747 
0748     if (!dmar_ir_support())
0749         return -ENODEV;
0750 
0751     if (parse_ioapics_under_ir()) {
0752         pr_info("Not enabling interrupt remapping\n");
0753         goto error;
0754     }
0755 
0756     /* First make sure all IOMMUs support IRQ remapping */
0757     for_each_iommu(iommu, drhd)
0758         if (!ecap_ir_support(iommu->ecap))
0759             goto error;
0760 
0761     /* Detect remapping mode: lapic or x2apic */
0762     if (x2apic_supported()) {
0763         eim = !dmar_x2apic_optout();
0764         if (!eim) {
0765             pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
0766             pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
0767         }
0768     }
0769 
0770     for_each_iommu(iommu, drhd) {
0771         if (eim && !ecap_eim_support(iommu->ecap)) {
0772             pr_info("%s does not support EIM\n", iommu->name);
0773             eim = 0;
0774         }
0775     }
0776 
0777     eim_mode = eim;
0778     if (eim)
0779         pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
0780 
0781     /* Do the initializations early */
0782     for_each_iommu(iommu, drhd) {
0783         if (intel_setup_irq_remapping(iommu)) {
0784             pr_err("Failed to setup irq remapping for %s\n",
0785                    iommu->name);
0786             goto error;
0787         }
0788     }
0789 
0790     return 0;
0791 
0792 error:
0793     intel_cleanup_irq_remapping();
0794     return -ENODEV;
0795 }
0796 
0797 /*
0798  * Set Posted-Interrupts capability.
0799  */
0800 static inline void set_irq_posting_cap(void)
0801 {
0802     struct dmar_drhd_unit *drhd;
0803     struct intel_iommu *iommu;
0804 
0805     if (!disable_irq_post) {
0806         /*
0807          * If IRTE is in posted format, the 'pda' field goes across the
0808          * 64-bit boundary, we need use cmpxchg16b to atomically update
0809          * it. We only expose posted-interrupt when X86_FEATURE_CX16
0810          * is supported. Actually, hardware platforms supporting PI
0811          * should have X86_FEATURE_CX16 support, this has been confirmed
0812          * with Intel hardware guys.
0813          */
0814         if (boot_cpu_has(X86_FEATURE_CX16))
0815             intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
0816 
0817         for_each_iommu(iommu, drhd)
0818             if (!cap_pi_support(iommu->cap)) {
0819                 intel_irq_remap_ops.capability &=
0820                         ~(1 << IRQ_POSTING_CAP);
0821                 break;
0822             }
0823     }
0824 }
0825 
0826 static int __init intel_enable_irq_remapping(void)
0827 {
0828     struct dmar_drhd_unit *drhd;
0829     struct intel_iommu *iommu;
0830     bool setup = false;
0831 
0832     /*
0833      * Setup Interrupt-remapping for all the DRHD's now.
0834      */
0835     for_each_iommu(iommu, drhd) {
0836         if (!ir_pre_enabled(iommu))
0837             iommu_enable_irq_remapping(iommu);
0838         setup = true;
0839     }
0840 
0841     if (!setup)
0842         goto error;
0843 
0844     irq_remapping_enabled = 1;
0845 
0846     set_irq_posting_cap();
0847 
0848     pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
0849 
0850     return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
0851 
0852 error:
0853     intel_cleanup_irq_remapping();
0854     return -1;
0855 }
0856 
0857 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
0858                    struct intel_iommu *iommu,
0859                    struct acpi_dmar_hardware_unit *drhd)
0860 {
0861     struct acpi_dmar_pci_path *path;
0862     u8 bus;
0863     int count, free = -1;
0864 
0865     bus = scope->bus;
0866     path = (struct acpi_dmar_pci_path *)(scope + 1);
0867     count = (scope->length - sizeof(struct acpi_dmar_device_scope))
0868         / sizeof(struct acpi_dmar_pci_path);
0869 
0870     while (--count > 0) {
0871         /*
0872          * Access PCI directly due to the PCI
0873          * subsystem isn't initialized yet.
0874          */
0875         bus = read_pci_config_byte(bus, path->device, path->function,
0876                        PCI_SECONDARY_BUS);
0877         path++;
0878     }
0879 
0880     for (count = 0; count < MAX_HPET_TBS; count++) {
0881         if (ir_hpet[count].iommu == iommu &&
0882             ir_hpet[count].id == scope->enumeration_id)
0883             return 0;
0884         else if (ir_hpet[count].iommu == NULL && free == -1)
0885             free = count;
0886     }
0887     if (free == -1) {
0888         pr_warn("Exceeded Max HPET blocks\n");
0889         return -ENOSPC;
0890     }
0891 
0892     ir_hpet[free].iommu = iommu;
0893     ir_hpet[free].id    = scope->enumeration_id;
0894     ir_hpet[free].bus   = bus;
0895     ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
0896     pr_info("HPET id %d under DRHD base 0x%Lx\n",
0897         scope->enumeration_id, drhd->address);
0898 
0899     return 0;
0900 }
0901 
0902 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
0903                      struct intel_iommu *iommu,
0904                      struct acpi_dmar_hardware_unit *drhd)
0905 {
0906     struct acpi_dmar_pci_path *path;
0907     u8 bus;
0908     int count, free = -1;
0909 
0910     bus = scope->bus;
0911     path = (struct acpi_dmar_pci_path *)(scope + 1);
0912     count = (scope->length - sizeof(struct acpi_dmar_device_scope))
0913         / sizeof(struct acpi_dmar_pci_path);
0914 
0915     while (--count > 0) {
0916         /*
0917          * Access PCI directly due to the PCI
0918          * subsystem isn't initialized yet.
0919          */
0920         bus = read_pci_config_byte(bus, path->device, path->function,
0921                        PCI_SECONDARY_BUS);
0922         path++;
0923     }
0924 
0925     for (count = 0; count < MAX_IO_APICS; count++) {
0926         if (ir_ioapic[count].iommu == iommu &&
0927             ir_ioapic[count].id == scope->enumeration_id)
0928             return 0;
0929         else if (ir_ioapic[count].iommu == NULL && free == -1)
0930             free = count;
0931     }
0932     if (free == -1) {
0933         pr_warn("Exceeded Max IO APICS\n");
0934         return -ENOSPC;
0935     }
0936 
0937     ir_ioapic[free].bus   = bus;
0938     ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
0939     ir_ioapic[free].iommu = iommu;
0940     ir_ioapic[free].id    = scope->enumeration_id;
0941     pr_info("IOAPIC id %d under DRHD base  0x%Lx IOMMU %d\n",
0942         scope->enumeration_id, drhd->address, iommu->seq_id);
0943 
0944     return 0;
0945 }
0946 
0947 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
0948                       struct intel_iommu *iommu)
0949 {
0950     int ret = 0;
0951     struct acpi_dmar_hardware_unit *drhd;
0952     struct acpi_dmar_device_scope *scope;
0953     void *start, *end;
0954 
0955     drhd = (struct acpi_dmar_hardware_unit *)header;
0956     start = (void *)(drhd + 1);
0957     end = ((void *)drhd) + header->length;
0958 
0959     while (start < end && ret == 0) {
0960         scope = start;
0961         if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
0962             ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
0963         else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
0964             ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
0965         start += scope->length;
0966     }
0967 
0968     return ret;
0969 }
0970 
0971 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
0972 {
0973     int i;
0974 
0975     for (i = 0; i < MAX_HPET_TBS; i++)
0976         if (ir_hpet[i].iommu == iommu)
0977             ir_hpet[i].iommu = NULL;
0978 
0979     for (i = 0; i < MAX_IO_APICS; i++)
0980         if (ir_ioapic[i].iommu == iommu)
0981             ir_ioapic[i].iommu = NULL;
0982 }
0983 
0984 /*
0985  * Finds the assocaition between IOAPIC's and its Interrupt-remapping
0986  * hardware unit.
0987  */
0988 static int __init parse_ioapics_under_ir(void)
0989 {
0990     struct dmar_drhd_unit *drhd;
0991     struct intel_iommu *iommu;
0992     bool ir_supported = false;
0993     int ioapic_idx;
0994 
0995     for_each_iommu(iommu, drhd) {
0996         int ret;
0997 
0998         if (!ecap_ir_support(iommu->ecap))
0999             continue;
1000 
1001         ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
1002         if (ret)
1003             return ret;
1004 
1005         ir_supported = true;
1006     }
1007 
1008     if (!ir_supported)
1009         return -ENODEV;
1010 
1011     for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
1012         int ioapic_id = mpc_ioapic_id(ioapic_idx);
1013         if (!map_ioapic_to_iommu(ioapic_id)) {
1014             pr_err(FW_BUG "ioapic %d has no mapping iommu, "
1015                    "interrupt remapping will be disabled\n",
1016                    ioapic_id);
1017             return -1;
1018         }
1019     }
1020 
1021     return 0;
1022 }
1023 
1024 static int __init ir_dev_scope_init(void)
1025 {
1026     int ret;
1027 
1028     if (!irq_remapping_enabled)
1029         return 0;
1030 
1031     down_write(&dmar_global_lock);
1032     ret = dmar_dev_scope_init();
1033     up_write(&dmar_global_lock);
1034 
1035     return ret;
1036 }
1037 rootfs_initcall(ir_dev_scope_init);
1038 
1039 static void disable_irq_remapping(void)
1040 {
1041     struct dmar_drhd_unit *drhd;
1042     struct intel_iommu *iommu = NULL;
1043 
1044     /*
1045      * Disable Interrupt-remapping for all the DRHD's now.
1046      */
1047     for_each_iommu(iommu, drhd) {
1048         if (!ecap_ir_support(iommu->ecap))
1049             continue;
1050 
1051         iommu_disable_irq_remapping(iommu);
1052     }
1053 
1054     /*
1055      * Clear Posted-Interrupts capability.
1056      */
1057     if (!disable_irq_post)
1058         intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
1059 }
1060 
1061 static int reenable_irq_remapping(int eim)
1062 {
1063     struct dmar_drhd_unit *drhd;
1064     bool setup = false;
1065     struct intel_iommu *iommu = NULL;
1066 
1067     for_each_iommu(iommu, drhd)
1068         if (iommu->qi)
1069             dmar_reenable_qi(iommu);
1070 
1071     /*
1072      * Setup Interrupt-remapping for all the DRHD's now.
1073      */
1074     for_each_iommu(iommu, drhd) {
1075         if (!ecap_ir_support(iommu->ecap))
1076             continue;
1077 
1078         /* Set up interrupt remapping for iommu.*/
1079         iommu_set_irq_remapping(iommu, eim);
1080         iommu_enable_irq_remapping(iommu);
1081         setup = true;
1082     }
1083 
1084     if (!setup)
1085         goto error;
1086 
1087     set_irq_posting_cap();
1088 
1089     return 0;
1090 
1091 error:
1092     /*
1093      * handle error condition gracefully here!
1094      */
1095     return -1;
1096 }
1097 
1098 /*
1099  * Store the MSI remapping domain pointer in the device if enabled.
1100  *
1101  * This is called from dmar_pci_bus_add_dev() so it works even when DMA
1102  * remapping is disabled. Only update the pointer if the device is not
1103  * already handled by a non default PCI/MSI interrupt domain. This protects
1104  * e.g. VMD devices.
1105  */
1106 void intel_irq_remap_add_device(struct dmar_pci_notify_info *info)
1107 {
1108     if (!irq_remapping_enabled || pci_dev_has_special_msi_domain(info->dev))
1109         return;
1110 
1111     dev_set_msi_domain(&info->dev->dev, map_dev_to_ir(info->dev));
1112 }
1113 
1114 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1115 {
1116     memset(irte, 0, sizeof(*irte));
1117 
1118     irte->present = 1;
1119     irte->dst_mode = apic->dest_mode_logical;
1120     /*
1121      * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1122      * actual level or edge trigger will be setup in the IO-APIC
1123      * RTE. This will help simplify level triggered irq migration.
1124      * For more details, see the comments (in io_apic.c) explainig IO-APIC
1125      * irq migration in the presence of interrupt-remapping.
1126     */
1127     irte->trigger_mode = 0;
1128     irte->dlvry_mode = apic->delivery_mode;
1129     irte->vector = vector;
1130     irte->dest_id = IRTE_DEST(dest);
1131     irte->redir_hint = 1;
1132 }
1133 
1134 struct irq_remap_ops intel_irq_remap_ops = {
1135     .prepare        = intel_prepare_irq_remapping,
1136     .enable         = intel_enable_irq_remapping,
1137     .disable        = disable_irq_remapping,
1138     .reenable       = reenable_irq_remapping,
1139     .enable_faulting    = enable_drhd_fault_handling,
1140 };
1141 
1142 static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force)
1143 {
1144     struct intel_ir_data *ir_data = irqd->chip_data;
1145     struct irte *irte = &ir_data->irte_entry;
1146     struct irq_cfg *cfg = irqd_cfg(irqd);
1147 
1148     /*
1149      * Atomically updates the IRTE with the new destination, vector
1150      * and flushes the interrupt entry cache.
1151      */
1152     irte->vector = cfg->vector;
1153     irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1154 
1155     /* Update the hardware only if the interrupt is in remapped mode. */
1156     if (force || ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1157         modify_irte(&ir_data->irq_2_iommu, irte);
1158 }
1159 
1160 /*
1161  * Migrate the IO-APIC irq in the presence of intr-remapping.
1162  *
1163  * For both level and edge triggered, irq migration is a simple atomic
1164  * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1165  *
1166  * For level triggered, we eliminate the io-apic RTE modification (with the
1167  * updated vector information), by using a virtual vector (io-apic pin number).
1168  * Real vector that is used for interrupting cpu will be coming from
1169  * the interrupt-remapping table entry.
1170  *
1171  * As the migration is a simple atomic update of IRTE, the same mechanism
1172  * is used to migrate MSI irq's in the presence of interrupt-remapping.
1173  */
1174 static int
1175 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1176               bool force)
1177 {
1178     struct irq_data *parent = data->parent_data;
1179     struct irq_cfg *cfg = irqd_cfg(data);
1180     int ret;
1181 
1182     ret = parent->chip->irq_set_affinity(parent, mask, force);
1183     if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1184         return ret;
1185 
1186     intel_ir_reconfigure_irte(data, false);
1187     /*
1188      * After this point, all the interrupts will start arriving
1189      * at the new destination. So, time to cleanup the previous
1190      * vector allocation.
1191      */
1192     send_cleanup_vector(cfg);
1193 
1194     return IRQ_SET_MASK_OK_DONE;
1195 }
1196 
1197 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1198                      struct msi_msg *msg)
1199 {
1200     struct intel_ir_data *ir_data = irq_data->chip_data;
1201 
1202     *msg = ir_data->msi_entry;
1203 }
1204 
1205 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1206 {
1207     struct intel_ir_data *ir_data = data->chip_data;
1208     struct vcpu_data *vcpu_pi_info = info;
1209 
1210     /* stop posting interrupts, back to remapping mode */
1211     if (!vcpu_pi_info) {
1212         modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1213     } else {
1214         struct irte irte_pi;
1215 
1216         /*
1217          * We are not caching the posted interrupt entry. We
1218          * copy the data from the remapped entry and modify
1219          * the fields which are relevant for posted mode. The
1220          * cached remapped entry is used for switching back to
1221          * remapped mode.
1222          */
1223         memset(&irte_pi, 0, sizeof(irte_pi));
1224         dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1225 
1226         /* Update the posted mode fields */
1227         irte_pi.p_pst = 1;
1228         irte_pi.p_urgent = 0;
1229         irte_pi.p_vector = vcpu_pi_info->vector;
1230         irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1231                 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1232         irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1233                 ~(-1UL << PDA_HIGH_BIT);
1234 
1235         modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1236     }
1237 
1238     return 0;
1239 }
1240 
1241 static struct irq_chip intel_ir_chip = {
1242     .name           = "INTEL-IR",
1243     .irq_ack        = apic_ack_irq,
1244     .irq_set_affinity   = intel_ir_set_affinity,
1245     .irq_compose_msi_msg    = intel_ir_compose_msi_msg,
1246     .irq_set_vcpu_affinity  = intel_ir_set_vcpu_affinity,
1247 };
1248 
1249 static void fill_msi_msg(struct msi_msg *msg, u32 index, u32 subhandle)
1250 {
1251     memset(msg, 0, sizeof(*msg));
1252 
1253     msg->arch_addr_lo.dmar_base_address = X86_MSI_BASE_ADDRESS_LOW;
1254     msg->arch_addr_lo.dmar_subhandle_valid = true;
1255     msg->arch_addr_lo.dmar_format = true;
1256     msg->arch_addr_lo.dmar_index_0_14 = index & 0x7FFF;
1257     msg->arch_addr_lo.dmar_index_15 = !!(index & 0x8000);
1258 
1259     msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
1260 
1261     msg->arch_data.dmar_subhandle = subhandle;
1262 }
1263 
1264 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1265                          struct irq_cfg *irq_cfg,
1266                          struct irq_alloc_info *info,
1267                          int index, int sub_handle)
1268 {
1269     struct irte *irte = &data->irte_entry;
1270 
1271     prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1272 
1273     switch (info->type) {
1274     case X86_IRQ_ALLOC_TYPE_IOAPIC:
1275         /* Set source-id of interrupt request */
1276         set_ioapic_sid(irte, info->devid);
1277         apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1278             info->devid, irte->present, irte->fpd,
1279             irte->dst_mode, irte->redir_hint,
1280             irte->trigger_mode, irte->dlvry_mode,
1281             irte->avail, irte->vector, irte->dest_id,
1282             irte->sid, irte->sq, irte->svt);
1283         sub_handle = info->ioapic.pin;
1284         break;
1285     case X86_IRQ_ALLOC_TYPE_HPET:
1286         set_hpet_sid(irte, info->devid);
1287         break;
1288     case X86_IRQ_ALLOC_TYPE_PCI_MSI:
1289     case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
1290         set_msi_sid(irte,
1291                 pci_real_dma_dev(msi_desc_to_pci_dev(info->desc)));
1292         break;
1293     default:
1294         BUG_ON(1);
1295         break;
1296     }
1297     fill_msi_msg(&data->msi_entry, index, sub_handle);
1298 }
1299 
1300 static void intel_free_irq_resources(struct irq_domain *domain,
1301                      unsigned int virq, unsigned int nr_irqs)
1302 {
1303     struct irq_data *irq_data;
1304     struct intel_ir_data *data;
1305     struct irq_2_iommu *irq_iommu;
1306     unsigned long flags;
1307     int i;
1308     for (i = 0; i < nr_irqs; i++) {
1309         irq_data = irq_domain_get_irq_data(domain, virq  + i);
1310         if (irq_data && irq_data->chip_data) {
1311             data = irq_data->chip_data;
1312             irq_iommu = &data->irq_2_iommu;
1313             raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1314             clear_entries(irq_iommu);
1315             raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1316             irq_domain_reset_irq_data(irq_data);
1317             kfree(data);
1318         }
1319     }
1320 }
1321 
1322 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1323                      unsigned int virq, unsigned int nr_irqs,
1324                      void *arg)
1325 {
1326     struct intel_iommu *iommu = domain->host_data;
1327     struct irq_alloc_info *info = arg;
1328     struct intel_ir_data *data, *ird;
1329     struct irq_data *irq_data;
1330     struct irq_cfg *irq_cfg;
1331     int i, ret, index;
1332 
1333     if (!info || !iommu)
1334         return -EINVAL;
1335     if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI &&
1336         info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX)
1337         return -EINVAL;
1338 
1339     /*
1340      * With IRQ remapping enabled, don't need contiguous CPU vectors
1341      * to support multiple MSI interrupts.
1342      */
1343     if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI)
1344         info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1345 
1346     ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1347     if (ret < 0)
1348         return ret;
1349 
1350     ret = -ENOMEM;
1351     data = kzalloc(sizeof(*data), GFP_KERNEL);
1352     if (!data)
1353         goto out_free_parent;
1354 
1355     down_read(&dmar_global_lock);
1356     index = alloc_irte(iommu, &data->irq_2_iommu, nr_irqs);
1357     up_read(&dmar_global_lock);
1358     if (index < 0) {
1359         pr_warn("Failed to allocate IRTE\n");
1360         kfree(data);
1361         goto out_free_parent;
1362     }
1363 
1364     for (i = 0; i < nr_irqs; i++) {
1365         irq_data = irq_domain_get_irq_data(domain, virq + i);
1366         irq_cfg = irqd_cfg(irq_data);
1367         if (!irq_data || !irq_cfg) {
1368             if (!i)
1369                 kfree(data);
1370             ret = -EINVAL;
1371             goto out_free_data;
1372         }
1373 
1374         if (i > 0) {
1375             ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1376             if (!ird)
1377                 goto out_free_data;
1378             /* Initialize the common data */
1379             ird->irq_2_iommu = data->irq_2_iommu;
1380             ird->irq_2_iommu.sub_handle = i;
1381         } else {
1382             ird = data;
1383         }
1384 
1385         irq_data->hwirq = (index << 16) + i;
1386         irq_data->chip_data = ird;
1387         irq_data->chip = &intel_ir_chip;
1388         intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1389         irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1390     }
1391     return 0;
1392 
1393 out_free_data:
1394     intel_free_irq_resources(domain, virq, i);
1395 out_free_parent:
1396     irq_domain_free_irqs_common(domain, virq, nr_irqs);
1397     return ret;
1398 }
1399 
1400 static void intel_irq_remapping_free(struct irq_domain *domain,
1401                      unsigned int virq, unsigned int nr_irqs)
1402 {
1403     intel_free_irq_resources(domain, virq, nr_irqs);
1404     irq_domain_free_irqs_common(domain, virq, nr_irqs);
1405 }
1406 
1407 static int intel_irq_remapping_activate(struct irq_domain *domain,
1408                     struct irq_data *irq_data, bool reserve)
1409 {
1410     intel_ir_reconfigure_irte(irq_data, true);
1411     return 0;
1412 }
1413 
1414 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1415                        struct irq_data *irq_data)
1416 {
1417     struct intel_ir_data *data = irq_data->chip_data;
1418     struct irte entry;
1419 
1420     memset(&entry, 0, sizeof(entry));
1421     modify_irte(&data->irq_2_iommu, &entry);
1422 }
1423 
1424 static int intel_irq_remapping_select(struct irq_domain *d,
1425                       struct irq_fwspec *fwspec,
1426                       enum irq_domain_bus_token bus_token)
1427 {
1428     struct intel_iommu *iommu = NULL;
1429 
1430     if (x86_fwspec_is_ioapic(fwspec))
1431         iommu = map_ioapic_to_iommu(fwspec->param[0]);
1432     else if (x86_fwspec_is_hpet(fwspec))
1433         iommu = map_hpet_to_iommu(fwspec->param[0]);
1434 
1435     return iommu && d == iommu->ir_domain;
1436 }
1437 
1438 static const struct irq_domain_ops intel_ir_domain_ops = {
1439     .select = intel_irq_remapping_select,
1440     .alloc = intel_irq_remapping_alloc,
1441     .free = intel_irq_remapping_free,
1442     .activate = intel_irq_remapping_activate,
1443     .deactivate = intel_irq_remapping_deactivate,
1444 };
1445 
1446 /*
1447  * Support of Interrupt Remapping Unit Hotplug
1448  */
1449 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1450 {
1451     int ret;
1452     int eim = x2apic_enabled();
1453 
1454     ret = intel_cap_audit(CAP_AUDIT_HOTPLUG_IRQR, iommu);
1455     if (ret)
1456         return ret;
1457 
1458     if (eim && !ecap_eim_support(iommu->ecap)) {
1459         pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1460             iommu->reg_phys, iommu->ecap);
1461         return -ENODEV;
1462     }
1463 
1464     if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1465         pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1466             iommu->reg_phys);
1467         return -ENODEV;
1468     }
1469 
1470     /* TODO: check all IOAPICs are covered by IOMMU */
1471 
1472     /* Setup Interrupt-remapping now. */
1473     ret = intel_setup_irq_remapping(iommu);
1474     if (ret) {
1475         pr_err("Failed to setup irq remapping for %s\n",
1476                iommu->name);
1477         intel_teardown_irq_remapping(iommu);
1478         ir_remove_ioapic_hpet_scope(iommu);
1479     } else {
1480         iommu_enable_irq_remapping(iommu);
1481     }
1482 
1483     return ret;
1484 }
1485 
1486 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1487 {
1488     int ret = 0;
1489     struct intel_iommu *iommu = dmaru->iommu;
1490 
1491     if (!irq_remapping_enabled)
1492         return 0;
1493     if (iommu == NULL)
1494         return -EINVAL;
1495     if (!ecap_ir_support(iommu->ecap))
1496         return 0;
1497     if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1498         !cap_pi_support(iommu->cap))
1499         return -EBUSY;
1500 
1501     if (insert) {
1502         if (!iommu->ir_table)
1503             ret = dmar_ir_add(dmaru, iommu);
1504     } else {
1505         if (iommu->ir_table) {
1506             if (!bitmap_empty(iommu->ir_table->bitmap,
1507                       INTR_REMAP_TABLE_ENTRIES)) {
1508                 ret = -EBUSY;
1509             } else {
1510                 iommu_disable_irq_remapping(iommu);
1511                 intel_teardown_irq_remapping(iommu);
1512                 ir_remove_ioapic_hpet_scope(iommu);
1513             }
1514         }
1515     }
1516 
1517     return ret;
1518 }
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