iommu/intel/cap_audit.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * cap_audit.c - audit iommu capabilities for boot time and hot plug
0004  *
0005  * Copyright (C) 2021 Intel Corporation
0006  *
0007  * Author: Kyung Min Park <kyung.min.park@intel.com>
0008  *         Lu Baolu <baolu.lu@linux.intel.com>
0009  */
0010
0011 #define pr_fmt(fmt) "DMAR: " fmt
0012
0013 #include "iommu.h"
0014 #include "cap_audit.h"
0015
0016 static u64 intel_iommu_cap_sanity;
0017 static u64 intel_iommu_ecap_sanity;
0018
0019 static inline void check_irq_capabilities(struct intel_iommu *a,
0020                       struct intel_iommu *b)
0021 {
0022     CHECK_FEATURE_MISMATCH(a, b, cap, pi_support, CAP_PI_MASK);
0023     CHECK_FEATURE_MISMATCH(a, b, ecap, eim_support, ECAP_EIM_MASK);
0024 }
0025
0026 static inline void check_dmar_capabilities(struct intel_iommu *a,
0027                        struct intel_iommu *b)
0028 {
0029     MINIMAL_FEATURE_IOMMU(b, cap, CAP_MAMV_MASK);
0030     MINIMAL_FEATURE_IOMMU(b, cap, CAP_NFR_MASK);
0031     MINIMAL_FEATURE_IOMMU(b, cap, CAP_SLLPS_MASK);
0032     MINIMAL_FEATURE_IOMMU(b, cap, CAP_FRO_MASK);
0033     MINIMAL_FEATURE_IOMMU(b, cap, CAP_MGAW_MASK);
0034     MINIMAL_FEATURE_IOMMU(b, cap, CAP_SAGAW_MASK);
0035     MINIMAL_FEATURE_IOMMU(b, cap, CAP_NDOMS_MASK);
0036     MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_PSS_MASK);
0037     MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_MHMV_MASK);
0038     MINIMAL_FEATURE_IOMMU(b, ecap, ECAP_IRO_MASK);
0039
0040     CHECK_FEATURE_MISMATCH(a, b, cap, 5lp_support, CAP_FL5LP_MASK);
0041     CHECK_FEATURE_MISMATCH(a, b, cap, fl1gp_support, CAP_FL1GP_MASK);
0042     CHECK_FEATURE_MISMATCH(a, b, cap, read_drain, CAP_RD_MASK);
0043     CHECK_FEATURE_MISMATCH(a, b, cap, write_drain, CAP_WD_MASK);
0044     CHECK_FEATURE_MISMATCH(a, b, cap, pgsel_inv, CAP_PSI_MASK);
0045     CHECK_FEATURE_MISMATCH(a, b, cap, zlr, CAP_ZLR_MASK);
0046     CHECK_FEATURE_MISMATCH(a, b, cap, caching_mode, CAP_CM_MASK);
0047     CHECK_FEATURE_MISMATCH(a, b, cap, phmr, CAP_PHMR_MASK);
0048     CHECK_FEATURE_MISMATCH(a, b, cap, plmr, CAP_PLMR_MASK);
0049     CHECK_FEATURE_MISMATCH(a, b, cap, rwbf, CAP_RWBF_MASK);
0050     CHECK_FEATURE_MISMATCH(a, b, cap, afl, CAP_AFL_MASK);
0051     CHECK_FEATURE_MISMATCH(a, b, ecap, rps, ECAP_RPS_MASK);
0052     CHECK_FEATURE_MISMATCH(a, b, ecap, smpwc, ECAP_SMPWC_MASK);
0053     CHECK_FEATURE_MISMATCH(a, b, ecap, flts, ECAP_FLTS_MASK);
0054     CHECK_FEATURE_MISMATCH(a, b, ecap, slts, ECAP_SLTS_MASK);
0055     CHECK_FEATURE_MISMATCH(a, b, ecap, nwfs, ECAP_NWFS_MASK);
0056     CHECK_FEATURE_MISMATCH(a, b, ecap, slads, ECAP_SLADS_MASK);
0057     CHECK_FEATURE_MISMATCH(a, b, ecap, vcs, ECAP_VCS_MASK);
0058     CHECK_FEATURE_MISMATCH(a, b, ecap, smts, ECAP_SMTS_MASK);
0059     CHECK_FEATURE_MISMATCH(a, b, ecap, pds, ECAP_PDS_MASK);
0060     CHECK_FEATURE_MISMATCH(a, b, ecap, dit, ECAP_DIT_MASK);
0061     CHECK_FEATURE_MISMATCH(a, b, ecap, pasid, ECAP_PASID_MASK);
0062     CHECK_FEATURE_MISMATCH(a, b, ecap, eafs, ECAP_EAFS_MASK);
0063     CHECK_FEATURE_MISMATCH(a, b, ecap, srs, ECAP_SRS_MASK);
0064     CHECK_FEATURE_MISMATCH(a, b, ecap, ers, ECAP_ERS_MASK);
0065     CHECK_FEATURE_MISMATCH(a, b, ecap, prs, ECAP_PRS_MASK);
0066     CHECK_FEATURE_MISMATCH(a, b, ecap, nest, ECAP_NEST_MASK);
0067     CHECK_FEATURE_MISMATCH(a, b, ecap, mts, ECAP_MTS_MASK);
0068     CHECK_FEATURE_MISMATCH(a, b, ecap, sc_support, ECAP_SC_MASK);
0069     CHECK_FEATURE_MISMATCH(a, b, ecap, pass_through, ECAP_PT_MASK);
0070     CHECK_FEATURE_MISMATCH(a, b, ecap, dev_iotlb_support, ECAP_DT_MASK);
0071     CHECK_FEATURE_MISMATCH(a, b, ecap, qis, ECAP_QI_MASK);
0072     CHECK_FEATURE_MISMATCH(a, b, ecap, coherent, ECAP_C_MASK);
0073 }
0074
0075 static int cap_audit_hotplug(struct intel_iommu *iommu, enum cap_audit_type type)
0076 {
0077     bool mismatch = false;
0078     u64 old_cap = intel_iommu_cap_sanity;
0079     u64 old_ecap = intel_iommu_ecap_sanity;
0080
0081     if (type == CAP_AUDIT_HOTPLUG_IRQR) {
0082         CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, pi_support, CAP_PI_MASK);
0083         CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, eim_support, ECAP_EIM_MASK);
0084         goto out;
0085     }
0086
0087     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, 5lp_support, CAP_FL5LP_MASK);
0088     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, fl1gp_support, CAP_FL1GP_MASK);
0089     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, read_drain, CAP_RD_MASK);
0090     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, write_drain, CAP_WD_MASK);
0091     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, pgsel_inv, CAP_PSI_MASK);
0092     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, zlr, CAP_ZLR_MASK);
0093     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, caching_mode, CAP_CM_MASK);
0094     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, phmr, CAP_PHMR_MASK);
0095     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, plmr, CAP_PLMR_MASK);
0096     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, rwbf, CAP_RWBF_MASK);
0097     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, afl, CAP_AFL_MASK);
0098     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, rps, ECAP_RPS_MASK);
0099     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, smpwc, ECAP_SMPWC_MASK);
0100     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, flts, ECAP_FLTS_MASK);
0101     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, slts, ECAP_SLTS_MASK);
0102     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, nwfs, ECAP_NWFS_MASK);
0103     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, slads, ECAP_SLADS_MASK);
0104     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, vcs, ECAP_VCS_MASK);
0105     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, smts, ECAP_SMTS_MASK);
0106     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, pds, ECAP_PDS_MASK);
0107     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, dit, ECAP_DIT_MASK);
0108     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, pasid, ECAP_PASID_MASK);
0109     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, eafs, ECAP_EAFS_MASK);
0110     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, srs, ECAP_SRS_MASK);
0111     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, ers, ECAP_ERS_MASK);
0112     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, prs, ECAP_PRS_MASK);
0113     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, nest, ECAP_NEST_MASK);
0114     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, mts, ECAP_MTS_MASK);
0115     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, sc_support, ECAP_SC_MASK);
0116     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, pass_through, ECAP_PT_MASK);
0117     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, dev_iotlb_support, ECAP_DT_MASK);
0118     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, qis, ECAP_QI_MASK);
0119     CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, coherent, ECAP_C_MASK);
0120
0121     /* Abort hot plug if the hot plug iommu feature is smaller than global */
0122     MINIMAL_FEATURE_HOTPLUG(iommu, cap, max_amask_val, CAP_MAMV_MASK, mismatch);
0123     MINIMAL_FEATURE_HOTPLUG(iommu, cap, num_fault_regs, CAP_NFR_MASK, mismatch);
0124     MINIMAL_FEATURE_HOTPLUG(iommu, cap, super_page_val, CAP_SLLPS_MASK, mismatch);
0125     MINIMAL_FEATURE_HOTPLUG(iommu, cap, fault_reg_offset, CAP_FRO_MASK, mismatch);
0126     MINIMAL_FEATURE_HOTPLUG(iommu, cap, mgaw, CAP_MGAW_MASK, mismatch);
0127     MINIMAL_FEATURE_HOTPLUG(iommu, cap, sagaw, CAP_SAGAW_MASK, mismatch);
0128     MINIMAL_FEATURE_HOTPLUG(iommu, cap, ndoms, CAP_NDOMS_MASK, mismatch);
0129     MINIMAL_FEATURE_HOTPLUG(iommu, ecap, pss, ECAP_PSS_MASK, mismatch);
0130     MINIMAL_FEATURE_HOTPLUG(iommu, ecap, max_handle_mask, ECAP_MHMV_MASK, mismatch);
0131     MINIMAL_FEATURE_HOTPLUG(iommu, ecap, iotlb_offset, ECAP_IRO_MASK, mismatch);
0132
0133 out:
0134     if (mismatch) {
0135         intel_iommu_cap_sanity = old_cap;
0136         intel_iommu_ecap_sanity = old_ecap;
0137         return -EFAULT;
0138     }
0139
0140     return 0;
0141 }
0142
0143 static int cap_audit_static(struct intel_iommu *iommu, enum cap_audit_type type)
0144 {
0145     struct dmar_drhd_unit *d;
0146     struct intel_iommu *i;
0147     int rc = 0;
0148
0149     rcu_read_lock();
0150     if (list_empty(&dmar_drhd_units))
0151         goto out;
0152
0153     for_each_active_iommu(i, d) {
0154         if (!iommu) {
0155             intel_iommu_ecap_sanity = i->ecap;
0156             intel_iommu_cap_sanity = i->cap;
0157             iommu = i;
0158             continue;
0159         }
0160
0161         if (type == CAP_AUDIT_STATIC_DMAR)
0162             check_dmar_capabilities(iommu, i);
0163         else
0164             check_irq_capabilities(iommu, i);
0165     }
0166
0167     /*
0168      * If the system is sane to support scalable mode, either SL or FL
0169      * should be sane.
0170      */
0171     if (intel_cap_smts_sanity() &&
0172         !intel_cap_flts_sanity() && !intel_cap_slts_sanity())
0173         rc = -EOPNOTSUPP;
0174
0175 out:
0176     rcu_read_unlock();
0177     return rc;
0178 }
0179
0180 int intel_cap_audit(enum cap_audit_type type, struct intel_iommu *iommu)
0181 {
0182     switch (type) {
0183     case CAP_AUDIT_STATIC_DMAR:
0184     case CAP_AUDIT_STATIC_IRQR:
0185         return cap_audit_static(iommu, type);
0186     case CAP_AUDIT_HOTPLUG_DMAR:
0187     case CAP_AUDIT_HOTPLUG_IRQR:
0188         return cap_audit_hotplug(iommu, type);
0189     default:
0190         break;
0191     }
0192
0193     return -EFAULT;
0194 }
0195
0196 bool intel_cap_smts_sanity(void)
0197 {
0198     return ecap_smts(intel_iommu_ecap_sanity);
0199 }
0200
0201 bool intel_cap_pasid_sanity(void)
0202 {
0203     return ecap_pasid(intel_iommu_ecap_sanity);
0204 }
0205
0206 bool intel_cap_nest_sanity(void)
0207 {
0208     return ecap_nest(intel_iommu_ecap_sanity);
0209 }
0210
0211 bool intel_cap_flts_sanity(void)
0212 {
0213     return ecap_flts(intel_iommu_ecap_sanity);
0214 }
0215
0216 bool intel_cap_slts_sanity(void)
0217 {
0218     return ecap_slts(intel_iommu_ecap_sanity);
0219 }