iommu/amd/amd_iommu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
0004  * Author: Joerg Roedel <jroedel@suse.de>
0005  */
0006
0007 #ifndef AMD_IOMMU_H
0008 #define AMD_IOMMU_H
0009
0010 #include <linux/iommu.h>
0011
0012 #include "amd_iommu_types.h"
0013
0014 extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
0015 extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
0016 extern void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid);
0017 extern void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
0018 extern int amd_iommu_init_devices(void);
0019 extern void amd_iommu_uninit_devices(void);
0020 extern void amd_iommu_init_notifier(void);
0021 extern int amd_iommu_init_api(void);
0022 extern void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
0023
0024 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
0025 void amd_iommu_debugfs_setup(struct amd_iommu *iommu);
0026 #else
0027 static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
0028 #endif
0029
0030 /* Needed for interrupt remapping */
0031 extern int amd_iommu_prepare(void);
0032 extern int amd_iommu_enable(void);
0033 extern void amd_iommu_disable(void);
0034 extern int amd_iommu_reenable(int);
0035 extern int amd_iommu_enable_faulting(void);
0036 extern int amd_iommu_guest_ir;
0037 extern enum io_pgtable_fmt amd_iommu_pgtable;
0038
0039 /* IOMMUv2 specific functions */
0040 struct iommu_domain;
0041
0042 extern bool amd_iommu_v2_supported(void);
0043 extern struct amd_iommu *get_amd_iommu(unsigned int idx);
0044 extern u8 amd_iommu_pc_get_max_banks(unsigned int idx);
0045 extern bool amd_iommu_pc_supported(void);
0046 extern u8 amd_iommu_pc_get_max_counters(unsigned int idx);
0047 extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
0048                 u8 fxn, u64 *value);
0049 extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
0050                 u8 fxn, u64 *value);
0051
0052 extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
0053 extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
0054 extern void amd_iommu_domain_direct_map(struct iommu_domain *dom);
0055 extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
0056 extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
0057                 u64 address);
0058 extern void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
0059 extern void amd_iommu_domain_update(struct protection_domain *domain);
0060 extern void amd_iommu_domain_flush_complete(struct protection_domain *domain);
0061 extern void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain);
0062 extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
0063 extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
0064                      unsigned long cr3);
0065 extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
0066
0067 #ifdef CONFIG_IRQ_REMAP
0068 extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
0069 #else
0070 static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
0071 {
0072     return 0;
0073 }
0074 #endif
0075
0076 #define PPR_SUCCESS         0x0
0077 #define PPR_INVALID         0x1
0078 #define PPR_FAILURE         0xf
0079
0080 extern int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
0081                   int status, int tag);
0082
0083 static inline bool is_rd890_iommu(struct pci_dev *pdev)
0084 {
0085     return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
0086            (pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
0087 }
0088
0089 static inline bool iommu_feature(struct amd_iommu *iommu, u64 mask)
0090 {
0091     return !!(iommu->features & mask);
0092 }
0093
0094 static inline u64 iommu_virt_to_phys(void *vaddr)
0095 {
0096     return (u64)__sme_set(virt_to_phys(vaddr));
0097 }
0098
0099 static inline void *iommu_phys_to_virt(unsigned long paddr)
0100 {
0101     return phys_to_virt(__sme_clr(paddr));
0102 }
0103
0104 static inline
0105 void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)
0106 {
0107     atomic64_set(&domain->iop.pt_root, root);
0108     domain->iop.root = (u64 *)(root & PAGE_MASK);
0109     domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */
0110 }
0111
0112 static inline
0113 void amd_iommu_domain_clr_pt_root(struct protection_domain *domain)
0114 {
0115     amd_iommu_domain_set_pt_root(domain, 0);
0116 }
0117
0118 static inline int get_pci_sbdf_id(struct pci_dev *pdev)
0119 {
0120     int seg = pci_domain_nr(pdev->bus);
0121     u16 devid = pci_dev_id(pdev);
0122
0123     return PCI_SEG_DEVID_TO_SBDF(seg, devid);
0124 }
0125
0126 extern bool translation_pre_enabled(struct amd_iommu *iommu);
0127 extern bool amd_iommu_is_attach_deferred(struct device *dev);
0128 extern int __init add_special_device(u8 type, u8 id, u32 *devid,
0129                      bool cmd_line);
0130
0131 #ifdef CONFIG_DMI
0132 void amd_iommu_apply_ivrs_quirks(void);
0133 #else
0134 static inline void amd_iommu_apply_ivrs_quirks(void) { }
0135 #endif
0136
0137 extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
0138                      u64 *root, int mode);
0139 extern struct dev_table_entry *get_dev_table(struct amd_iommu *iommu);
0140
0141 extern u64 amd_iommu_efr;
0142 extern u64 amd_iommu_efr2;
0143
0144 extern bool amd_iommu_snp_en;
0145 #endif