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0008 #include <linux/interconnect-provider.h>
0009 #include <linux/module.h>
0010 #include <linux/of_device.h>
0011 #include <dt-bindings/interconnect/qcom,sm8350.h>
0012
0013 #include "bcm-voter.h"
0014 #include "icc-rpmh.h"
0015 #include "sm8350.h"
0016
0017 DEFINE_QNODE(qhm_qspi, SM8350_MASTER_QSPI_0, 1, 4, SM8350_SLAVE_A1NOC_SNOC);
0018 DEFINE_QNODE(qhm_qup0, SM8350_MASTER_QUP_0, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
0019 DEFINE_QNODE(qhm_qup1, SM8350_MASTER_QUP_1, 1, 4, SM8350_SLAVE_A1NOC_SNOC);
0020 DEFINE_QNODE(qhm_qup2, SM8350_MASTER_QUP_2, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
0021 DEFINE_QNODE(qnm_a1noc_cfg, SM8350_MASTER_A1NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A1NOC);
0022 DEFINE_QNODE(xm_sdc4, SM8350_MASTER_SDCC_4, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
0023 DEFINE_QNODE(xm_ufs_mem, SM8350_MASTER_UFS_MEM, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
0024 DEFINE_QNODE(xm_usb3_0, SM8350_MASTER_USB3_0, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
0025 DEFINE_QNODE(xm_usb3_1, SM8350_MASTER_USB3_1, 1, 8, SM8350_SLAVE_A1NOC_SNOC);
0026 DEFINE_QNODE(qhm_qdss_bam, SM8350_MASTER_QDSS_BAM, 1, 4, SM8350_SLAVE_A2NOC_SNOC);
0027 DEFINE_QNODE(qnm_a2noc_cfg, SM8350_MASTER_A2NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A2NOC);
0028 DEFINE_QNODE(qxm_crypto, SM8350_MASTER_CRYPTO, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
0029 DEFINE_QNODE(qxm_ipa, SM8350_MASTER_IPA, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
0030 DEFINE_QNODE(xm_pcie3_0, SM8350_MASTER_PCIE_0, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC);
0031 DEFINE_QNODE(xm_pcie3_1, SM8350_MASTER_PCIE_1, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC);
0032 DEFINE_QNODE(xm_qdss_etr, SM8350_MASTER_QDSS_ETR, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
0033 DEFINE_QNODE(xm_sdc2, SM8350_MASTER_SDCC_2, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
0034 DEFINE_QNODE(xm_ufs_card, SM8350_MASTER_UFS_CARD, 1, 8, SM8350_SLAVE_A2NOC_SNOC);
0035 DEFINE_QNODE(qnm_gemnoc_cnoc, SM8350_MASTER_GEM_NOC_CNOC, 1, 16, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU);
0036 DEFINE_QNODE(qnm_gemnoc_pcie, SM8350_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8350_SLAVE_PCIE_0, SM8350_SLAVE_PCIE_1);
0037 DEFINE_QNODE(xm_qdss_dap, SM8350_MASTER_QDSS_DAP, 1, 8, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU);
0038 DEFINE_QNODE(qnm_cnoc_dc_noc, SM8350_MASTER_CNOC_DC_NOC, 1, 4, SM8350_SLAVE_LLCC_CFG, SM8350_SLAVE_GEM_NOC_CFG);
0039 DEFINE_QNODE(alm_gpu_tcu, SM8350_MASTER_GPU_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
0040 DEFINE_QNODE(alm_sys_tcu, SM8350_MASTER_SYS_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
0041 DEFINE_QNODE(chm_apps, SM8350_MASTER_APPSS_PROC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC);
0042 DEFINE_QNODE(qnm_cmpnoc, SM8350_MASTER_COMPUTE_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
0043 DEFINE_QNODE(qnm_gemnoc_cfg, SM8350_MASTER_GEM_NOC_CFG, 1, 4, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, SM8350_SLAVE_MCDMA_MS_MPU_CFG, SM8350_SLAVE_SERVICE_GEM_NOC_1, SM8350_SLAVE_SERVICE_GEM_NOC_2, SM8350_SLAVE_SERVICE_GEM_NOC);
0044 DEFINE_QNODE(qnm_gpu, SM8350_MASTER_GFX3D, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
0045 DEFINE_QNODE(qnm_mnoc_hf, SM8350_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8350_SLAVE_LLCC);
0046 DEFINE_QNODE(qnm_mnoc_sf, SM8350_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
0047 DEFINE_QNODE(qnm_pcie, SM8350_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC);
0048 DEFINE_QNODE(qnm_snoc_gc, SM8350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8350_SLAVE_LLCC);
0049 DEFINE_QNODE(qnm_snoc_sf, SM8350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC);
0050 DEFINE_QNODE(qhm_config_noc, SM8350_MASTER_CNOC_LPASS_AG_NOC, 1, 4, SM8350_SLAVE_LPASS_CORE_CFG, SM8350_SLAVE_LPASS_LPI_CFG, SM8350_SLAVE_LPASS_MPU_CFG, SM8350_SLAVE_LPASS_TOP_CFG, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, SM8350_SLAVE_SERVICE_LPASS_AG_NOC);
0051 DEFINE_QNODE(llcc_mc, SM8350_MASTER_LLCC, 4, 4, SM8350_SLAVE_EBI1);
0052 DEFINE_QNODE(qnm_camnoc_hf, SM8350_MASTER_CAMNOC_HF, 2, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
0053 DEFINE_QNODE(qnm_camnoc_icp, SM8350_MASTER_CAMNOC_ICP, 1, 8, SM8350_SLAVE_MNOC_SF_MEM_NOC);
0054 DEFINE_QNODE(qnm_camnoc_sf, SM8350_MASTER_CAMNOC_SF, 2, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
0055 DEFINE_QNODE(qnm_mnoc_cfg, SM8350_MASTER_CNOC_MNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_MNOC);
0056 DEFINE_QNODE(qnm_video0, SM8350_MASTER_VIDEO_P0, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
0057 DEFINE_QNODE(qnm_video1, SM8350_MASTER_VIDEO_P1, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
0058 DEFINE_QNODE(qnm_video_cvp, SM8350_MASTER_VIDEO_PROC, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
0059 DEFINE_QNODE(qxm_mdp0, SM8350_MASTER_MDP0, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
0060 DEFINE_QNODE(qxm_mdp1, SM8350_MASTER_MDP1, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC);
0061 DEFINE_QNODE(qxm_rot, SM8350_MASTER_ROTATOR, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC);
0062 DEFINE_QNODE(qhm_nsp_noc_config, SM8350_MASTER_CDSP_NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_NSP_NOC);
0063 DEFINE_QNODE(qxm_nsp, SM8350_MASTER_CDSP_PROC, 2, 32, SM8350_SLAVE_CDSP_MEM_NOC);
0064 DEFINE_QNODE(qnm_aggre1_noc, SM8350_MASTER_A1NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF);
0065 DEFINE_QNODE(qnm_aggre2_noc, SM8350_MASTER_A2NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF);
0066 DEFINE_QNODE(qnm_snoc_cfg, SM8350_MASTER_SNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_SNOC);
0067 DEFINE_QNODE(qxm_pimem, SM8350_MASTER_PIMEM, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC);
0068 DEFINE_QNODE(xm_gic, SM8350_MASTER_GIC, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC);
0069 DEFINE_QNODE(qnm_mnoc_hf_disp, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP);
0070 DEFINE_QNODE(qnm_mnoc_sf_disp, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP);
0071 DEFINE_QNODE(llcc_mc_disp, SM8350_MASTER_LLCC_DISP, 4, 4, SM8350_SLAVE_EBI1_DISP);
0072 DEFINE_QNODE(qxm_mdp0_disp, SM8350_MASTER_MDP0_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP);
0073 DEFINE_QNODE(qxm_mdp1_disp, SM8350_MASTER_MDP1_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP);
0074 DEFINE_QNODE(qxm_rot_disp, SM8350_MASTER_ROTATOR_DISP, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP);
0075 DEFINE_QNODE(qns_a1noc_snoc, SM8350_SLAVE_A1NOC_SNOC, 1, 16, SM8350_MASTER_A1NOC_SNOC);
0076 DEFINE_QNODE(srvc_aggre1_noc, SM8350_SLAVE_SERVICE_A1NOC, 1, 4);
0077 DEFINE_QNODE(qns_a2noc_snoc, SM8350_SLAVE_A2NOC_SNOC, 1, 16, SM8350_MASTER_A2NOC_SNOC);
0078 DEFINE_QNODE(qns_pcie_mem_noc, SM8350_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_MASTER_ANOC_PCIE_GEM_NOC);
0079 DEFINE_QNODE(srvc_aggre2_noc, SM8350_SLAVE_SERVICE_A2NOC, 1, 4);
0080 DEFINE_QNODE(qhs_ahb2phy0, SM8350_SLAVE_AHB2PHY_SOUTH, 1, 4);
0081 DEFINE_QNODE(qhs_ahb2phy1, SM8350_SLAVE_AHB2PHY_NORTH, 1, 4);
0082 DEFINE_QNODE(qhs_aoss, SM8350_SLAVE_AOSS, 1, 4);
0083 DEFINE_QNODE(qhs_apss, SM8350_SLAVE_APPSS, 1, 8);
0084 DEFINE_QNODE(qhs_camera_cfg, SM8350_SLAVE_CAMERA_CFG, 1, 4);
0085 DEFINE_QNODE(qhs_clk_ctl, SM8350_SLAVE_CLK_CTL, 1, 4);
0086 DEFINE_QNODE(qhs_compute_cfg, SM8350_SLAVE_CDSP_CFG, 1, 4);
0087 DEFINE_QNODE(qhs_cpr_cx, SM8350_SLAVE_RBCPR_CX_CFG, 1, 4);
0088 DEFINE_QNODE(qhs_cpr_mmcx, SM8350_SLAVE_RBCPR_MMCX_CFG, 1, 4);
0089 DEFINE_QNODE(qhs_cpr_mx, SM8350_SLAVE_RBCPR_MX_CFG, 1, 4);
0090 DEFINE_QNODE(qhs_crypto0_cfg, SM8350_SLAVE_CRYPTO_0_CFG, 1, 4);
0091 DEFINE_QNODE(qhs_cx_rdpm, SM8350_SLAVE_CX_RDPM, 1, 4);
0092 DEFINE_QNODE(qhs_dcc_cfg, SM8350_SLAVE_DCC_CFG, 1, 4);
0093 DEFINE_QNODE(qhs_display_cfg, SM8350_SLAVE_DISPLAY_CFG, 1, 4);
0094 DEFINE_QNODE(qhs_gpuss_cfg, SM8350_SLAVE_GFX3D_CFG, 1, 8);
0095 DEFINE_QNODE(qhs_hwkm, SM8350_SLAVE_HWKM, 1, 4);
0096 DEFINE_QNODE(qhs_imem_cfg, SM8350_SLAVE_IMEM_CFG, 1, 4);
0097 DEFINE_QNODE(qhs_ipa, SM8350_SLAVE_IPA_CFG, 1, 4);
0098 DEFINE_QNODE(qhs_ipc_router, SM8350_SLAVE_IPC_ROUTER_CFG, 1, 4);
0099 DEFINE_QNODE(qhs_lpass_cfg, SM8350_SLAVE_LPASS, 1, 4, SM8350_MASTER_CNOC_LPASS_AG_NOC);
0100 DEFINE_QNODE(qhs_mss_cfg, SM8350_SLAVE_CNOC_MSS, 1, 4);
0101 DEFINE_QNODE(qhs_mx_rdpm, SM8350_SLAVE_MX_RDPM, 1, 4);
0102 DEFINE_QNODE(qhs_pcie0_cfg, SM8350_SLAVE_PCIE_0_CFG, 1, 4);
0103 DEFINE_QNODE(qhs_pcie1_cfg, SM8350_SLAVE_PCIE_1_CFG, 1, 4);
0104 DEFINE_QNODE(qhs_pdm, SM8350_SLAVE_PDM, 1, 4);
0105 DEFINE_QNODE(qhs_pimem_cfg, SM8350_SLAVE_PIMEM_CFG, 1, 4);
0106 DEFINE_QNODE(qhs_pka_wrapper_cfg, SM8350_SLAVE_PKA_WRAPPER_CFG, 1, 4);
0107 DEFINE_QNODE(qhs_pmu_wrapper_cfg, SM8350_SLAVE_PMU_WRAPPER_CFG, 1, 4);
0108 DEFINE_QNODE(qhs_qdss_cfg, SM8350_SLAVE_QDSS_CFG, 1, 4);
0109 DEFINE_QNODE(qhs_qspi, SM8350_SLAVE_QSPI_0, 1, 4);
0110 DEFINE_QNODE(qhs_qup0, SM8350_SLAVE_QUP_0, 1, 4);
0111 DEFINE_QNODE(qhs_qup1, SM8350_SLAVE_QUP_1, 1, 4);
0112 DEFINE_QNODE(qhs_qup2, SM8350_SLAVE_QUP_2, 1, 4);
0113 DEFINE_QNODE(qhs_sdc2, SM8350_SLAVE_SDCC_2, 1, 4);
0114 DEFINE_QNODE(qhs_sdc4, SM8350_SLAVE_SDCC_4, 1, 4);
0115 DEFINE_QNODE(qhs_security, SM8350_SLAVE_SECURITY, 1, 4);
0116 DEFINE_QNODE(qhs_spss_cfg, SM8350_SLAVE_SPSS_CFG, 1, 4);
0117 DEFINE_QNODE(qhs_tcsr, SM8350_SLAVE_TCSR, 1, 4);
0118 DEFINE_QNODE(qhs_tlmm, SM8350_SLAVE_TLMM, 1, 4);
0119 DEFINE_QNODE(qhs_ufs_card_cfg, SM8350_SLAVE_UFS_CARD_CFG, 1, 4);
0120 DEFINE_QNODE(qhs_ufs_mem_cfg, SM8350_SLAVE_UFS_MEM_CFG, 1, 4);
0121 DEFINE_QNODE(qhs_usb3_0, SM8350_SLAVE_USB3_0, 1, 4);
0122 DEFINE_QNODE(qhs_usb3_1, SM8350_SLAVE_USB3_1, 1, 4);
0123 DEFINE_QNODE(qhs_venus_cfg, SM8350_SLAVE_VENUS_CFG, 1, 4);
0124 DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8350_SLAVE_VSENSE_CTRL_CFG, 1, 4);
0125 DEFINE_QNODE(qns_a1_noc_cfg, SM8350_SLAVE_A1NOC_CFG, 1, 4);
0126 DEFINE_QNODE(qns_a2_noc_cfg, SM8350_SLAVE_A2NOC_CFG, 1, 4);
0127 DEFINE_QNODE(qns_ddrss_cfg, SM8350_SLAVE_DDRSS_CFG, 1, 4);
0128 DEFINE_QNODE(qns_mnoc_cfg, SM8350_SLAVE_CNOC_MNOC_CFG, 1, 4);
0129 DEFINE_QNODE(qns_snoc_cfg, SM8350_SLAVE_SNOC_CFG, 1, 4);
0130 DEFINE_QNODE(qxs_boot_imem, SM8350_SLAVE_BOOT_IMEM, 1, 8);
0131 DEFINE_QNODE(qxs_imem, SM8350_SLAVE_IMEM, 1, 8);
0132 DEFINE_QNODE(qxs_pimem, SM8350_SLAVE_PIMEM, 1, 8);
0133 DEFINE_QNODE(srvc_cnoc, SM8350_SLAVE_SERVICE_CNOC, 1, 4);
0134 DEFINE_QNODE(xs_pcie_0, SM8350_SLAVE_PCIE_0, 1, 8);
0135 DEFINE_QNODE(xs_pcie_1, SM8350_SLAVE_PCIE_1, 1, 8);
0136 DEFINE_QNODE(xs_qdss_stm, SM8350_SLAVE_QDSS_STM, 1, 4);
0137 DEFINE_QNODE(xs_sys_tcu_cfg, SM8350_SLAVE_TCU, 1, 8);
0138 DEFINE_QNODE(qhs_llcc, SM8350_SLAVE_LLCC_CFG, 1, 4);
0139 DEFINE_QNODE(qns_gemnoc, SM8350_SLAVE_GEM_NOC_CFG, 1, 4);
0140 DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
0141 DEFINE_QNODE(qhs_modem_ms_mpu_cfg, SM8350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4);
0142 DEFINE_QNODE(qns_gem_noc_cnoc, SM8350_SLAVE_GEM_NOC_CNOC, 1, 16, SM8350_MASTER_GEM_NOC_CNOC);
0143 DEFINE_QNODE(qns_llcc, SM8350_SLAVE_LLCC, 4, 16, SM8350_MASTER_LLCC);
0144 DEFINE_QNODE(qns_pcie, SM8350_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8);
0145 DEFINE_QNODE(srvc_even_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
0146 DEFINE_QNODE(srvc_odd_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
0147 DEFINE_QNODE(srvc_sys_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC, 1, 4);
0148 DEFINE_QNODE(qhs_lpass_core, SM8350_SLAVE_LPASS_CORE_CFG, 1, 4);
0149 DEFINE_QNODE(qhs_lpass_lpi, SM8350_SLAVE_LPASS_LPI_CFG, 1, 4);
0150 DEFINE_QNODE(qhs_lpass_mpu, SM8350_SLAVE_LPASS_MPU_CFG, 1, 4);
0151 DEFINE_QNODE(qhs_lpass_top, SM8350_SLAVE_LPASS_TOP_CFG, 1, 4);
0152 DEFINE_QNODE(srvc_niu_aml_noc, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, 1, 4);
0153 DEFINE_QNODE(srvc_niu_lpass_agnoc, SM8350_SLAVE_SERVICE_LPASS_AG_NOC, 1, 4);
0154 DEFINE_QNODE(ebi, SM8350_SLAVE_EBI1, 4, 4);
0155 DEFINE_QNODE(qns_mem_noc_hf, SM8350_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC);
0156 DEFINE_QNODE(qns_mem_noc_sf, SM8350_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC);
0157 DEFINE_QNODE(srvc_mnoc, SM8350_SLAVE_SERVICE_MNOC, 1, 4);
0158 DEFINE_QNODE(qns_nsp_gemnoc, SM8350_SLAVE_CDSP_MEM_NOC, 2, 32, SM8350_MASTER_COMPUTE_NOC);
0159 DEFINE_QNODE(service_nsp_noc, SM8350_SLAVE_SERVICE_NSP_NOC, 1, 4);
0160 DEFINE_QNODE(qns_gemnoc_gc, SM8350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8350_MASTER_SNOC_GC_MEM_NOC);
0161 DEFINE_QNODE(qns_gemnoc_sf, SM8350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8350_MASTER_SNOC_SF_MEM_NOC);
0162 DEFINE_QNODE(srvc_snoc, SM8350_SLAVE_SERVICE_SNOC, 1, 4);
0163 DEFINE_QNODE(qns_llcc_disp, SM8350_SLAVE_LLCC_DISP, 4, 16, SM8350_MASTER_LLCC_DISP);
0164 DEFINE_QNODE(ebi_disp, SM8350_SLAVE_EBI1_DISP, 4, 4);
0165 DEFINE_QNODE(qns_mem_noc_hf_disp, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP);
0166 DEFINE_QNODE(qns_mem_noc_sf_disp, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP);
0167
0168 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
0169 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
0170 DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie);
0171 DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_apss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_cfg, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_hwkm, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_mss_cfg, &qhs_mx_rdpm, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_security, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, &qns_a2_noc_cfg, &qns_ddrss_cfg, &qns_mnoc_cfg, &qns_snoc_cfg, &srvc_cnoc);
0172 DEFINE_QBCM(bcm_cn2, "CN2", false, &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4);
0173 DEFINE_QBCM(bcm_co0, "CO0", false, &qns_nsp_gemnoc);
0174 DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_nsp);
0175 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
0176 DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
0177 DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
0178 DEFINE_QBCM(bcm_mm4, "MM4", false, &qns_mem_noc_sf);
0179 DEFINE_QBCM(bcm_mm5, "MM5", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp, &qxm_rot);
0180 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
0181 DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
0182 DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
0183 DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
0184 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
0185 DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
0186 DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
0187 DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
0188 DEFINE_QBCM(bcm_sn5, "SN5", false, &xm_pcie3_0);
0189 DEFINE_QBCM(bcm_sn6, "SN6", false, &xm_pcie3_1);
0190 DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
0191 DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
0192 DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
0193 DEFINE_QBCM(bcm_acv_disp, "ACV", false, &ebi_disp);
0194 DEFINE_QBCM(bcm_mc0_disp, "MC0", false, &ebi_disp);
0195 DEFINE_QBCM(bcm_mm0_disp, "MM0", false, &qns_mem_noc_hf_disp);
0196 DEFINE_QBCM(bcm_mm1_disp, "MM1", false, &qxm_mdp0_disp, &qxm_mdp1_disp);
0197 DEFINE_QBCM(bcm_mm4_disp, "MM4", false, &qns_mem_noc_sf_disp);
0198 DEFINE_QBCM(bcm_mm5_disp, "MM5", false, &qxm_rot_disp);
0199 DEFINE_QBCM(bcm_sh0_disp, "SH0", false, &qns_llcc_disp);
0200
0201 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
0202 };
0203
0204 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
0205 [MASTER_QSPI_0] = &qhm_qspi,
0206 [MASTER_QUP_1] = &qhm_qup1,
0207 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
0208 [MASTER_SDCC_4] = &xm_sdc4,
0209 [MASTER_UFS_MEM] = &xm_ufs_mem,
0210 [MASTER_USB3_0] = &xm_usb3_0,
0211 [MASTER_USB3_1] = &xm_usb3_1,
0212 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
0213 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
0214 };
0215
0216 static const struct qcom_icc_desc sm8350_aggre1_noc = {
0217 .nodes = aggre1_noc_nodes,
0218 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
0219 .bcms = aggre1_noc_bcms,
0220 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
0221 };
0222
0223 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
0224 &bcm_ce0,
0225 &bcm_sn5,
0226 &bcm_sn6,
0227 &bcm_sn14,
0228 };
0229
0230 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
0231 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
0232 [MASTER_QUP_0] = &qhm_qup0,
0233 [MASTER_QUP_2] = &qhm_qup2,
0234 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
0235 [MASTER_CRYPTO] = &qxm_crypto,
0236 [MASTER_IPA] = &qxm_ipa,
0237 [MASTER_PCIE_0] = &xm_pcie3_0,
0238 [MASTER_PCIE_1] = &xm_pcie3_1,
0239 [MASTER_QDSS_ETR] = &xm_qdss_etr,
0240 [MASTER_SDCC_2] = &xm_sdc2,
0241 [MASTER_UFS_CARD] = &xm_ufs_card,
0242 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
0243 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
0244 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
0245 };
0246
0247 static const struct qcom_icc_desc sm8350_aggre2_noc = {
0248 .nodes = aggre2_noc_nodes,
0249 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
0250 .bcms = aggre2_noc_bcms,
0251 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
0252 };
0253
0254 static struct qcom_icc_bcm * const config_noc_bcms[] = {
0255 &bcm_cn0,
0256 &bcm_cn1,
0257 &bcm_cn2,
0258 &bcm_sn3,
0259 &bcm_sn4,
0260 };
0261
0262 static struct qcom_icc_node * const config_noc_nodes[] = {
0263 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
0264 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
0265 [MASTER_QDSS_DAP] = &xm_qdss_dap,
0266 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
0267 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
0268 [SLAVE_AOSS] = &qhs_aoss,
0269 [SLAVE_APPSS] = &qhs_apss,
0270 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
0271 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
0272 [SLAVE_CDSP_CFG] = &qhs_compute_cfg,
0273 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
0274 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
0275 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
0276 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
0277 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
0278 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
0279 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
0280 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
0281 [SLAVE_HWKM] = &qhs_hwkm,
0282 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
0283 [SLAVE_IPA_CFG] = &qhs_ipa,
0284 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
0285 [SLAVE_LPASS] = &qhs_lpass_cfg,
0286 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
0287 [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
0288 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
0289 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
0290 [SLAVE_PDM] = &qhs_pdm,
0291 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
0292 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg,
0293 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
0294 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
0295 [SLAVE_QSPI_0] = &qhs_qspi,
0296 [SLAVE_QUP_0] = &qhs_qup0,
0297 [SLAVE_QUP_1] = &qhs_qup1,
0298 [SLAVE_QUP_2] = &qhs_qup2,
0299 [SLAVE_SDCC_2] = &qhs_sdc2,
0300 [SLAVE_SDCC_4] = &qhs_sdc4,
0301 [SLAVE_SECURITY] = &qhs_security,
0302 [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
0303 [SLAVE_TCSR] = &qhs_tcsr,
0304 [SLAVE_TLMM] = &qhs_tlmm,
0305 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
0306 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
0307 [SLAVE_USB3_0] = &qhs_usb3_0,
0308 [SLAVE_USB3_1] = &qhs_usb3_1,
0309 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
0310 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
0311 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
0312 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
0313 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
0314 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
0315 [SLAVE_SNOC_CFG] = &qns_snoc_cfg,
0316 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
0317 [SLAVE_IMEM] = &qxs_imem,
0318 [SLAVE_PIMEM] = &qxs_pimem,
0319 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
0320 [SLAVE_PCIE_0] = &xs_pcie_0,
0321 [SLAVE_PCIE_1] = &xs_pcie_1,
0322 [SLAVE_QDSS_STM] = &xs_qdss_stm,
0323 [SLAVE_TCU] = &xs_sys_tcu_cfg,
0324 };
0325
0326 static const struct qcom_icc_desc sm8350_config_noc = {
0327 .nodes = config_noc_nodes,
0328 .num_nodes = ARRAY_SIZE(config_noc_nodes),
0329 .bcms = config_noc_bcms,
0330 .num_bcms = ARRAY_SIZE(config_noc_bcms),
0331 };
0332
0333 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
0334 };
0335
0336 static struct qcom_icc_node * const dc_noc_nodes[] = {
0337 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
0338 [SLAVE_LLCC_CFG] = &qhs_llcc,
0339 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
0340 };
0341
0342 static const struct qcom_icc_desc sm8350_dc_noc = {
0343 .nodes = dc_noc_nodes,
0344 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
0345 .bcms = dc_noc_bcms,
0346 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
0347 };
0348
0349 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
0350 &bcm_sh0,
0351 &bcm_sh2,
0352 &bcm_sh3,
0353 &bcm_sh4,
0354 &bcm_sh0_disp,
0355 };
0356
0357 static struct qcom_icc_node * const gem_noc_nodes[] = {
0358 [MASTER_GPU_TCU] = &alm_gpu_tcu,
0359 [MASTER_SYS_TCU] = &alm_sys_tcu,
0360 [MASTER_APPSS_PROC] = &chm_apps,
0361 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
0362 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
0363 [MASTER_GFX3D] = &qnm_gpu,
0364 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
0365 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
0366 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
0367 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
0368 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
0369 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
0370 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg,
0371 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
0372 [SLAVE_LLCC] = &qns_llcc,
0373 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
0374 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
0375 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
0376 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
0377 [MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
0378 [MASTER_MNOC_SF_MEM_NOC_DISP] = &qnm_mnoc_sf_disp,
0379 [SLAVE_LLCC_DISP] = &qns_llcc_disp,
0380 };
0381
0382 static const struct qcom_icc_desc sm8350_gem_noc = {
0383 .nodes = gem_noc_nodes,
0384 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
0385 .bcms = gem_noc_bcms,
0386 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
0387 };
0388
0389 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
0390 };
0391
0392 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
0393 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
0394 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
0395 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
0396 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
0397 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
0398 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
0399 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
0400 };
0401
0402 static const struct qcom_icc_desc sm8350_lpass_ag_noc = {
0403 .nodes = lpass_ag_noc_nodes,
0404 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
0405 .bcms = lpass_ag_noc_bcms,
0406 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
0407 };
0408
0409 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
0410 &bcm_acv,
0411 &bcm_mc0,
0412 &bcm_acv_disp,
0413 &bcm_mc0_disp,
0414 };
0415
0416 static struct qcom_icc_node * const mc_virt_nodes[] = {
0417 [MASTER_LLCC] = &llcc_mc,
0418 [SLAVE_EBI1] = &ebi,
0419 [MASTER_LLCC_DISP] = &llcc_mc_disp,
0420 [SLAVE_EBI1_DISP] = &ebi_disp,
0421 };
0422
0423 static const struct qcom_icc_desc sm8350_mc_virt = {
0424 .nodes = mc_virt_nodes,
0425 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
0426 .bcms = mc_virt_bcms,
0427 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
0428 };
0429
0430 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
0431 &bcm_mm0,
0432 &bcm_mm1,
0433 &bcm_mm4,
0434 &bcm_mm5,
0435 &bcm_mm0_disp,
0436 &bcm_mm1_disp,
0437 &bcm_mm4_disp,
0438 &bcm_mm5_disp,
0439 };
0440
0441 static struct qcom_icc_node * const mmss_noc_nodes[] = {
0442 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
0443 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
0444 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
0445 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
0446 [MASTER_VIDEO_P0] = &qnm_video0,
0447 [MASTER_VIDEO_P1] = &qnm_video1,
0448 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
0449 [MASTER_MDP0] = &qxm_mdp0,
0450 [MASTER_MDP1] = &qxm_mdp1,
0451 [MASTER_ROTATOR] = &qxm_rot,
0452 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
0453 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
0454 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
0455 [MASTER_MDP0_DISP] = &qxm_mdp0_disp,
0456 [MASTER_MDP1_DISP] = &qxm_mdp1_disp,
0457 [MASTER_ROTATOR_DISP] = &qxm_rot_disp,
0458 [SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
0459 [SLAVE_MNOC_SF_MEM_NOC_DISP] = &qns_mem_noc_sf_disp,
0460 };
0461
0462 static const struct qcom_icc_desc sm8350_mmss_noc = {
0463 .nodes = mmss_noc_nodes,
0464 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
0465 .bcms = mmss_noc_bcms,
0466 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
0467 };
0468
0469 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
0470 &bcm_co0,
0471 &bcm_co3,
0472 };
0473
0474 static struct qcom_icc_node * const nsp_noc_nodes[] = {
0475 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
0476 [MASTER_CDSP_PROC] = &qxm_nsp,
0477 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
0478 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
0479 };
0480
0481 static const struct qcom_icc_desc sm8350_compute_noc = {
0482 .nodes = nsp_noc_nodes,
0483 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
0484 .bcms = nsp_noc_bcms,
0485 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
0486 };
0487
0488 static struct qcom_icc_bcm * const system_noc_bcms[] = {
0489 &bcm_sn0,
0490 &bcm_sn2,
0491 &bcm_sn7,
0492 &bcm_sn8,
0493 };
0494
0495 static struct qcom_icc_node * const system_noc_nodes[] = {
0496 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
0497 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
0498 [MASTER_SNOC_CFG] = &qnm_snoc_cfg,
0499 [MASTER_PIMEM] = &qxm_pimem,
0500 [MASTER_GIC] = &xm_gic,
0501 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
0502 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
0503 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
0504 };
0505
0506 static const struct qcom_icc_desc sm8350_system_noc = {
0507 .nodes = system_noc_nodes,
0508 .num_nodes = ARRAY_SIZE(system_noc_nodes),
0509 .bcms = system_noc_bcms,
0510 .num_bcms = ARRAY_SIZE(system_noc_bcms),
0511 };
0512
0513 static const struct of_device_id qnoc_of_match[] = {
0514 { .compatible = "qcom,sm8350-aggre1-noc", .data = &sm8350_aggre1_noc},
0515 { .compatible = "qcom,sm8350-aggre2-noc", .data = &sm8350_aggre2_noc},
0516 { .compatible = "qcom,sm8350-config-noc", .data = &sm8350_config_noc},
0517 { .compatible = "qcom,sm8350-dc-noc", .data = &sm8350_dc_noc},
0518 { .compatible = "qcom,sm8350-gem-noc", .data = &sm8350_gem_noc},
0519 { .compatible = "qcom,sm8350-lpass-ag-noc", .data = &sm8350_lpass_ag_noc},
0520 { .compatible = "qcom,sm8350-mc-virt", .data = &sm8350_mc_virt},
0521 { .compatible = "qcom,sm8350-mmss-noc", .data = &sm8350_mmss_noc},
0522 { .compatible = "qcom,sm8350-compute-noc", .data = &sm8350_compute_noc},
0523 { .compatible = "qcom,sm8350-system-noc", .data = &sm8350_system_noc},
0524 { }
0525 };
0526 MODULE_DEVICE_TABLE(of, qnoc_of_match);
0527
0528 static struct platform_driver qnoc_driver = {
0529 .probe = qcom_icc_rpmh_probe,
0530 .remove = qcom_icc_rpmh_remove,
0531 .driver = {
0532 .name = "qnoc-sm8350",
0533 .of_match_table = qnoc_of_match,
0534 },
0535 };
0536 module_platform_driver(qnoc_driver);
0537
0538 MODULE_DESCRIPTION("SM8350 NoC driver");
0539 MODULE_LICENSE("GPL v2");
