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0007 #include <linux/device.h>
0008 #include <linux/interconnect.h>
0009 #include <linux/interconnect-provider.h>
0010 #include <linux/module.h>
0011 #include <linux/of_platform.h>
0012 #include <dt-bindings/interconnect/qcom,sm8250.h>
0013
0014 #include "bcm-voter.h"
0015 #include "icc-rpmh.h"
0016 #include "sm8250.h"
0017
0018 DEFINE_QNODE(qhm_a1noc_cfg, SM8250_MASTER_A1NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A1NOC);
0019 DEFINE_QNODE(qhm_qspi, SM8250_MASTER_QSPI_0, 1, 4, SM8250_A1NOC_SNOC_SLV);
0020 DEFINE_QNODE(qhm_qup1, SM8250_MASTER_QUP_1, 1, 4, SM8250_A1NOC_SNOC_SLV);
0021 DEFINE_QNODE(qhm_qup2, SM8250_MASTER_QUP_2, 1, 4, SM8250_A1NOC_SNOC_SLV);
0022 DEFINE_QNODE(qhm_tsif, SM8250_MASTER_TSIF, 1, 4, SM8250_A1NOC_SNOC_SLV);
0023 DEFINE_QNODE(xm_pcie3_modem, SM8250_MASTER_PCIE_2, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1);
0024 DEFINE_QNODE(xm_sdc4, SM8250_MASTER_SDCC_4, 1, 8, SM8250_A1NOC_SNOC_SLV);
0025 DEFINE_QNODE(xm_ufs_mem, SM8250_MASTER_UFS_MEM, 1, 8, SM8250_A1NOC_SNOC_SLV);
0026 DEFINE_QNODE(xm_usb3_0, SM8250_MASTER_USB3, 1, 8, SM8250_A1NOC_SNOC_SLV);
0027 DEFINE_QNODE(xm_usb3_1, SM8250_MASTER_USB3_1, 1, 8, SM8250_A1NOC_SNOC_SLV);
0028 DEFINE_QNODE(qhm_a2noc_cfg, SM8250_MASTER_A2NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A2NOC);
0029 DEFINE_QNODE(qhm_qdss_bam, SM8250_MASTER_QDSS_BAM, 1, 4, SM8250_A2NOC_SNOC_SLV);
0030 DEFINE_QNODE(qhm_qup0, SM8250_MASTER_QUP_0, 1, 4, SM8250_A2NOC_SNOC_SLV);
0031 DEFINE_QNODE(qnm_cnoc, SM8250_MASTER_CNOC_A2NOC, 1, 8, SM8250_A2NOC_SNOC_SLV);
0032 DEFINE_QNODE(qxm_crypto, SM8250_MASTER_CRYPTO_CORE_0, 1, 8, SM8250_A2NOC_SNOC_SLV);
0033 DEFINE_QNODE(qxm_ipa, SM8250_MASTER_IPA, 1, 8, SM8250_A2NOC_SNOC_SLV);
0034 DEFINE_QNODE(xm_pcie3_0, SM8250_MASTER_PCIE, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
0035 DEFINE_QNODE(xm_pcie3_1, SM8250_MASTER_PCIE_1, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC);
0036 DEFINE_QNODE(xm_qdss_etr, SM8250_MASTER_QDSS_ETR, 1, 8, SM8250_A2NOC_SNOC_SLV);
0037 DEFINE_QNODE(xm_sdc2, SM8250_MASTER_SDCC_2, 1, 8, SM8250_A2NOC_SNOC_SLV);
0038 DEFINE_QNODE(xm_ufs_card, SM8250_MASTER_UFS_CARD, 1, 8, SM8250_A2NOC_SNOC_SLV);
0039 DEFINE_QNODE(qnm_npu, SM8250_MASTER_NPU, 2, 32, SM8250_SLAVE_CDSP_MEM_NOC);
0040 DEFINE_QNODE(qnm_snoc, SM8250_SNOC_CNOC_MAS, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
0041 DEFINE_QNODE(xm_qdss_dap, SM8250_MASTER_QDSS_DAP, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_CNOC_A2NOC, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL);
0042 DEFINE_QNODE(qhm_cnoc_dc_noc, SM8250_MASTER_CNOC_DC_NOC, 1, 4, SM8250_SLAVE_GEM_NOC_CFG, SM8250_SLAVE_LLCC_CFG);
0043 DEFINE_QNODE(alm_gpu_tcu, SM8250_MASTER_GPU_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
0044 DEFINE_QNODE(alm_sys_tcu, SM8250_MASTER_SYS_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
0045 DEFINE_QNODE(chm_apps, SM8250_MASTER_AMPSS_M0, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
0046 DEFINE_QNODE(qhm_gemnoc_cfg, SM8250_MASTER_GEM_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_GEM_NOC_2, SM8250_SLAVE_SERVICE_GEM_NOC_1, SM8250_SLAVE_SERVICE_GEM_NOC);
0047 DEFINE_QNODE(qnm_cmpnoc, SM8250_MASTER_COMPUTE_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
0048 DEFINE_QNODE(qnm_gpu, SM8250_MASTER_GRAPHICS_3D, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
0049 DEFINE_QNODE(qnm_mnoc_hf, SM8250_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC);
0050 DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
0051 DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC);
0052 DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAVE_LLCC);
0053 DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC);
0054 DEFINE_QNODE(ipa_core_master, SM8250_MASTER_IPA_CORE, 1, 8, SM8250_SLAVE_IPA_CORE);
0055 DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0);
0056 DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_MNOC);
0057 DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
0058 DEFINE_QNODE(qnm_camnoc_icp, SM8250_MASTER_CAMNOC_ICP, 1, 8, SM8250_SLAVE_MNOC_SF_MEM_NOC);
0059 DEFINE_QNODE(qnm_camnoc_sf, SM8250_MASTER_CAMNOC_SF, 2, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
0060 DEFINE_QNODE(qnm_video0, SM8250_MASTER_VIDEO_P0, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
0061 DEFINE_QNODE(qnm_video1, SM8250_MASTER_VIDEO_P1, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
0062 DEFINE_QNODE(qnm_video_cvp, SM8250_MASTER_VIDEO_PROC, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
0063 DEFINE_QNODE(qxm_mdp0, SM8250_MASTER_MDP_PORT0, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
0064 DEFINE_QNODE(qxm_mdp1, SM8250_MASTER_MDP_PORT1, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC);
0065 DEFINE_QNODE(qxm_rot, SM8250_MASTER_ROTATOR, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC);
0066 DEFINE_QNODE(amm_npu_sys, SM8250_MASTER_NPU_SYS, 4, 32, SM8250_SLAVE_NPU_COMPUTE_NOC);
0067 DEFINE_QNODE(amm_npu_sys_cdp_w, SM8250_MASTER_NPU_CDP, 2, 16, SM8250_SLAVE_NPU_COMPUTE_NOC);
0068 DEFINE_QNODE(qhm_cfg, SM8250_MASTER_NPU_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_NPU_NOC, SM8250_SLAVE_ISENSE_CFG, SM8250_SLAVE_NPU_LLM_CFG, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, SM8250_SLAVE_NPU_CP, SM8250_SLAVE_NPU_TCM, SM8250_SLAVE_NPU_CAL_DP0, SM8250_SLAVE_NPU_CAL_DP1, SM8250_SLAVE_NPU_DPM);
0069 DEFINE_QNODE(qhm_snoc_cfg, SM8250_MASTER_SNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_SNOC);
0070 DEFINE_QNODE(qnm_aggre1_noc, SM8250_A1NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
0071 DEFINE_QNODE(qnm_aggre2_noc, SM8250_A2NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF);
0072 DEFINE_QNODE(qnm_gemnoc, SM8250_MASTER_GEM_NOC_SNOC, 1, 16, SM8250_SLAVE_PIMEM, SM8250_SLAVE_OCIMEM, SM8250_SLAVE_APPSS, SM8250_SNOC_CNOC_SLV, SM8250_SLAVE_TCU, SM8250_SLAVE_QDSS_STM);
0073 DEFINE_QNODE(qnm_gemnoc_pcie, SM8250_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8250_SLAVE_PCIE_2, SM8250_SLAVE_PCIE_0, SM8250_SLAVE_PCIE_1);
0074 DEFINE_QNODE(qxm_pimem, SM8250_MASTER_PIMEM, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
0075 DEFINE_QNODE(xm_gic, SM8250_MASTER_GIC, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC);
0076 DEFINE_QNODE(qns_a1noc_snoc, SM8250_A1NOC_SNOC_SLV, 1, 16, SM8250_A1NOC_SNOC_MAS);
0077 DEFINE_QNODE(qns_pcie_modem_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
0078 DEFINE_QNODE(srvc_aggre1_noc, SM8250_SLAVE_SERVICE_A1NOC, 1, 4);
0079 DEFINE_QNODE(qns_a2noc_snoc, SM8250_A2NOC_SNOC_SLV, 1, 16, SM8250_A2NOC_SNOC_MAS);
0080 DEFINE_QNODE(qns_pcie_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC);
0081 DEFINE_QNODE(srvc_aggre2_noc, SM8250_SLAVE_SERVICE_A2NOC, 1, 4);
0082 DEFINE_QNODE(qns_cdsp_mem_noc, SM8250_SLAVE_CDSP_MEM_NOC, 2, 32, SM8250_MASTER_COMPUTE_NOC);
0083 DEFINE_QNODE(qhs_a1_noc_cfg, SM8250_SLAVE_A1NOC_CFG, 1, 4, SM8250_MASTER_A1NOC_CFG);
0084 DEFINE_QNODE(qhs_a2_noc_cfg, SM8250_SLAVE_A2NOC_CFG, 1, 4, SM8250_MASTER_A2NOC_CFG);
0085 DEFINE_QNODE(qhs_ahb2phy0, SM8250_SLAVE_AHB2PHY_SOUTH, 1, 4);
0086 DEFINE_QNODE(qhs_ahb2phy1, SM8250_SLAVE_AHB2PHY_NORTH, 1, 4);
0087 DEFINE_QNODE(qhs_aoss, SM8250_SLAVE_AOSS, 1, 4);
0088 DEFINE_QNODE(qhs_camera_cfg, SM8250_SLAVE_CAMERA_CFG, 1, 4);
0089 DEFINE_QNODE(qhs_clk_ctl, SM8250_SLAVE_CLK_CTL, 1, 4);
0090 DEFINE_QNODE(qhs_compute_dsp, SM8250_SLAVE_CDSP_CFG, 1, 4);
0091 DEFINE_QNODE(qhs_cpr_cx, SM8250_SLAVE_RBCPR_CX_CFG, 1, 4);
0092 DEFINE_QNODE(qhs_cpr_mmcx, SM8250_SLAVE_RBCPR_MMCX_CFG, 1, 4);
0093 DEFINE_QNODE(qhs_cpr_mx, SM8250_SLAVE_RBCPR_MX_CFG, 1, 4);
0094 DEFINE_QNODE(qhs_crypto0_cfg, SM8250_SLAVE_CRYPTO_0_CFG, 1, 4);
0095 DEFINE_QNODE(qhs_cx_rdpm, SM8250_SLAVE_CX_RDPM, 1, 4);
0096 DEFINE_QNODE(qhs_dcc_cfg, SM8250_SLAVE_DCC_CFG, 1, 4);
0097 DEFINE_QNODE(qhs_ddrss_cfg, SM8250_SLAVE_CNOC_DDRSS, 1, 4, SM8250_MASTER_CNOC_DC_NOC);
0098 DEFINE_QNODE(qhs_display_cfg, SM8250_SLAVE_DISPLAY_CFG, 1, 4);
0099 DEFINE_QNODE(qhs_gpuss_cfg, SM8250_SLAVE_GRAPHICS_3D_CFG, 1, 8);
0100 DEFINE_QNODE(qhs_imem_cfg, SM8250_SLAVE_IMEM_CFG, 1, 4);
0101 DEFINE_QNODE(qhs_ipa, SM8250_SLAVE_IPA_CFG, 1, 4);
0102 DEFINE_QNODE(qhs_ipc_router, SM8250_SLAVE_IPC_ROUTER_CFG, 1, 4);
0103 DEFINE_QNODE(qhs_lpass_cfg, SM8250_SLAVE_LPASS, 1, 4);
0104 DEFINE_QNODE(qhs_mnoc_cfg, SM8250_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8250_MASTER_CNOC_MNOC_CFG);
0105 DEFINE_QNODE(qhs_npu_cfg, SM8250_SLAVE_NPU_CFG, 1, 4, SM8250_MASTER_NPU_NOC_CFG);
0106 DEFINE_QNODE(qhs_pcie0_cfg, SM8250_SLAVE_PCIE_0_CFG, 1, 4);
0107 DEFINE_QNODE(qhs_pcie1_cfg, SM8250_SLAVE_PCIE_1_CFG, 1, 4);
0108 DEFINE_QNODE(qhs_pcie_modem_cfg, SM8250_SLAVE_PCIE_2_CFG, 1, 4);
0109 DEFINE_QNODE(qhs_pdm, SM8250_SLAVE_PDM, 1, 4);
0110 DEFINE_QNODE(qhs_pimem_cfg, SM8250_SLAVE_PIMEM_CFG, 1, 4);
0111 DEFINE_QNODE(qhs_prng, SM8250_SLAVE_PRNG, 1, 4);
0112 DEFINE_QNODE(qhs_qdss_cfg, SM8250_SLAVE_QDSS_CFG, 1, 4);
0113 DEFINE_QNODE(qhs_qspi, SM8250_SLAVE_QSPI_0, 1, 4);
0114 DEFINE_QNODE(qhs_qup0, SM8250_SLAVE_QUP_0, 1, 4);
0115 DEFINE_QNODE(qhs_qup1, SM8250_SLAVE_QUP_1, 1, 4);
0116 DEFINE_QNODE(qhs_qup2, SM8250_SLAVE_QUP_2, 1, 4);
0117 DEFINE_QNODE(qhs_sdc2, SM8250_SLAVE_SDCC_2, 1, 4);
0118 DEFINE_QNODE(qhs_sdc4, SM8250_SLAVE_SDCC_4, 1, 4);
0119 DEFINE_QNODE(qhs_snoc_cfg, SM8250_SLAVE_SNOC_CFG, 1, 4, SM8250_MASTER_SNOC_CFG);
0120 DEFINE_QNODE(qhs_tcsr, SM8250_SLAVE_TCSR, 1, 4);
0121 DEFINE_QNODE(qhs_tlmm0, SM8250_SLAVE_TLMM_NORTH, 1, 4);
0122 DEFINE_QNODE(qhs_tlmm1, SM8250_SLAVE_TLMM_SOUTH, 1, 4);
0123 DEFINE_QNODE(qhs_tlmm2, SM8250_SLAVE_TLMM_WEST, 1, 4);
0124 DEFINE_QNODE(qhs_tsif, SM8250_SLAVE_TSIF, 1, 4);
0125 DEFINE_QNODE(qhs_ufs_card_cfg, SM8250_SLAVE_UFS_CARD_CFG, 1, 4);
0126 DEFINE_QNODE(qhs_ufs_mem_cfg, SM8250_SLAVE_UFS_MEM_CFG, 1, 4);
0127 DEFINE_QNODE(qhs_usb3_0, SM8250_SLAVE_USB3, 1, 4);
0128 DEFINE_QNODE(qhs_usb3_1, SM8250_SLAVE_USB3_1, 1, 4);
0129 DEFINE_QNODE(qhs_venus_cfg, SM8250_SLAVE_VENUS_CFG, 1, 4);
0130 DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8250_SLAVE_VSENSE_CTRL_CFG, 1, 4);
0131 DEFINE_QNODE(qns_cnoc_a2noc, SM8250_SLAVE_CNOC_A2NOC, 1, 8, SM8250_MASTER_CNOC_A2NOC);
0132 DEFINE_QNODE(srvc_cnoc, SM8250_SLAVE_SERVICE_CNOC, 1, 4);
0133 DEFINE_QNODE(qhs_llcc, SM8250_SLAVE_LLCC_CFG, 1, 4);
0134 DEFINE_QNODE(qhs_memnoc, SM8250_SLAVE_GEM_NOC_CFG, 1, 4, SM8250_MASTER_GEM_NOC_CFG);
0135 DEFINE_QNODE(qns_gem_noc_snoc, SM8250_SLAVE_GEM_NOC_SNOC, 1, 16, SM8250_MASTER_GEM_NOC_SNOC);
0136 DEFINE_QNODE(qns_llcc, SM8250_SLAVE_LLCC, 4, 16, SM8250_MASTER_LLCC);
0137 DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MASTER_GEM_NOC_PCIE_SNOC);
0138 DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4);
0139 DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4);
0140 DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4);
0141 DEFINE_QNODE(ipa_core_slave, SM8250_SLAVE_IPA_CORE, 1, 8);
0142 DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4);
0143 DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC);
0144 DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC);
0145 DEFINE_QNODE(srvc_mnoc, SM8250_SLAVE_SERVICE_MNOC, 1, 4);
0146 DEFINE_QNODE(qhs_cal_dp0, SM8250_SLAVE_NPU_CAL_DP0, 1, 4);
0147 DEFINE_QNODE(qhs_cal_dp1, SM8250_SLAVE_NPU_CAL_DP1, 1, 4);
0148 DEFINE_QNODE(qhs_cp, SM8250_SLAVE_NPU_CP, 1, 4);
0149 DEFINE_QNODE(qhs_dma_bwmon, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
0150 DEFINE_QNODE(qhs_dpm, SM8250_SLAVE_NPU_DPM, 1, 4);
0151 DEFINE_QNODE(qhs_isense, SM8250_SLAVE_ISENSE_CFG, 1, 4);
0152 DEFINE_QNODE(qhs_llm, SM8250_SLAVE_NPU_LLM_CFG, 1, 4);
0153 DEFINE_QNODE(qhs_tcm, SM8250_SLAVE_NPU_TCM, 1, 4);
0154 DEFINE_QNODE(qns_npu_sys, SM8250_SLAVE_NPU_COMPUTE_NOC, 2, 32);
0155 DEFINE_QNODE(srvc_noc, SM8250_SLAVE_SERVICE_NPU_NOC, 1, 4);
0156 DEFINE_QNODE(qhs_apss, SM8250_SLAVE_APPSS, 1, 8);
0157 DEFINE_QNODE(qns_cnoc, SM8250_SNOC_CNOC_SLV, 1, 8, SM8250_SNOC_CNOC_MAS);
0158 DEFINE_QNODE(qns_gemnoc_gc, SM8250_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8250_MASTER_SNOC_GC_MEM_NOC);
0159 DEFINE_QNODE(qns_gemnoc_sf, SM8250_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8250_MASTER_SNOC_SF_MEM_NOC);
0160 DEFINE_QNODE(qxs_imem, SM8250_SLAVE_OCIMEM, 1, 8);
0161 DEFINE_QNODE(qxs_pimem, SM8250_SLAVE_PIMEM, 1, 8);
0162 DEFINE_QNODE(srvc_snoc, SM8250_SLAVE_SERVICE_SNOC, 1, 4);
0163 DEFINE_QNODE(xs_pcie_0, SM8250_SLAVE_PCIE_0, 1, 8);
0164 DEFINE_QNODE(xs_pcie_1, SM8250_SLAVE_PCIE_1, 1, 8);
0165 DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8);
0166 DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4);
0167 DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8);
0168
0169 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
0170 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
0171 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
0172 DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
0173 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
0174 DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
0175 DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
0176 DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
0177 DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
0178 DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2, &qhm_qup0);
0179 DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
0180 DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp);
0181 DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
0182 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
0183 DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
0184 DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
0185 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
0186 DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
0187 DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
0188 DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
0189 DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
0190 DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie_modem);
0191 DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1);
0192 DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
0193 DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
0194 DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie);
0195 DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc);
0196 DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc);
0197
0198 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
0199 &bcm_qup0,
0200 &bcm_sn12,
0201 };
0202
0203 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
0204 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
0205 [MASTER_QSPI_0] = &qhm_qspi,
0206 [MASTER_QUP_1] = &qhm_qup1,
0207 [MASTER_QUP_2] = &qhm_qup2,
0208 [MASTER_TSIF] = &qhm_tsif,
0209 [MASTER_PCIE_2] = &xm_pcie3_modem,
0210 [MASTER_SDCC_4] = &xm_sdc4,
0211 [MASTER_UFS_MEM] = &xm_ufs_mem,
0212 [MASTER_USB3] = &xm_usb3_0,
0213 [MASTER_USB3_1] = &xm_usb3_1,
0214 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
0215 [SLAVE_ANOC_PCIE_GEM_NOC_1] = &qns_pcie_modem_mem_noc,
0216 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
0217 };
0218
0219 static const struct qcom_icc_desc sm8250_aggre1_noc = {
0220 .nodes = aggre1_noc_nodes,
0221 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
0222 .bcms = aggre1_noc_bcms,
0223 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
0224 };
0225
0226 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
0227 &bcm_ce0,
0228 &bcm_qup0,
0229 &bcm_sn12,
0230 };
0231
0232 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
0233 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
0234 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
0235 [MASTER_QUP_0] = &qhm_qup0,
0236 [MASTER_CNOC_A2NOC] = &qnm_cnoc,
0237 [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
0238 [MASTER_IPA] = &qxm_ipa,
0239 [MASTER_PCIE] = &xm_pcie3_0,
0240 [MASTER_PCIE_1] = &xm_pcie3_1,
0241 [MASTER_QDSS_ETR] = &xm_qdss_etr,
0242 [MASTER_SDCC_2] = &xm_sdc2,
0243 [MASTER_UFS_CARD] = &xm_ufs_card,
0244 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
0245 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
0246 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
0247 };
0248
0249 static const struct qcom_icc_desc sm8250_aggre2_noc = {
0250 .nodes = aggre2_noc_nodes,
0251 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
0252 .bcms = aggre2_noc_bcms,
0253 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
0254 };
0255
0256 static struct qcom_icc_bcm * const compute_noc_bcms[] = {
0257 &bcm_co0,
0258 &bcm_co2,
0259 };
0260
0261 static struct qcom_icc_node * const compute_noc_nodes[] = {
0262 [MASTER_NPU] = &qnm_npu,
0263 [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
0264 };
0265
0266 static const struct qcom_icc_desc sm8250_compute_noc = {
0267 .nodes = compute_noc_nodes,
0268 .num_nodes = ARRAY_SIZE(compute_noc_nodes),
0269 .bcms = compute_noc_bcms,
0270 .num_bcms = ARRAY_SIZE(compute_noc_bcms),
0271 };
0272
0273 static struct qcom_icc_bcm * const config_noc_bcms[] = {
0274 &bcm_cn0,
0275 };
0276
0277 static struct qcom_icc_node * const config_noc_nodes[] = {
0278 [SNOC_CNOC_MAS] = &qnm_snoc,
0279 [MASTER_QDSS_DAP] = &xm_qdss_dap,
0280 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
0281 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
0282 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
0283 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
0284 [SLAVE_AOSS] = &qhs_aoss,
0285 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
0286 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
0287 [SLAVE_CDSP_CFG] = &qhs_compute_dsp,
0288 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
0289 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
0290 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
0291 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
0292 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
0293 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
0294 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
0295 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
0296 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
0297 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
0298 [SLAVE_IPA_CFG] = &qhs_ipa,
0299 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
0300 [SLAVE_LPASS] = &qhs_lpass_cfg,
0301 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
0302 [SLAVE_NPU_CFG] = &qhs_npu_cfg,
0303 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
0304 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
0305 [SLAVE_PCIE_2_CFG] = &qhs_pcie_modem_cfg,
0306 [SLAVE_PDM] = &qhs_pdm,
0307 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
0308 [SLAVE_PRNG] = &qhs_prng,
0309 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
0310 [SLAVE_QSPI_0] = &qhs_qspi,
0311 [SLAVE_QUP_0] = &qhs_qup0,
0312 [SLAVE_QUP_1] = &qhs_qup1,
0313 [SLAVE_QUP_2] = &qhs_qup2,
0314 [SLAVE_SDCC_2] = &qhs_sdc2,
0315 [SLAVE_SDCC_4] = &qhs_sdc4,
0316 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
0317 [SLAVE_TCSR] = &qhs_tcsr,
0318 [SLAVE_TLMM_NORTH] = &qhs_tlmm0,
0319 [SLAVE_TLMM_SOUTH] = &qhs_tlmm1,
0320 [SLAVE_TLMM_WEST] = &qhs_tlmm2,
0321 [SLAVE_TSIF] = &qhs_tsif,
0322 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
0323 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
0324 [SLAVE_USB3] = &qhs_usb3_0,
0325 [SLAVE_USB3_1] = &qhs_usb3_1,
0326 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
0327 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
0328 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
0329 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
0330 };
0331
0332 static const struct qcom_icc_desc sm8250_config_noc = {
0333 .nodes = config_noc_nodes,
0334 .num_nodes = ARRAY_SIZE(config_noc_nodes),
0335 .bcms = config_noc_bcms,
0336 .num_bcms = ARRAY_SIZE(config_noc_bcms),
0337 };
0338
0339 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
0340 };
0341
0342 static struct qcom_icc_node * const dc_noc_nodes[] = {
0343 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
0344 [SLAVE_LLCC_CFG] = &qhs_llcc,
0345 [SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
0346 };
0347
0348 static const struct qcom_icc_desc sm8250_dc_noc = {
0349 .nodes = dc_noc_nodes,
0350 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
0351 .bcms = dc_noc_bcms,
0352 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
0353 };
0354
0355 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
0356 &bcm_sh0,
0357 &bcm_sh2,
0358 &bcm_sh3,
0359 &bcm_sh4,
0360 };
0361
0362 static struct qcom_icc_node * const gem_noc_nodes[] = {
0363 [MASTER_GPU_TCU] = &alm_gpu_tcu,
0364 [MASTER_SYS_TCU] = &alm_sys_tcu,
0365 [MASTER_AMPSS_M0] = &chm_apps,
0366 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
0367 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
0368 [MASTER_GRAPHICS_3D] = &qnm_gpu,
0369 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
0370 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
0371 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
0372 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
0373 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
0374 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
0375 [SLAVE_LLCC] = &qns_llcc,
0376 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
0377 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
0378 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
0379 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
0380 };
0381
0382 static const struct qcom_icc_desc sm8250_gem_noc = {
0383 .nodes = gem_noc_nodes,
0384 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
0385 .bcms = gem_noc_bcms,
0386 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
0387 };
0388
0389 static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
0390 &bcm_ip0,
0391 };
0392
0393 static struct qcom_icc_node * const ipa_virt_nodes[] = {
0394 [MASTER_IPA_CORE] = &ipa_core_master,
0395 [SLAVE_IPA_CORE] = &ipa_core_slave,
0396 };
0397
0398 static const struct qcom_icc_desc sm8250_ipa_virt = {
0399 .nodes = ipa_virt_nodes,
0400 .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
0401 .bcms = ipa_virt_bcms,
0402 .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
0403 };
0404
0405 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
0406 &bcm_acv,
0407 &bcm_mc0,
0408 };
0409
0410 static struct qcom_icc_node * const mc_virt_nodes[] = {
0411 [MASTER_LLCC] = &llcc_mc,
0412 [SLAVE_EBI_CH0] = &ebi,
0413 };
0414
0415 static const struct qcom_icc_desc sm8250_mc_virt = {
0416 .nodes = mc_virt_nodes,
0417 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
0418 .bcms = mc_virt_bcms,
0419 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
0420 };
0421
0422 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
0423 &bcm_mm0,
0424 &bcm_mm1,
0425 &bcm_mm2,
0426 &bcm_mm3,
0427 };
0428
0429 static struct qcom_icc_node * const mmss_noc_nodes[] = {
0430 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
0431 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
0432 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
0433 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
0434 [MASTER_VIDEO_P0] = &qnm_video0,
0435 [MASTER_VIDEO_P1] = &qnm_video1,
0436 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
0437 [MASTER_MDP_PORT0] = &qxm_mdp0,
0438 [MASTER_MDP_PORT1] = &qxm_mdp1,
0439 [MASTER_ROTATOR] = &qxm_rot,
0440 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
0441 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
0442 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
0443 };
0444
0445 static const struct qcom_icc_desc sm8250_mmss_noc = {
0446 .nodes = mmss_noc_nodes,
0447 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
0448 .bcms = mmss_noc_bcms,
0449 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
0450 };
0451
0452 static struct qcom_icc_bcm * const npu_noc_bcms[] = {
0453 };
0454
0455 static struct qcom_icc_node * const npu_noc_nodes[] = {
0456 [MASTER_NPU_SYS] = &amm_npu_sys,
0457 [MASTER_NPU_CDP] = &amm_npu_sys_cdp_w,
0458 [MASTER_NPU_NOC_CFG] = &qhm_cfg,
0459 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
0460 [SLAVE_NPU_CAL_DP1] = &qhs_cal_dp1,
0461 [SLAVE_NPU_CP] = &qhs_cp,
0462 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
0463 [SLAVE_NPU_DPM] = &qhs_dpm,
0464 [SLAVE_ISENSE_CFG] = &qhs_isense,
0465 [SLAVE_NPU_LLM_CFG] = &qhs_llm,
0466 [SLAVE_NPU_TCM] = &qhs_tcm,
0467 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
0468 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
0469 };
0470
0471 static const struct qcom_icc_desc sm8250_npu_noc = {
0472 .nodes = npu_noc_nodes,
0473 .num_nodes = ARRAY_SIZE(npu_noc_nodes),
0474 .bcms = npu_noc_bcms,
0475 .num_bcms = ARRAY_SIZE(npu_noc_bcms),
0476 };
0477
0478 static struct qcom_icc_bcm * const system_noc_bcms[] = {
0479 &bcm_sn0,
0480 &bcm_sn1,
0481 &bcm_sn11,
0482 &bcm_sn2,
0483 &bcm_sn3,
0484 &bcm_sn4,
0485 &bcm_sn5,
0486 &bcm_sn6,
0487 &bcm_sn7,
0488 &bcm_sn8,
0489 &bcm_sn9,
0490 };
0491
0492 static struct qcom_icc_node * const system_noc_nodes[] = {
0493 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
0494 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
0495 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
0496 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
0497 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
0498 [MASTER_PIMEM] = &qxm_pimem,
0499 [MASTER_GIC] = &xm_gic,
0500 [SLAVE_APPSS] = &qhs_apss,
0501 [SNOC_CNOC_SLV] = &qns_cnoc,
0502 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
0503 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
0504 [SLAVE_OCIMEM] = &qxs_imem,
0505 [SLAVE_PIMEM] = &qxs_pimem,
0506 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
0507 [SLAVE_PCIE_0] = &xs_pcie_0,
0508 [SLAVE_PCIE_1] = &xs_pcie_1,
0509 [SLAVE_PCIE_2] = &xs_pcie_modem,
0510 [SLAVE_QDSS_STM] = &xs_qdss_stm,
0511 [SLAVE_TCU] = &xs_sys_tcu_cfg,
0512 };
0513
0514 static const struct qcom_icc_desc sm8250_system_noc = {
0515 .nodes = system_noc_nodes,
0516 .num_nodes = ARRAY_SIZE(system_noc_nodes),
0517 .bcms = system_noc_bcms,
0518 .num_bcms = ARRAY_SIZE(system_noc_bcms),
0519 };
0520
0521 static const struct of_device_id qnoc_of_match[] = {
0522 { .compatible = "qcom,sm8250-aggre1-noc",
0523 .data = &sm8250_aggre1_noc},
0524 { .compatible = "qcom,sm8250-aggre2-noc",
0525 .data = &sm8250_aggre2_noc},
0526 { .compatible = "qcom,sm8250-compute-noc",
0527 .data = &sm8250_compute_noc},
0528 { .compatible = "qcom,sm8250-config-noc",
0529 .data = &sm8250_config_noc},
0530 { .compatible = "qcom,sm8250-dc-noc",
0531 .data = &sm8250_dc_noc},
0532 { .compatible = "qcom,sm8250-gem-noc",
0533 .data = &sm8250_gem_noc},
0534 { .compatible = "qcom,sm8250-ipa-virt",
0535 .data = &sm8250_ipa_virt},
0536 { .compatible = "qcom,sm8250-mc-virt",
0537 .data = &sm8250_mc_virt},
0538 { .compatible = "qcom,sm8250-mmss-noc",
0539 .data = &sm8250_mmss_noc},
0540 { .compatible = "qcom,sm8250-npu-noc",
0541 .data = &sm8250_npu_noc},
0542 { .compatible = "qcom,sm8250-system-noc",
0543 .data = &sm8250_system_noc},
0544 { }
0545 };
0546 MODULE_DEVICE_TABLE(of, qnoc_of_match);
0547
0548 static struct platform_driver qnoc_driver = {
0549 .probe = qcom_icc_rpmh_probe,
0550 .remove = qcom_icc_rpmh_remove,
0551 .driver = {
0552 .name = "qnoc-sm8250",
0553 .of_match_table = qnoc_of_match,
0554 },
0555 };
0556 module_platform_driver(qnoc_driver);
0557
0558 MODULE_DESCRIPTION("Qualcomm SM8250 NoC driver");
0559 MODULE_LICENSE("GPL v2");
