interconnect/qcom/sm8150.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
0004  *
0005  */
0006
0007 #include <linux/device.h>
0008 #include <linux/interconnect.h>
0009 #include <linux/interconnect-provider.h>
0010 #include <linux/module.h>
0011 #include <linux/of_platform.h>
0012 #include <dt-bindings/interconnect/qcom,sm8150.h>
0013
0014 #include "bcm-voter.h"
0015 #include "icc-rpmh.h"
0016 #include "sm8150.h"
0017
0018 DEFINE_QNODE(qhm_a1noc_cfg, SM8150_MASTER_A1NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A1NOC);
0019 DEFINE_QNODE(qhm_qup0, SM8150_MASTER_QUP_0, 1, 4, SM8150_A1NOC_SNOC_SLV);
0020 DEFINE_QNODE(xm_emac, SM8150_MASTER_EMAC, 1, 8, SM8150_A1NOC_SNOC_SLV);
0021 DEFINE_QNODE(xm_ufs_mem, SM8150_MASTER_UFS_MEM, 1, 8, SM8150_A1NOC_SNOC_SLV);
0022 DEFINE_QNODE(xm_usb3_0, SM8150_MASTER_USB3, 1, 8, SM8150_A1NOC_SNOC_SLV);
0023 DEFINE_QNODE(xm_usb3_1, SM8150_MASTER_USB3_1, 1, 8, SM8150_A1NOC_SNOC_SLV);
0024 DEFINE_QNODE(qhm_a2noc_cfg, SM8150_MASTER_A2NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A2NOC);
0025 DEFINE_QNODE(qhm_qdss_bam, SM8150_MASTER_QDSS_BAM, 1, 4, SM8150_A2NOC_SNOC_SLV);
0026 DEFINE_QNODE(qhm_qspi, SM8150_MASTER_QSPI, 1, 4, SM8150_A2NOC_SNOC_SLV);
0027 DEFINE_QNODE(qhm_qup1, SM8150_MASTER_QUP_1, 1, 4, SM8150_A2NOC_SNOC_SLV);
0028 DEFINE_QNODE(qhm_qup2, SM8150_MASTER_QUP_2, 1, 4, SM8150_A2NOC_SNOC_SLV);
0029 DEFINE_QNODE(qhm_sensorss_ahb, SM8150_MASTER_SENSORS_AHB, 1, 4, SM8150_A2NOC_SNOC_SLV);
0030 DEFINE_QNODE(qhm_tsif, SM8150_MASTER_TSIF, 1, 4, SM8150_A2NOC_SNOC_SLV);
0031 DEFINE_QNODE(qnm_cnoc, SM8150_MASTER_CNOC_A2NOC, 1, 8, SM8150_A2NOC_SNOC_SLV);
0032 DEFINE_QNODE(qxm_crypto, SM8150_MASTER_CRYPTO_CORE_0, 1, 8, SM8150_A2NOC_SNOC_SLV);
0033 DEFINE_QNODE(qxm_ipa, SM8150_MASTER_IPA, 1, 8, SM8150_A2NOC_SNOC_SLV);
0034 DEFINE_QNODE(xm_pcie3_0, SM8150_MASTER_PCIE, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
0035 DEFINE_QNODE(xm_pcie3_1, SM8150_MASTER_PCIE_1, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC);
0036 DEFINE_QNODE(xm_qdss_etr, SM8150_MASTER_QDSS_ETR, 1, 8, SM8150_A2NOC_SNOC_SLV);
0037 DEFINE_QNODE(xm_sdc2, SM8150_MASTER_SDCC_2, 1, 8, SM8150_A2NOC_SNOC_SLV);
0038 DEFINE_QNODE(xm_sdc4, SM8150_MASTER_SDCC_4, 1, 8, SM8150_A2NOC_SNOC_SLV);
0039 DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM8150_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
0040 DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SM8150_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
0041 DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM8150_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP);
0042 DEFINE_QNODE(qnm_npu, SM8150_MASTER_NPU, 1, 32, SM8150_SLAVE_CDSP_MEM_NOC);
0043 DEFINE_QNODE(qhm_spdm, SM8150_MASTER_SPDM, 1, 4, SM8150_SLAVE_CNOC_A2NOC);
0044 DEFINE_QNODE(qnm_snoc, SM8150_SNOC_CNOC_MAS, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
0045 DEFINE_QNODE(xm_qdss_dap, SM8150_MASTER_QDSS_DAP, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_CNOC_A2NOC, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG);
0046 DEFINE_QNODE(qhm_cnoc_dc_noc, SM8150_MASTER_CNOC_DC_NOC, 1, 4, SM8150_SLAVE_GEM_NOC_CFG, SM8150_SLAVE_LLCC_CFG);
0047 DEFINE_QNODE(acm_apps, SM8150_MASTER_AMPSS_M0, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
0048 DEFINE_QNODE(acm_gpu_tcu, SM8150_MASTER_GPU_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
0049 DEFINE_QNODE(acm_sys_tcu, SM8150_MASTER_SYS_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
0050 DEFINE_QNODE(qhm_gemnoc_cfg, SM8150_MASTER_GEM_NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_GEM_NOC, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG);
0051 DEFINE_QNODE(qnm_cmpnoc, SM8150_MASTER_COMPUTE_NOC, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
0052 DEFINE_QNODE(qnm_gpu, SM8150_MASTER_GRAPHICS_3D, 2, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
0053 DEFINE_QNODE(qnm_mnoc_hf, SM8150_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8150_SLAVE_LLCC);
0054 DEFINE_QNODE(qnm_mnoc_sf, SM8150_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
0055 DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC);
0056 DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAVE_LLCC);
0057 DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLAVE_LLCC);
0058 DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC);
0059 DEFINE_QNODE(ipa_core_master, SM8150_MASTER_IPA_CORE, 1, 8, SM8150_SLAVE_IPA_CORE);
0060 DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0);
0061 DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_MNOC);
0062 DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
0063 DEFINE_QNODE(qxm_camnoc_hf1, SM8150_MASTER_CAMNOC_HF1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
0064 DEFINE_QNODE(qxm_camnoc_sf, SM8150_MASTER_CAMNOC_SF, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
0065 DEFINE_QNODE(qxm_mdp0, SM8150_MASTER_MDP_PORT0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
0066 DEFINE_QNODE(qxm_mdp1, SM8150_MASTER_MDP_PORT1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC);
0067 DEFINE_QNODE(qxm_rot, SM8150_MASTER_ROTATOR, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
0068 DEFINE_QNODE(qxm_venus0, SM8150_MASTER_VIDEO_P0, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
0069 DEFINE_QNODE(qxm_venus1, SM8150_MASTER_VIDEO_P1, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC);
0070 DEFINE_QNODE(qxm_venus_arm9, SM8150_MASTER_VIDEO_PROC, 1, 8, SM8150_SLAVE_MNOC_SF_MEM_NOC);
0071 DEFINE_QNODE(qhm_snoc_cfg, SM8150_MASTER_SNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_SNOC);
0072 DEFINE_QNODE(qnm_aggre1_noc, SM8150_A1NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_QDSS_STM);
0073 DEFINE_QNODE(qnm_aggre2_noc, SM8150_A2NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_PCIE_0, SM8150_SLAVE_PCIE_1, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
0074 DEFINE_QNODE(qnm_gemnoc, SM8150_MASTER_GEM_NOC_SNOC, 1, 8, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM);
0075 DEFINE_QNODE(qxm_pimem, SM8150_MASTER_PIMEM, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
0076 DEFINE_QNODE(xm_gic, SM8150_MASTER_GIC, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM);
0077 DEFINE_QNODE(qns_a1noc_snoc, SM8150_A1NOC_SNOC_SLV, 1, 16, SM8150_A1NOC_SNOC_MAS);
0078 DEFINE_QNODE(srvc_aggre1_noc, SM8150_SLAVE_SERVICE_A1NOC, 1, 4);
0079 DEFINE_QNODE(qns_a2noc_snoc, SM8150_A2NOC_SNOC_SLV, 1, 16, SM8150_A2NOC_SNOC_MAS);
0080 DEFINE_QNODE(qns_pcie_mem_noc, SM8150_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8150_MASTER_GEM_NOC_PCIE_SNOC);
0081 DEFINE_QNODE(srvc_aggre2_noc, SM8150_SLAVE_SERVICE_A2NOC, 1, 4);
0082 DEFINE_QNODE(qns_camnoc_uncomp, SM8150_SLAVE_CAMNOC_UNCOMP, 1, 32);
0083 DEFINE_QNODE(qns_cdsp_mem_noc, SM8150_SLAVE_CDSP_MEM_NOC, 2, 32, SM8150_MASTER_COMPUTE_NOC);
0084 DEFINE_QNODE(qhs_a1_noc_cfg, SM8150_SLAVE_A1NOC_CFG, 1, 4, SM8150_MASTER_A1NOC_CFG);
0085 DEFINE_QNODE(qhs_a2_noc_cfg, SM8150_SLAVE_A2NOC_CFG, 1, 4, SM8150_MASTER_A2NOC_CFG);
0086 DEFINE_QNODE(qhs_ahb2phy_south, SM8150_SLAVE_AHB2PHY_SOUTH, 1, 4);
0087 DEFINE_QNODE(qhs_aop, SM8150_SLAVE_AOP, 1, 4);
0088 DEFINE_QNODE(qhs_aoss, SM8150_SLAVE_AOSS, 1, 4);
0089 DEFINE_QNODE(qhs_camera_cfg, SM8150_SLAVE_CAMERA_CFG, 1, 4);
0090 DEFINE_QNODE(qhs_clk_ctl, SM8150_SLAVE_CLK_CTL, 1, 4);
0091 DEFINE_QNODE(qhs_compute_dsp, SM8150_SLAVE_CDSP_CFG, 1, 4);
0092 DEFINE_QNODE(qhs_cpr_cx, SM8150_SLAVE_RBCPR_CX_CFG, 1, 4);
0093 DEFINE_QNODE(qhs_cpr_mmcx, SM8150_SLAVE_RBCPR_MMCX_CFG, 1, 4);
0094 DEFINE_QNODE(qhs_cpr_mx, SM8150_SLAVE_RBCPR_MX_CFG, 1, 4);
0095 DEFINE_QNODE(qhs_crypto0_cfg, SM8150_SLAVE_CRYPTO_0_CFG, 1, 4);
0096 DEFINE_QNODE(qhs_ddrss_cfg, SM8150_SLAVE_CNOC_DDRSS, 1, 4, SM8150_MASTER_CNOC_DC_NOC);
0097 DEFINE_QNODE(qhs_display_cfg, SM8150_SLAVE_DISPLAY_CFG, 1, 4);
0098 DEFINE_QNODE(qhs_emac_cfg, SM8150_SLAVE_EMAC_CFG, 1, 4);
0099 DEFINE_QNODE(qhs_glm, SM8150_SLAVE_GLM, 1, 4);
0100 DEFINE_QNODE(qhs_gpuss_cfg, SM8150_SLAVE_GRAPHICS_3D_CFG, 1, 8);
0101 DEFINE_QNODE(qhs_imem_cfg, SM8150_SLAVE_IMEM_CFG, 1, 4);
0102 DEFINE_QNODE(qhs_ipa, SM8150_SLAVE_IPA_CFG, 1, 4);
0103 DEFINE_QNODE(qhs_mnoc_cfg, SM8150_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8150_MASTER_CNOC_MNOC_CFG);
0104 DEFINE_QNODE(qhs_npu_cfg, SM8150_SLAVE_NPU_CFG, 1, 4);
0105 DEFINE_QNODE(qhs_pcie0_cfg, SM8150_SLAVE_PCIE_0_CFG, 1, 4);
0106 DEFINE_QNODE(qhs_pcie1_cfg, SM8150_SLAVE_PCIE_1_CFG, 1, 4);
0107 DEFINE_QNODE(qhs_phy_refgen_north, SM8150_SLAVE_NORTH_PHY_CFG, 1, 4);
0108 DEFINE_QNODE(qhs_pimem_cfg, SM8150_SLAVE_PIMEM_CFG, 1, 4);
0109 DEFINE_QNODE(qhs_prng, SM8150_SLAVE_PRNG, 1, 4);
0110 DEFINE_QNODE(qhs_qdss_cfg, SM8150_SLAVE_QDSS_CFG, 1, 4);
0111 DEFINE_QNODE(qhs_qspi, SM8150_SLAVE_QSPI, 1, 4);
0112 DEFINE_QNODE(qhs_qupv3_east, SM8150_SLAVE_QUP_2, 1, 4);
0113 DEFINE_QNODE(qhs_qupv3_north, SM8150_SLAVE_QUP_1, 1, 4);
0114 DEFINE_QNODE(qhs_qupv3_south, SM8150_SLAVE_QUP_0, 1, 4);
0115 DEFINE_QNODE(qhs_sdc2, SM8150_SLAVE_SDCC_2, 1, 4);
0116 DEFINE_QNODE(qhs_sdc4, SM8150_SLAVE_SDCC_4, 1, 4);
0117 DEFINE_QNODE(qhs_snoc_cfg, SM8150_SLAVE_SNOC_CFG, 1, 4, SM8150_MASTER_SNOC_CFG);
0118 DEFINE_QNODE(qhs_spdm, SM8150_SLAVE_SPDM_WRAPPER, 1, 4);
0119 DEFINE_QNODE(qhs_spss_cfg, SM8150_SLAVE_SPSS_CFG, 1, 4);
0120 DEFINE_QNODE(qhs_ssc_cfg, SM8150_SLAVE_SSC_CFG, 1, 4);
0121 DEFINE_QNODE(qhs_tcsr, SM8150_SLAVE_TCSR, 1, 4);
0122 DEFINE_QNODE(qhs_tlmm_east, SM8150_SLAVE_TLMM_EAST, 1, 4);
0123 DEFINE_QNODE(qhs_tlmm_north, SM8150_SLAVE_TLMM_NORTH, 1, 4);
0124 DEFINE_QNODE(qhs_tlmm_south, SM8150_SLAVE_TLMM_SOUTH, 1, 4);
0125 DEFINE_QNODE(qhs_tlmm_west, SM8150_SLAVE_TLMM_WEST, 1, 4);
0126 DEFINE_QNODE(qhs_tsif, SM8150_SLAVE_TSIF, 1, 4);
0127 DEFINE_QNODE(qhs_ufs_card_cfg, SM8150_SLAVE_UFS_CARD_CFG, 1, 4);
0128 DEFINE_QNODE(qhs_ufs_mem_cfg, SM8150_SLAVE_UFS_MEM_CFG, 1, 4);
0129 DEFINE_QNODE(qhs_usb3_0, SM8150_SLAVE_USB3, 1, 4);
0130 DEFINE_QNODE(qhs_usb3_1, SM8150_SLAVE_USB3_1, 1, 4);
0131 DEFINE_QNODE(qhs_venus_cfg, SM8150_SLAVE_VENUS_CFG, 1, 4);
0132 DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8150_SLAVE_VSENSE_CTRL_CFG, 1, 4);
0133 DEFINE_QNODE(qns_cnoc_a2noc, SM8150_SLAVE_CNOC_A2NOC, 1, 8, SM8150_MASTER_CNOC_A2NOC);
0134 DEFINE_QNODE(srvc_cnoc, SM8150_SLAVE_SERVICE_CNOC, 1, 4);
0135 DEFINE_QNODE(qhs_llcc, SM8150_SLAVE_LLCC_CFG, 1, 4);
0136 DEFINE_QNODE(qhs_memnoc, SM8150_SLAVE_GEM_NOC_CFG, 1, 4, SM8150_MASTER_GEM_NOC_CFG);
0137 DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
0138 DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32);
0139 DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MASTER_GEM_NOC_SNOC);
0140 DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC);
0141 DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4);
0142 DEFINE_QNODE(ipa_core_slave, SM8150_SLAVE_IPA_CORE, 1, 8);
0143 DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4);
0144 DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC);
0145 DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC);
0146 DEFINE_QNODE(srvc_mnoc, SM8150_SLAVE_SERVICE_MNOC, 1, 4);
0147 DEFINE_QNODE(qhs_apss, SM8150_SLAVE_APPSS, 1, 8);
0148 DEFINE_QNODE(qns_cnoc, SM8150_SNOC_CNOC_SLV, 1, 8, SM8150_SNOC_CNOC_MAS);
0149 DEFINE_QNODE(qns_gemnoc_gc, SM8150_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8150_MASTER_SNOC_GC_MEM_NOC);
0150 DEFINE_QNODE(qns_gemnoc_sf, SM8150_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8150_MASTER_SNOC_SF_MEM_NOC);
0151 DEFINE_QNODE(qxs_imem, SM8150_SLAVE_OCIMEM, 1, 8);
0152 DEFINE_QNODE(qxs_pimem, SM8150_SLAVE_PIMEM, 1, 8);
0153 DEFINE_QNODE(srvc_snoc, SM8150_SLAVE_SERVICE_SNOC, 1, 4);
0154 DEFINE_QNODE(xs_pcie_0, SM8150_SLAVE_PCIE_0, 1, 8);
0155 DEFINE_QNODE(xs_pcie_1, SM8150_SLAVE_PCIE_1, 1, 8);
0156 DEFINE_QNODE(xs_qdss_stm, SM8150_SLAVE_QDSS_STM, 1, 4);
0157 DEFINE_QNODE(xs_sys_tcu_cfg, SM8150_SLAVE_TCU, 1, 8);
0158
0159 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
0160 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
0161 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
0162 DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
0163 DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
0164 DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_gem_noc_snoc);
0165 DEFINE_QBCM(bcm_mm2, "MM2", false, &qxm_camnoc_sf, &qns2_mem_noc);
0166 DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_gpu_tcu, &acm_sys_tcu);
0167 DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
0168 DEFINE_QBCM(bcm_sh4, "SH4", false, &qnm_cmpnoc);
0169 DEFINE_QBCM(bcm_sh5, "SH5", false, &acm_apps);
0170 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
0171 DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
0172 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
0173 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
0174 DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu);
0175 DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
0176 DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ssc_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tlmm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
0177 DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2);
0178 DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
0179 DEFINE_QBCM(bcm_sn3, "SN3", false, &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc);
0180 DEFINE_QBCM(bcm_sn4, "SN4", false, &qxs_pimem);
0181 DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
0182 DEFINE_QBCM(bcm_sn8, "SN8", false, &xs_pcie_0, &xs_pcie_1);
0183 DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre1_noc);
0184 DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_aggre2_noc);
0185 DEFINE_QBCM(bcm_sn12, "SN12", false, &qxm_pimem, &xm_gic);
0186 DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc);
0187 DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_gemnoc);
0188
0189 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
0190     &bcm_qup0,
0191     &bcm_sn3,
0192 };
0193
0194 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
0195     [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
0196     [MASTER_QUP_0] = &qhm_qup0,
0197     [MASTER_EMAC] = &xm_emac,
0198     [MASTER_UFS_MEM] = &xm_ufs_mem,
0199     [MASTER_USB3] = &xm_usb3_0,
0200     [MASTER_USB3_1] = &xm_usb3_1,
0201     [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
0202     [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
0203 };
0204
0205 static const struct qcom_icc_desc sm8150_aggre1_noc = {
0206     .nodes = aggre1_noc_nodes,
0207     .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
0208     .bcms = aggre1_noc_bcms,
0209     .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
0210 };
0211
0212 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
0213     &bcm_ce0,
0214     &bcm_qup0,
0215     &bcm_sn14,
0216     &bcm_sn3,
0217 };
0218
0219 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
0220     [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
0221     [MASTER_QDSS_BAM] = &qhm_qdss_bam,
0222     [MASTER_QSPI] = &qhm_qspi,
0223     [MASTER_QUP_1] = &qhm_qup1,
0224     [MASTER_QUP_2] = &qhm_qup2,
0225     [MASTER_SENSORS_AHB] = &qhm_sensorss_ahb,
0226     [MASTER_TSIF] = &qhm_tsif,
0227     [MASTER_CNOC_A2NOC] = &qnm_cnoc,
0228     [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
0229     [MASTER_IPA] = &qxm_ipa,
0230     [MASTER_PCIE] = &xm_pcie3_0,
0231     [MASTER_PCIE_1] = &xm_pcie3_1,
0232     [MASTER_QDSS_ETR] = &xm_qdss_etr,
0233     [MASTER_SDCC_2] = &xm_sdc2,
0234     [MASTER_SDCC_4] = &xm_sdc4,
0235     [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
0236     [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
0237     [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
0238 };
0239
0240 static const struct qcom_icc_desc sm8150_aggre2_noc = {
0241     .nodes = aggre2_noc_nodes,
0242     .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
0243     .bcms = aggre2_noc_bcms,
0244     .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
0245 };
0246
0247 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
0248     &bcm_mm1,
0249 };
0250
0251 static struct qcom_icc_node * const camnoc_virt_nodes[] = {
0252     [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
0253     [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
0254     [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
0255     [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
0256 };
0257
0258 static const struct qcom_icc_desc sm8150_camnoc_virt = {
0259     .nodes = camnoc_virt_nodes,
0260     .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
0261     .bcms = camnoc_virt_bcms,
0262     .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
0263 };
0264
0265 static struct qcom_icc_bcm * const compute_noc_bcms[] = {
0266     &bcm_co0,
0267     &bcm_co1,
0268 };
0269
0270 static struct qcom_icc_node * const compute_noc_nodes[] = {
0271     [MASTER_NPU] = &qnm_npu,
0272     [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc,
0273 };
0274
0275 static const struct qcom_icc_desc sm8150_compute_noc = {
0276     .nodes = compute_noc_nodes,
0277     .num_nodes = ARRAY_SIZE(compute_noc_nodes),
0278     .bcms = compute_noc_bcms,
0279     .num_bcms = ARRAY_SIZE(compute_noc_bcms),
0280 };
0281
0282 static struct qcom_icc_bcm * const config_noc_bcms[] = {
0283     &bcm_cn0,
0284 };
0285
0286 static struct qcom_icc_node * const config_noc_nodes[] = {
0287     [MASTER_SPDM] = &qhm_spdm,
0288     [SNOC_CNOC_MAS] = &qnm_snoc,
0289     [MASTER_QDSS_DAP] = &xm_qdss_dap,
0290     [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
0291     [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
0292     [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy_south,
0293     [SLAVE_AOP] = &qhs_aop,
0294     [SLAVE_AOSS] = &qhs_aoss,
0295     [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
0296     [SLAVE_CLK_CTL] = &qhs_clk_ctl,
0297     [SLAVE_CDSP_CFG] = &qhs_compute_dsp,
0298     [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
0299     [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
0300     [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
0301     [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
0302     [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
0303     [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
0304     [SLAVE_EMAC_CFG] = &qhs_emac_cfg,
0305     [SLAVE_GLM] = &qhs_glm,
0306     [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
0307     [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
0308     [SLAVE_IPA_CFG] = &qhs_ipa,
0309     [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
0310     [SLAVE_NPU_CFG] = &qhs_npu_cfg,
0311     [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
0312     [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
0313     [SLAVE_NORTH_PHY_CFG] = &qhs_phy_refgen_north,
0314     [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
0315     [SLAVE_PRNG] = &qhs_prng,
0316     [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
0317     [SLAVE_QSPI] = &qhs_qspi,
0318     [SLAVE_QUP_2] = &qhs_qupv3_east,
0319     [SLAVE_QUP_1] = &qhs_qupv3_north,
0320     [SLAVE_QUP_0] = &qhs_qupv3_south,
0321     [SLAVE_SDCC_2] = &qhs_sdc2,
0322     [SLAVE_SDCC_4] = &qhs_sdc4,
0323     [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
0324     [SLAVE_SPDM_WRAPPER] = &qhs_spdm,
0325     [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
0326     [SLAVE_SSC_CFG] = &qhs_ssc_cfg,
0327     [SLAVE_TCSR] = &qhs_tcsr,
0328     [SLAVE_TLMM_EAST] = &qhs_tlmm_east,
0329     [SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
0330     [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
0331     [SLAVE_TLMM_WEST] = &qhs_tlmm_west,
0332     [SLAVE_TSIF] = &qhs_tsif,
0333     [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
0334     [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
0335     [SLAVE_USB3] = &qhs_usb3_0,
0336     [SLAVE_USB3_1] = &qhs_usb3_1,
0337     [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
0338     [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
0339     [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
0340     [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
0341 };
0342
0343 static const struct qcom_icc_desc sm8150_config_noc = {
0344     .nodes = config_noc_nodes,
0345     .num_nodes = ARRAY_SIZE(config_noc_nodes),
0346     .bcms = config_noc_bcms,
0347     .num_bcms = ARRAY_SIZE(config_noc_bcms),
0348 };
0349
0350 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
0351 };
0352
0353 static struct qcom_icc_node * const dc_noc_nodes[] = {
0354     [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
0355     [SLAVE_LLCC_CFG] = &qhs_llcc,
0356     [SLAVE_GEM_NOC_CFG] = &qhs_memnoc,
0357 };
0358
0359 static const struct qcom_icc_desc sm8150_dc_noc = {
0360     .nodes = dc_noc_nodes,
0361     .num_nodes = ARRAY_SIZE(dc_noc_nodes),
0362     .bcms = dc_noc_bcms,
0363     .num_bcms = ARRAY_SIZE(dc_noc_bcms),
0364 };
0365
0366 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
0367     &bcm_sh0,
0368     &bcm_sh2,
0369     &bcm_sh3,
0370     &bcm_sh4,
0371     &bcm_sh5,
0372 };
0373
0374 static struct qcom_icc_node * const gem_noc_nodes[] = {
0375     [MASTER_AMPSS_M0] = &acm_apps,
0376     [MASTER_GPU_TCU] = &acm_gpu_tcu,
0377     [MASTER_SYS_TCU] = &acm_sys_tcu,
0378     [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
0379     [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
0380     [MASTER_GRAPHICS_3D] = &qnm_gpu,
0381     [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
0382     [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
0383     [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie,
0384     [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
0385     [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
0386     [MASTER_ECC] = &qxm_ecc,
0387     [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
0388     [SLAVE_ECC] = &qns_ecc,
0389     [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
0390     [SLAVE_LLCC] = &qns_llcc,
0391     [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
0392 };
0393
0394 static const struct qcom_icc_desc sm8150_gem_noc = {
0395     .nodes = gem_noc_nodes,
0396     .num_nodes = ARRAY_SIZE(gem_noc_nodes),
0397     .bcms = gem_noc_bcms,
0398     .num_bcms = ARRAY_SIZE(gem_noc_bcms),
0399 };
0400
0401 static struct qcom_icc_bcm * const ipa_virt_bcms[] = {
0402     &bcm_ip0,
0403 };
0404
0405 static struct qcom_icc_node * const ipa_virt_nodes[] = {
0406     [MASTER_IPA_CORE] = &ipa_core_master,
0407     [SLAVE_IPA_CORE] = &ipa_core_slave,
0408 };
0409
0410 static const struct qcom_icc_desc sm8150_ipa_virt = {
0411     .nodes = ipa_virt_nodes,
0412     .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
0413     .bcms = ipa_virt_bcms,
0414     .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
0415 };
0416
0417 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
0418     &bcm_acv,
0419     &bcm_mc0,
0420 };
0421
0422 static struct qcom_icc_node * const mc_virt_nodes[] = {
0423     [MASTER_LLCC] = &llcc_mc,
0424     [SLAVE_EBI_CH0] = &ebi,
0425 };
0426
0427 static const struct qcom_icc_desc sm8150_mc_virt = {
0428     .nodes = mc_virt_nodes,
0429     .num_nodes = ARRAY_SIZE(mc_virt_nodes),
0430     .bcms = mc_virt_bcms,
0431     .num_bcms = ARRAY_SIZE(mc_virt_bcms),
0432 };
0433
0434 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
0435     &bcm_mm0,
0436     &bcm_mm1,
0437     &bcm_mm2,
0438     &bcm_mm3,
0439 };
0440
0441 static struct qcom_icc_node * const mmss_noc_nodes[] = {
0442     [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
0443     [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
0444     [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
0445     [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
0446     [MASTER_MDP_PORT0] = &qxm_mdp0,
0447     [MASTER_MDP_PORT1] = &qxm_mdp1,
0448     [MASTER_ROTATOR] = &qxm_rot,
0449     [MASTER_VIDEO_P0] = &qxm_venus0,
0450     [MASTER_VIDEO_P1] = &qxm_venus1,
0451     [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
0452     [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
0453     [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
0454     [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
0455 };
0456
0457 static const struct qcom_icc_desc sm8150_mmss_noc = {
0458     .nodes = mmss_noc_nodes,
0459     .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
0460     .bcms = mmss_noc_bcms,
0461     .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
0462 };
0463
0464 static struct qcom_icc_bcm * const system_noc_bcms[] = {
0465     &bcm_sn0,
0466     &bcm_sn1,
0467     &bcm_sn11,
0468     &bcm_sn12,
0469     &bcm_sn15,
0470     &bcm_sn2,
0471     &bcm_sn3,
0472     &bcm_sn4,
0473     &bcm_sn5,
0474     &bcm_sn8,
0475     &bcm_sn9,
0476 };
0477
0478 static struct qcom_icc_node * const system_noc_nodes[] = {
0479     [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
0480     [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
0481     [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
0482     [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
0483     [MASTER_PIMEM] = &qxm_pimem,
0484     [MASTER_GIC] = &xm_gic,
0485     [SLAVE_APPSS] = &qhs_apss,
0486     [SNOC_CNOC_SLV] = &qns_cnoc,
0487     [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
0488     [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
0489     [SLAVE_OCIMEM] = &qxs_imem,
0490     [SLAVE_PIMEM] = &qxs_pimem,
0491     [SLAVE_SERVICE_SNOC] = &srvc_snoc,
0492     [SLAVE_PCIE_0] = &xs_pcie_0,
0493     [SLAVE_PCIE_1] = &xs_pcie_1,
0494     [SLAVE_QDSS_STM] = &xs_qdss_stm,
0495     [SLAVE_TCU] = &xs_sys_tcu_cfg,
0496 };
0497
0498 static const struct qcom_icc_desc sm8150_system_noc = {
0499     .nodes = system_noc_nodes,
0500     .num_nodes = ARRAY_SIZE(system_noc_nodes),
0501     .bcms = system_noc_bcms,
0502     .num_bcms = ARRAY_SIZE(system_noc_bcms),
0503 };
0504
0505 static const struct of_device_id qnoc_of_match[] = {
0506     { .compatible = "qcom,sm8150-aggre1-noc",
0507       .data = &sm8150_aggre1_noc},
0508     { .compatible = "qcom,sm8150-aggre2-noc",
0509       .data = &sm8150_aggre2_noc},
0510     { .compatible = "qcom,sm8150-camnoc-virt",
0511       .data = &sm8150_camnoc_virt},
0512     { .compatible = "qcom,sm8150-compute-noc",
0513       .data = &sm8150_compute_noc},
0514     { .compatible = "qcom,sm8150-config-noc",
0515       .data = &sm8150_config_noc},
0516     { .compatible = "qcom,sm8150-dc-noc",
0517       .data = &sm8150_dc_noc},
0518     { .compatible = "qcom,sm8150-gem-noc",
0519       .data = &sm8150_gem_noc},
0520     { .compatible = "qcom,sm8150-ipa-virt",
0521       .data = &sm8150_ipa_virt},
0522     { .compatible = "qcom,sm8150-mc-virt",
0523       .data = &sm8150_mc_virt},
0524     { .compatible = "qcom,sm8150-mmss-noc",
0525       .data = &sm8150_mmss_noc},
0526     { .compatible = "qcom,sm8150-system-noc",
0527       .data = &sm8150_system_noc},
0528     { }
0529 };
0530 MODULE_DEVICE_TABLE(of, qnoc_of_match);
0531
0532 static struct platform_driver qnoc_driver = {
0533     .probe = qcom_icc_rpmh_probe,
0534     .remove = qcom_icc_rpmh_remove,
0535     .driver = {
0536         .name = "qnoc-sm8150",
0537         .of_match_table = qnoc_of_match,
0538     },
0539 };
0540 module_platform_driver(qnoc_driver);
0541
0542 MODULE_DESCRIPTION("Qualcomm SM8150 NoC driver");
0543 MODULE_LICENSE("GPL v2");