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0006 #include <linux/device.h>
0007 #include <linux/interconnect.h>
0008 #include <linux/interconnect-provider.h>
0009 #include <linux/module.h>
0010 #include <linux/of_platform.h>
0011 #include <dt-bindings/interconnect/qcom,sm6350.h>
0012
0013 #include "bcm-voter.h"
0014 #include "icc-rpmh.h"
0015 #include "sm6350.h"
0016
0017 DEFINE_QNODE(qhm_a1noc_cfg, SM6350_MASTER_A1NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_A1NOC);
0018 DEFINE_QNODE(qhm_qup_0, SM6350_MASTER_QUP_0, 1, 4, SM6350_A1NOC_SNOC_SLV);
0019 DEFINE_QNODE(xm_emmc, SM6350_MASTER_EMMC, 1, 8, SM6350_A1NOC_SNOC_SLV);
0020 DEFINE_QNODE(xm_ufs_mem, SM6350_MASTER_UFS_MEM, 1, 8, SM6350_A1NOC_SNOC_SLV);
0021 DEFINE_QNODE(qhm_a2noc_cfg, SM6350_MASTER_A2NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_A2NOC);
0022 DEFINE_QNODE(qhm_qdss_bam, SM6350_MASTER_QDSS_BAM, 1, 4, SM6350_A2NOC_SNOC_SLV);
0023 DEFINE_QNODE(qhm_qup_1, SM6350_MASTER_QUP_1, 1, 4, SM6350_A2NOC_SNOC_SLV);
0024 DEFINE_QNODE(qxm_crypto, SM6350_MASTER_CRYPTO_CORE_0, 1, 8, SM6350_A2NOC_SNOC_SLV);
0025 DEFINE_QNODE(qxm_ipa, SM6350_MASTER_IPA, 1, 8, SM6350_A2NOC_SNOC_SLV);
0026 DEFINE_QNODE(xm_qdss_etr, SM6350_MASTER_QDSS_ETR, 1, 8, SM6350_A2NOC_SNOC_SLV);
0027 DEFINE_QNODE(xm_sdc2, SM6350_MASTER_SDCC_2, 1, 8, SM6350_A2NOC_SNOC_SLV);
0028 DEFINE_QNODE(xm_usb3_0, SM6350_MASTER_USB3, 1, 8, SM6350_A2NOC_SNOC_SLV);
0029 DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM6350_MASTER_CAMNOC_HF0_UNCOMP, 2, 32, SM6350_SLAVE_CAMNOC_UNCOMP);
0030 DEFINE_QNODE(qxm_camnoc_icp_uncomp, SM6350_MASTER_CAMNOC_ICP_UNCOMP, 1, 32, SM6350_SLAVE_CAMNOC_UNCOMP);
0031 DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM6350_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM6350_SLAVE_CAMNOC_UNCOMP);
0032 DEFINE_QNODE(qup0_core_master, SM6350_MASTER_QUP_CORE_0, 1, 4, SM6350_SLAVE_QUP_CORE_0);
0033 DEFINE_QNODE(qup1_core_master, SM6350_MASTER_QUP_CORE_1, 1, 4, SM6350_SLAVE_QUP_CORE_1);
0034 DEFINE_QNODE(qnm_npu, SM6350_MASTER_NPU, 2, 32, SM6350_SLAVE_CDSP_GEM_NOC);
0035 DEFINE_QNODE(qxm_npu_dsp, SM6350_MASTER_NPU_PROC, 1, 8, SM6350_SLAVE_CDSP_GEM_NOC);
0036 DEFINE_QNODE(qnm_snoc, SM6350_SNOC_CNOC_MAS, 1, 8, SM6350_SLAVE_CAMERA_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SLAVE_PIMEM_CFG, SM6350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CLK_CTL);
0037 DEFINE_QNODE(xm_qdss_dap, SM6350_MASTER_QDSS_DAP, 1, 8, SM6350_SLAVE_CAMERA_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SLAVE_PIMEM_CFG, SM6350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CLK_CTL);
0038 DEFINE_QNODE(qhm_cnoc_dc_noc, SM6350_MASTER_CNOC_DC_NOC, 1, 4, SM6350_SLAVE_LLCC_CFG, SM6350_SLAVE_GEM_NOC_CFG);
0039 DEFINE_QNODE(acm_apps, SM6350_MASTER_AMPSS_M0, 1, 16, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC);
0040 DEFINE_QNODE(acm_sys_tcu, SM6350_MASTER_SYS_TCU, 1, 8, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC);
0041 DEFINE_QNODE(qhm_gemnoc_cfg, SM6350_MASTER_GEM_NOC_CFG, 1, 4, SM6350_SLAVE_MCDMA_MS_MPU_CFG, SM6350_SLAVE_SERVICE_GEM_NOC, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG);
0042 DEFINE_QNODE(qnm_cmpnoc, SM6350_MASTER_COMPUTE_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC);
0043 DEFINE_QNODE(qnm_mnoc_hf, SM6350_MASTER_MNOC_HF_MEM_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC);
0044 DEFINE_QNODE(qnm_mnoc_sf, SM6350_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC);
0045 DEFINE_QNODE(qnm_snoc_gc, SM6350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM6350_SLAVE_LLCC);
0046 DEFINE_QNODE(qnm_snoc_sf, SM6350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM6350_SLAVE_LLCC);
0047 DEFINE_QNODE(qxm_gpu, SM6350_MASTER_GRAPHICS_3D, 2, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC);
0048 DEFINE_QNODE(llcc_mc, SM6350_MASTER_LLCC, 2, 4, SM6350_SLAVE_EBI_CH0);
0049 DEFINE_QNODE(qhm_mnoc_cfg, SM6350_MASTER_CNOC_MNOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_MNOC);
0050 DEFINE_QNODE(qnm_video0, SM6350_MASTER_VIDEO_P0, 1, 32, SM6350_SLAVE_MNOC_SF_MEM_NOC);
0051 DEFINE_QNODE(qnm_video_cvp, SM6350_MASTER_VIDEO_PROC, 1, 8, SM6350_SLAVE_MNOC_SF_MEM_NOC);
0052 DEFINE_QNODE(qxm_camnoc_hf, SM6350_MASTER_CAMNOC_HF, 2, 32, SM6350_SLAVE_MNOC_HF_MEM_NOC);
0053 DEFINE_QNODE(qxm_camnoc_icp, SM6350_MASTER_CAMNOC_ICP, 1, 8, SM6350_SLAVE_MNOC_SF_MEM_NOC);
0054 DEFINE_QNODE(qxm_camnoc_sf, SM6350_MASTER_CAMNOC_SF, 1, 32, SM6350_SLAVE_MNOC_SF_MEM_NOC);
0055 DEFINE_QNODE(qxm_mdp0, SM6350_MASTER_MDP_PORT0, 1, 32, SM6350_SLAVE_MNOC_HF_MEM_NOC);
0056 DEFINE_QNODE(amm_npu_sys, SM6350_MASTER_NPU_SYS, 2, 32, SM6350_SLAVE_NPU_COMPUTE_NOC);
0057 DEFINE_QNODE(qhm_npu_cfg, SM6350_MASTER_NPU_NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_NPU_NOC, SM6350_SLAVE_ISENSE_CFG, SM6350_SLAVE_NPU_LLM_CFG, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, SM6350_SLAVE_NPU_CP, SM6350_SLAVE_NPU_TCM, SM6350_SLAVE_NPU_CAL_DP0, SM6350_SLAVE_NPU_DPM);
0058 DEFINE_QNODE(qhm_snoc_cfg, SM6350_MASTER_SNOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_SNOC);
0059 DEFINE_QNODE(qnm_aggre1_noc, SM6350_A1NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SNOC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_QDSS_STM);
0060 DEFINE_QNODE(qnm_aggre2_noc, SM6350_A2NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SNOC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM);
0061 DEFINE_QNODE(qnm_gemnoc, SM6350_MASTER_GEM_NOC_SNOC, 1, 8, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM);
0062 DEFINE_QNODE(qxm_pimem, SM6350_MASTER_PIMEM, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC, SM6350_SLAVE_OCIMEM);
0063 DEFINE_QNODE(xm_gic, SM6350_MASTER_GIC, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC);
0064 DEFINE_QNODE(qns_a1noc_snoc, SM6350_A1NOC_SNOC_SLV, 1, 16, SM6350_A1NOC_SNOC_MAS);
0065 DEFINE_QNODE(srvc_aggre1_noc, SM6350_SLAVE_SERVICE_A1NOC, 1, 4);
0066 DEFINE_QNODE(qns_a2noc_snoc, SM6350_A2NOC_SNOC_SLV, 1, 16, SM6350_A2NOC_SNOC_MAS);
0067 DEFINE_QNODE(srvc_aggre2_noc, SM6350_SLAVE_SERVICE_A2NOC, 1, 4);
0068 DEFINE_QNODE(qns_camnoc_uncomp, SM6350_SLAVE_CAMNOC_UNCOMP, 1, 32);
0069 DEFINE_QNODE(qup0_core_slave, SM6350_SLAVE_QUP_CORE_0, 1, 4);
0070 DEFINE_QNODE(qup1_core_slave, SM6350_SLAVE_QUP_CORE_1, 1, 4);
0071 DEFINE_QNODE(qns_cdsp_gemnoc, SM6350_SLAVE_CDSP_GEM_NOC, 1, 32, SM6350_MASTER_COMPUTE_NOC);
0072 DEFINE_QNODE(qhs_a1_noc_cfg, SM6350_SLAVE_A1NOC_CFG, 1, 4, SM6350_MASTER_A1NOC_CFG);
0073 DEFINE_QNODE(qhs_a2_noc_cfg, SM6350_SLAVE_A2NOC_CFG, 1, 4, SM6350_MASTER_A2NOC_CFG);
0074 DEFINE_QNODE(qhs_ahb2phy0, SM6350_SLAVE_AHB2PHY, 1, 4);
0075 DEFINE_QNODE(qhs_ahb2phy2, SM6350_SLAVE_AHB2PHY_2, 1, 4);
0076 DEFINE_QNODE(qhs_aoss, SM6350_SLAVE_AOSS, 1, 4);
0077 DEFINE_QNODE(qhs_boot_rom, SM6350_SLAVE_BOOT_ROM, 1, 4);
0078 DEFINE_QNODE(qhs_camera_cfg, SM6350_SLAVE_CAMERA_CFG, 1, 4);
0079 DEFINE_QNODE(qhs_camera_nrt_thrott_cfg, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4);
0080 DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4);
0081 DEFINE_QNODE(qhs_clk_ctl, SM6350_SLAVE_CLK_CTL, 1, 4);
0082 DEFINE_QNODE(qhs_cpr_cx, SM6350_SLAVE_RBCPR_CX_CFG, 1, 4);
0083 DEFINE_QNODE(qhs_cpr_mx, SM6350_SLAVE_RBCPR_MX_CFG, 1, 4);
0084 DEFINE_QNODE(qhs_crypto0_cfg, SM6350_SLAVE_CRYPTO_0_CFG, 1, 4);
0085 DEFINE_QNODE(qhs_dcc_cfg, SM6350_SLAVE_DCC_CFG, 1, 4);
0086 DEFINE_QNODE(qhs_ddrss_cfg, SM6350_SLAVE_CNOC_DDRSS, 1, 4, SM6350_MASTER_CNOC_DC_NOC);
0087 DEFINE_QNODE(qhs_display_cfg, SM6350_SLAVE_DISPLAY_CFG, 1, 4);
0088 DEFINE_QNODE(qhs_display_throttle_cfg, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4);
0089 DEFINE_QNODE(qhs_emmc_cfg, SM6350_SLAVE_EMMC_CFG, 1, 4);
0090 DEFINE_QNODE(qhs_glm, SM6350_SLAVE_GLM, 1, 4);
0091 DEFINE_QNODE(qhs_gpuss_cfg, SM6350_SLAVE_GRAPHICS_3D_CFG, 1, 8);
0092 DEFINE_QNODE(qhs_imem_cfg, SM6350_SLAVE_IMEM_CFG, 1, 4);
0093 DEFINE_QNODE(qhs_ipa, SM6350_SLAVE_IPA_CFG, 1, 4);
0094 DEFINE_QNODE(qhs_mnoc_cfg, SM6350_SLAVE_CNOC_MNOC_CFG, 1, 4, SM6350_MASTER_CNOC_MNOC_CFG);
0095 DEFINE_QNODE(qhs_mss_cfg, SM6350_SLAVE_CNOC_MSS, 1, 4);
0096 DEFINE_QNODE(qhs_npu_cfg, SM6350_SLAVE_NPU_CFG, 1, 4, SM6350_MASTER_NPU_NOC_CFG);
0097 DEFINE_QNODE(qhs_pdm, SM6350_SLAVE_PDM, 1, 4);
0098 DEFINE_QNODE(qhs_pimem_cfg, SM6350_SLAVE_PIMEM_CFG, 1, 4);
0099 DEFINE_QNODE(qhs_prng, SM6350_SLAVE_PRNG, 1, 4);
0100 DEFINE_QNODE(qhs_qdss_cfg, SM6350_SLAVE_QDSS_CFG, 1, 4);
0101 DEFINE_QNODE(qhs_qm_cfg, SM6350_SLAVE_QM_CFG, 1, 4);
0102 DEFINE_QNODE(qhs_qm_mpu_cfg, SM6350_SLAVE_QM_MPU_CFG, 1, 4);
0103 DEFINE_QNODE(qhs_qup0, SM6350_SLAVE_QUP_0, 1, 4);
0104 DEFINE_QNODE(qhs_qup1, SM6350_SLAVE_QUP_1, 1, 4);
0105 DEFINE_QNODE(qhs_sdc2, SM6350_SLAVE_SDCC_2, 1, 4);
0106 DEFINE_QNODE(qhs_security, SM6350_SLAVE_SECURITY, 1, 4);
0107 DEFINE_QNODE(qhs_snoc_cfg, SM6350_SLAVE_SNOC_CFG, 1, 4, SM6350_MASTER_SNOC_CFG);
0108 DEFINE_QNODE(qhs_tcsr, SM6350_SLAVE_TCSR, 1, 4);
0109 DEFINE_QNODE(qhs_ufs_mem_cfg, SM6350_SLAVE_UFS_MEM_CFG, 1, 4);
0110 DEFINE_QNODE(qhs_usb3_0, SM6350_SLAVE_USB3, 1, 4);
0111 DEFINE_QNODE(qhs_venus_cfg, SM6350_SLAVE_VENUS_CFG, 1, 4);
0112 DEFINE_QNODE(qhs_venus_throttle_cfg, SM6350_SLAVE_VENUS_THROTTLE_CFG, 1, 4);
0113 DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM6350_SLAVE_VSENSE_CTRL_CFG, 1, 4);
0114 DEFINE_QNODE(srvc_cnoc, SM6350_SLAVE_SERVICE_CNOC, 1, 4);
0115 DEFINE_QNODE(qhs_gemnoc, SM6350_SLAVE_GEM_NOC_CFG, 1, 4, SM6350_MASTER_GEM_NOC_CFG);
0116 DEFINE_QNODE(qhs_llcc, SM6350_SLAVE_LLCC_CFG, 1, 4);
0117 DEFINE_QNODE(qhs_mcdma_ms_mpu_cfg, SM6350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4);
0118 DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
0119 DEFINE_QNODE(qns_gem_noc_snoc, SM6350_SLAVE_GEM_NOC_SNOC, 1, 8, SM6350_MASTER_GEM_NOC_SNOC);
0120 DEFINE_QNODE(qns_llcc, SM6350_SLAVE_LLCC, 1, 16, SM6350_MASTER_LLCC);
0121 DEFINE_QNODE(srvc_gemnoc, SM6350_SLAVE_SERVICE_GEM_NOC, 1, 4);
0122 DEFINE_QNODE(ebi, SM6350_SLAVE_EBI_CH0, 2, 4);
0123 DEFINE_QNODE(qns_mem_noc_hf, SM6350_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SM6350_MASTER_MNOC_HF_MEM_NOC);
0124 DEFINE_QNODE(qns_mem_noc_sf, SM6350_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM6350_MASTER_MNOC_SF_MEM_NOC);
0125 DEFINE_QNODE(srvc_mnoc, SM6350_SLAVE_SERVICE_MNOC, 1, 4);
0126 DEFINE_QNODE(qhs_cal_dp0, SM6350_SLAVE_NPU_CAL_DP0, 1, 4);
0127 DEFINE_QNODE(qhs_cp, SM6350_SLAVE_NPU_CP, 1, 4);
0128 DEFINE_QNODE(qhs_dma_bwmon, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
0129 DEFINE_QNODE(qhs_dpm, SM6350_SLAVE_NPU_DPM, 1, 4);
0130 DEFINE_QNODE(qhs_isense, SM6350_SLAVE_ISENSE_CFG, 1, 4);
0131 DEFINE_QNODE(qhs_llm, SM6350_SLAVE_NPU_LLM_CFG, 1, 4);
0132 DEFINE_QNODE(qhs_tcm, SM6350_SLAVE_NPU_TCM, 1, 4);
0133 DEFINE_QNODE(qns_npu_sys, SM6350_SLAVE_NPU_COMPUTE_NOC, 2, 32);
0134 DEFINE_QNODE(srvc_noc, SM6350_SLAVE_SERVICE_NPU_NOC, 1, 4);
0135 DEFINE_QNODE(qhs_apss, SM6350_SLAVE_APPSS, 1, 8);
0136 DEFINE_QNODE(qns_cnoc, SM6350_SNOC_CNOC_SLV, 1, 8, SM6350_SNOC_CNOC_MAS);
0137 DEFINE_QNODE(qns_gemnoc_gc, SM6350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM6350_MASTER_SNOC_GC_MEM_NOC);
0138 DEFINE_QNODE(qns_gemnoc_sf, SM6350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM6350_MASTER_SNOC_SF_MEM_NOC);
0139 DEFINE_QNODE(qxs_imem, SM6350_SLAVE_OCIMEM, 1, 8);
0140 DEFINE_QNODE(qxs_pimem, SM6350_SLAVE_PIMEM, 1, 8);
0141 DEFINE_QNODE(srvc_snoc, SM6350_SLAVE_SERVICE_SNOC, 1, 4);
0142 DEFINE_QNODE(xs_qdss_stm, SM6350_SLAVE_QDSS_STM, 1, 4);
0143 DEFINE_QNODE(xs_sys_tcu_cfg, SM6350_SLAVE_TCU, 1, 8);
0144
0145 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
0146 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
0147 DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_thrott_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc);
0148 DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_emmc, &xm_sdc2, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_sdc2);
0149 DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc);
0150 DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
0151 DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp);
0152 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
0153 DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
0154 DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_icp_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf, &qxm_mdp0);
0155 DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
0156 DEFINE_QBCM(bcm_mm3, "MM3", false, &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf);
0157 DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave);
0158 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
0159 DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
0160 DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
0161 DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps);
0162 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
0163 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
0164 DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
0165 DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
0166 DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
0167 DEFINE_QBCM(bcm_sn5, "SN5", false, &qnm_aggre1_noc);
0168 DEFINE_QBCM(bcm_sn6, "SN6", false, &qnm_aggre2_noc);
0169 DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_gemnoc);
0170
0171 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
0172 &bcm_cn1,
0173 };
0174
0175 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
0176 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
0177 [MASTER_QUP_0] = &qhm_qup_0,
0178 [MASTER_EMMC] = &xm_emmc,
0179 [MASTER_UFS_MEM] = &xm_ufs_mem,
0180 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
0181 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
0182 };
0183
0184 static const struct qcom_icc_desc sm6350_aggre1_noc = {
0185 .nodes = aggre1_noc_nodes,
0186 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
0187 .bcms = aggre1_noc_bcms,
0188 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
0189 };
0190
0191 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
0192 &bcm_ce0,
0193 &bcm_cn1,
0194 };
0195
0196 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
0197 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
0198 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
0199 [MASTER_QUP_1] = &qhm_qup_1,
0200 [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
0201 [MASTER_IPA] = &qxm_ipa,
0202 [MASTER_QDSS_ETR] = &xm_qdss_etr,
0203 [MASTER_SDCC_2] = &xm_sdc2,
0204 [MASTER_USB3] = &xm_usb3_0,
0205 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
0206 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
0207 };
0208
0209 static const struct qcom_icc_desc sm6350_aggre2_noc = {
0210 .nodes = aggre2_noc_nodes,
0211 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
0212 .bcms = aggre2_noc_bcms,
0213 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
0214 };
0215
0216 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
0217 &bcm_acv,
0218 &bcm_mc0,
0219 &bcm_mm1,
0220 &bcm_qup0,
0221 };
0222
0223 static struct qcom_icc_node * const clk_virt_nodes[] = {
0224 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
0225 [MASTER_CAMNOC_ICP_UNCOMP] = &qxm_camnoc_icp_uncomp,
0226 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
0227 [MASTER_QUP_CORE_0] = &qup0_core_master,
0228 [MASTER_QUP_CORE_1] = &qup1_core_master,
0229 [MASTER_LLCC] = &llcc_mc,
0230 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
0231 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
0232 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
0233 [SLAVE_EBI_CH0] = &ebi,
0234 };
0235
0236 static const struct qcom_icc_desc sm6350_clk_virt = {
0237 .nodes = clk_virt_nodes,
0238 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
0239 .bcms = clk_virt_bcms,
0240 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
0241 };
0242
0243 static struct qcom_icc_bcm * const compute_noc_bcms[] = {
0244 &bcm_co0,
0245 &bcm_co2,
0246 &bcm_co3,
0247 };
0248
0249 static struct qcom_icc_node * const compute_noc_nodes[] = {
0250 [MASTER_NPU] = &qnm_npu,
0251 [MASTER_NPU_PROC] = &qxm_npu_dsp,
0252 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
0253 };
0254
0255 static const struct qcom_icc_desc sm6350_compute_noc = {
0256 .nodes = compute_noc_nodes,
0257 .num_nodes = ARRAY_SIZE(compute_noc_nodes),
0258 .bcms = compute_noc_bcms,
0259 .num_bcms = ARRAY_SIZE(compute_noc_bcms),
0260 };
0261
0262 static struct qcom_icc_bcm * const config_noc_bcms[] = {
0263 &bcm_cn0,
0264 &bcm_cn1,
0265 };
0266
0267 static struct qcom_icc_node * const config_noc_nodes[] = {
0268 [SNOC_CNOC_MAS] = &qnm_snoc,
0269 [MASTER_QDSS_DAP] = &xm_qdss_dap,
0270 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
0271 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
0272 [SLAVE_AHB2PHY] = &qhs_ahb2phy0,
0273 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
0274 [SLAVE_AOSS] = &qhs_aoss,
0275 [SLAVE_BOOT_ROM] = &qhs_boot_rom,
0276 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
0277 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_thrott_cfg,
0278 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
0279 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
0280 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
0281 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
0282 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
0283 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
0284 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
0285 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
0286 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg,
0287 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
0288 [SLAVE_GLM] = &qhs_glm,
0289 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
0290 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
0291 [SLAVE_IPA_CFG] = &qhs_ipa,
0292 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
0293 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
0294 [SLAVE_NPU_CFG] = &qhs_npu_cfg,
0295 [SLAVE_PDM] = &qhs_pdm,
0296 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
0297 [SLAVE_PRNG] = &qhs_prng,
0298 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
0299 [SLAVE_QM_CFG] = &qhs_qm_cfg,
0300 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
0301 [SLAVE_QUP_0] = &qhs_qup0,
0302 [SLAVE_QUP_1] = &qhs_qup1,
0303 [SLAVE_SDCC_2] = &qhs_sdc2,
0304 [SLAVE_SECURITY] = &qhs_security,
0305 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
0306 [SLAVE_TCSR] = &qhs_tcsr,
0307 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
0308 [SLAVE_USB3] = &qhs_usb3_0,
0309 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
0310 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg,
0311 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
0312 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
0313 };
0314
0315 static const struct qcom_icc_desc sm6350_config_noc = {
0316 .nodes = config_noc_nodes,
0317 .num_nodes = ARRAY_SIZE(config_noc_nodes),
0318 .bcms = config_noc_bcms,
0319 .num_bcms = ARRAY_SIZE(config_noc_bcms),
0320 };
0321
0322 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
0323 };
0324
0325 static struct qcom_icc_node * const dc_noc_nodes[] = {
0326 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
0327 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
0328 [SLAVE_LLCC_CFG] = &qhs_llcc,
0329 };
0330
0331 static const struct qcom_icc_desc sm6350_dc_noc = {
0332 .nodes = dc_noc_nodes,
0333 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
0334 .bcms = dc_noc_bcms,
0335 .num_bcms = ARRAY_SIZE(dc_noc_bcms),
0336 };
0337
0338 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
0339 &bcm_sh0,
0340 &bcm_sh2,
0341 &bcm_sh3,
0342 &bcm_sh4,
0343 };
0344
0345 static struct qcom_icc_node * const gem_noc_nodes[] = {
0346 [MASTER_AMPSS_M0] = &acm_apps,
0347 [MASTER_SYS_TCU] = &acm_sys_tcu,
0348 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
0349 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
0350 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
0351 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
0352 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
0353 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
0354 [MASTER_GRAPHICS_3D] = &qxm_gpu,
0355 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_mcdma_ms_mpu_cfg,
0356 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
0357 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
0358 [SLAVE_LLCC] = &qns_llcc,
0359 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
0360 };
0361
0362 static const struct qcom_icc_desc sm6350_gem_noc = {
0363 .nodes = gem_noc_nodes,
0364 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
0365 .bcms = gem_noc_bcms,
0366 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
0367 };
0368
0369 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
0370 &bcm_mm0,
0371 &bcm_mm1,
0372 &bcm_mm2,
0373 &bcm_mm3,
0374 };
0375
0376 static struct qcom_icc_node * const mmss_noc_nodes[] = {
0377 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
0378 [MASTER_VIDEO_P0] = &qnm_video0,
0379 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
0380 [MASTER_CAMNOC_HF] = &qxm_camnoc_hf,
0381 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp,
0382 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
0383 [MASTER_MDP_PORT0] = &qxm_mdp0,
0384 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
0385 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
0386 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
0387 };
0388
0389 static const struct qcom_icc_desc sm6350_mmss_noc = {
0390 .nodes = mmss_noc_nodes,
0391 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
0392 .bcms = mmss_noc_bcms,
0393 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
0394 };
0395
0396 static struct qcom_icc_bcm * const npu_noc_bcms[] = {
0397 };
0398
0399 static struct qcom_icc_node * const npu_noc_nodes[] = {
0400 [MASTER_NPU_SYS] = &amm_npu_sys,
0401 [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg,
0402 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
0403 [SLAVE_NPU_CP] = &qhs_cp,
0404 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
0405 [SLAVE_NPU_DPM] = &qhs_dpm,
0406 [SLAVE_ISENSE_CFG] = &qhs_isense,
0407 [SLAVE_NPU_LLM_CFG] = &qhs_llm,
0408 [SLAVE_NPU_TCM] = &qhs_tcm,
0409 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
0410 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
0411 };
0412
0413 static const struct qcom_icc_desc sm6350_npu_noc = {
0414 .nodes = npu_noc_nodes,
0415 .num_nodes = ARRAY_SIZE(npu_noc_nodes),
0416 .bcms = npu_noc_bcms,
0417 .num_bcms = ARRAY_SIZE(npu_noc_bcms),
0418 };
0419
0420 static struct qcom_icc_bcm * const system_noc_bcms[] = {
0421 &bcm_sn0,
0422 &bcm_sn1,
0423 &bcm_sn10,
0424 &bcm_sn2,
0425 &bcm_sn3,
0426 &bcm_sn4,
0427 &bcm_sn5,
0428 &bcm_sn6,
0429 };
0430
0431 static struct qcom_icc_node * const system_noc_nodes[] = {
0432 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
0433 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
0434 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
0435 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
0436 [MASTER_PIMEM] = &qxm_pimem,
0437 [MASTER_GIC] = &xm_gic,
0438 [SLAVE_APPSS] = &qhs_apss,
0439 [SNOC_CNOC_SLV] = &qns_cnoc,
0440 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
0441 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
0442 [SLAVE_OCIMEM] = &qxs_imem,
0443 [SLAVE_PIMEM] = &qxs_pimem,
0444 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
0445 [SLAVE_QDSS_STM] = &xs_qdss_stm,
0446 [SLAVE_TCU] = &xs_sys_tcu_cfg,
0447 };
0448
0449 static const struct qcom_icc_desc sm6350_system_noc = {
0450 .nodes = system_noc_nodes,
0451 .num_nodes = ARRAY_SIZE(system_noc_nodes),
0452 .bcms = system_noc_bcms,
0453 .num_bcms = ARRAY_SIZE(system_noc_bcms),
0454 };
0455
0456 static const struct of_device_id qnoc_of_match[] = {
0457 { .compatible = "qcom,sm6350-aggre1-noc",
0458 .data = &sm6350_aggre1_noc},
0459 { .compatible = "qcom,sm6350-aggre2-noc",
0460 .data = &sm6350_aggre2_noc},
0461 { .compatible = "qcom,sm6350-clk-virt",
0462 .data = &sm6350_clk_virt},
0463 { .compatible = "qcom,sm6350-compute-noc",
0464 .data = &sm6350_compute_noc},
0465 { .compatible = "qcom,sm6350-config-noc",
0466 .data = &sm6350_config_noc},
0467 { .compatible = "qcom,sm6350-dc-noc",
0468 .data = &sm6350_dc_noc},
0469 { .compatible = "qcom,sm6350-gem-noc",
0470 .data = &sm6350_gem_noc},
0471 { .compatible = "qcom,sm6350-mmss-noc",
0472 .data = &sm6350_mmss_noc},
0473 { .compatible = "qcom,sm6350-npu-noc",
0474 .data = &sm6350_npu_noc},
0475 { .compatible = "qcom,sm6350-system-noc",
0476 .data = &sm6350_system_noc},
0477 { }
0478 };
0479 MODULE_DEVICE_TABLE(of, qnoc_of_match);
0480
0481 static struct platform_driver qnoc_driver = {
0482 .probe = qcom_icc_rpmh_probe,
0483 .remove = qcom_icc_rpmh_remove,
0484 .driver = {
0485 .name = "qnoc-sm6350",
0486 .of_match_table = qnoc_of_match,
0487 .sync_state = icc_sync_state,
0488 },
0489 };
0490 module_platform_driver(qnoc_driver);
0491
0492 MODULE_DESCRIPTION("Qualcomm SM6350 NoC driver");
0493 MODULE_LICENSE("GPL v2");
