interconnect/qcom/sdx65.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
0004  */
0005
0006 #include <linux/device.h>
0007 #include <linux/interconnect.h>
0008 #include <linux/interconnect-provider.h>
0009 #include <linux/module.h>
0010 #include <linux/of_platform.h>
0011 #include <dt-bindings/interconnect/qcom,sdx65.h>
0012
0013 #include "bcm-voter.h"
0014 #include "icc-rpmh.h"
0015 #include "sdx65.h"
0016
0017 DEFINE_QNODE(llcc_mc, SDX65_MASTER_LLCC, 1, 4, SDX65_SLAVE_EBI1);
0018 DEFINE_QNODE(acm_tcu, SDX65_MASTER_TCU_0, 1, 8, SDX65_SLAVE_LLCC, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC);
0019 DEFINE_QNODE(qnm_snoc_gc, SDX65_MASTER_SNOC_GC_MEM_NOC, 1, 16, SDX65_SLAVE_LLCC);
0020 DEFINE_QNODE(xm_apps_rdwr, SDX65_MASTER_APPSS_PROC, 1, 16, SDX65_SLAVE_LLCC, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC);
0021 DEFINE_QNODE(qhm_audio, SDX65_MASTER_AUDIO, 1, 4, SDX65_SLAVE_ANOC_SNOC);
0022 DEFINE_QNODE(qhm_blsp1, SDX65_MASTER_BLSP_1, 1, 4, SDX65_SLAVE_ANOC_SNOC);
0023 DEFINE_QNODE(qhm_qdss_bam, SDX65_MASTER_QDSS_BAM, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_TCU);
0024 DEFINE_QNODE(qhm_qpic, SDX65_MASTER_QPIC, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC);
0025 DEFINE_QNODE(qhm_snoc_cfg, SDX65_MASTER_SNOC_CFG, 1, 4, SDX65_SLAVE_SERVICE_SNOC);
0026 DEFINE_QNODE(qhm_spmi_fetcher1, SDX65_MASTER_SPMI_FETCHER, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_ANOC_SNOC);
0027 DEFINE_QNODE(qnm_aggre_noc, SDX65_MASTER_ANOC_SNOC, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU);
0028 DEFINE_QNODE(qnm_ipa, SDX65_MASTER_IPA, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM);
0029 DEFINE_QNODE(qnm_memnoc, SDX65_MASTER_MEM_NOC_SNOC, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_IMEM, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU);
0030 DEFINE_QNODE(qnm_memnoc_pcie, SDX65_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_SLAVE_PCIE_0);
0031 DEFINE_QNODE(qxm_crypto, SDX65_MASTER_CRYPTO, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_ANOC_SNOC);
0032 DEFINE_QNODE(xm_ipa2pcie_slv, SDX65_MASTER_IPA_PCIE, 1, 8, SDX65_SLAVE_PCIE_0);
0033 DEFINE_QNODE(xm_pcie, SDX65_MASTER_PCIE_0, 1, 8, SDX65_SLAVE_ANOC_SNOC);
0034 DEFINE_QNODE(xm_qdss_etr, SDX65_MASTER_QDSS_ETR, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_TCU);
0035 DEFINE_QNODE(xm_sdc1, SDX65_MASTER_SDCC_1, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC);
0036 DEFINE_QNODE(xm_usb3, SDX65_MASTER_USB3, 1, 8, SDX65_SLAVE_ANOC_SNOC);
0037 DEFINE_QNODE(ebi, SDX65_SLAVE_EBI1, 1, 4);
0038 DEFINE_QNODE(qns_llcc, SDX65_SLAVE_LLCC, 1, 16, SDX65_MASTER_LLCC);
0039 DEFINE_QNODE(qns_memnoc_snoc, SDX65_SLAVE_MEM_NOC_SNOC, 1, 8, SDX65_MASTER_MEM_NOC_SNOC);
0040 DEFINE_QNODE(qns_sys_pcie, SDX65_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_MASTER_MEM_NOC_PCIE_SNOC);
0041 DEFINE_QNODE(qhs_aoss, SDX65_SLAVE_AOSS, 1, 4);
0042 DEFINE_QNODE(qhs_apss, SDX65_SLAVE_APPSS, 1, 4);
0043 DEFINE_QNODE(qhs_audio, SDX65_SLAVE_AUDIO, 1, 4);
0044 DEFINE_QNODE(qhs_blsp1, SDX65_SLAVE_BLSP_1, 1, 4);
0045 DEFINE_QNODE(qhs_clk_ctl, SDX65_SLAVE_CLK_CTL, 1, 4);
0046 DEFINE_QNODE(qhs_crypto0_cfg, SDX65_SLAVE_CRYPTO_0_CFG, 1, 4);
0047 DEFINE_QNODE(qhs_ddrss_cfg, SDX65_SLAVE_CNOC_DDRSS, 1, 4);
0048 DEFINE_QNODE(qhs_ecc_cfg, SDX65_SLAVE_ECC_CFG, 1, 4);
0049 DEFINE_QNODE(qhs_imem_cfg, SDX65_SLAVE_IMEM_CFG, 1, 4);
0050 DEFINE_QNODE(qhs_ipa, SDX65_SLAVE_IPA_CFG, 1, 4);
0051 DEFINE_QNODE(qhs_mss_cfg, SDX65_SLAVE_CNOC_MSS, 1, 4);
0052 DEFINE_QNODE(qhs_pcie_parf, SDX65_SLAVE_PCIE_PARF, 1, 4);
0053 DEFINE_QNODE(qhs_pdm, SDX65_SLAVE_PDM, 1, 4);
0054 DEFINE_QNODE(qhs_prng, SDX65_SLAVE_PRNG, 1, 4);
0055 DEFINE_QNODE(qhs_qdss_cfg, SDX65_SLAVE_QDSS_CFG, 1, 4);
0056 DEFINE_QNODE(qhs_qpic, SDX65_SLAVE_QPIC, 1, 4);
0057 DEFINE_QNODE(qhs_sdc1, SDX65_SLAVE_SDCC_1, 1, 4);
0058 DEFINE_QNODE(qhs_snoc_cfg, SDX65_SLAVE_SNOC_CFG, 1, 4, SDX65_MASTER_SNOC_CFG);
0059 DEFINE_QNODE(qhs_spmi_fetcher, SDX65_SLAVE_SPMI_FETCHER, 1, 4);
0060 DEFINE_QNODE(qhs_spmi_vgi_coex, SDX65_SLAVE_SPMI_VGI_COEX, 1, 4);
0061 DEFINE_QNODE(qhs_tcsr, SDX65_SLAVE_TCSR, 1, 4);
0062 DEFINE_QNODE(qhs_tlmm, SDX65_SLAVE_TLMM, 1, 4);
0063 DEFINE_QNODE(qhs_usb3, SDX65_SLAVE_USB3, 1, 4);
0064 DEFINE_QNODE(qhs_usb3_phy, SDX65_SLAVE_USB3_PHY_CFG, 1, 4);
0065 DEFINE_QNODE(qns_aggre_noc, SDX65_SLAVE_ANOC_SNOC, 1, 8, SDX65_MASTER_ANOC_SNOC);
0066 DEFINE_QNODE(qns_snoc_memnoc, SDX65_SLAVE_SNOC_MEM_NOC_GC, 1, 16, SDX65_MASTER_SNOC_GC_MEM_NOC);
0067 DEFINE_QNODE(qxs_imem, SDX65_SLAVE_IMEM, 1, 8);
0068 DEFINE_QNODE(srvc_snoc, SDX65_SLAVE_SERVICE_SNOC, 1, 4);
0069 DEFINE_QNODE(xs_pcie, SDX65_SLAVE_PCIE_0, 1, 8);
0070 DEFINE_QNODE(xs_qdss_stm, SDX65_SLAVE_QDSS_STM, 1, 4);
0071 DEFINE_QNODE(xs_sys_tcu_cfg, SDX65_SLAVE_TCU, 1, 8);
0072
0073 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
0074 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
0075 DEFINE_QBCM(bcm_pn0, "PN0", true, &qhm_snoc_cfg, &qhs_aoss, &qhs_apss, &qhs_audio, &qhs_blsp1, &qhs_clk_ctl, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_ecc_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mss_cfg, &qhs_pcie_parf, &qhs_pdm, &qhs_prng, &qhs_qdss_cfg, &qhs_qpic, &qhs_sdc1, &qhs_snoc_cfg, &qhs_spmi_fetcher, &qhs_spmi_vgi_coex, &qhs_tcsr, &qhs_tlmm, &qhs_usb3, &qhs_usb3_phy, &srvc_snoc);
0076 DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1);
0077 DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1);
0078 DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic);
0079 DEFINE_QBCM(bcm_pn4, "PN4", false, &qxm_crypto);
0080 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
0081 DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_memnoc_snoc);
0082 DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr);
0083 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc);
0084 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
0085 DEFINE_QBCM(bcm_sn2, "SN2", false, &xs_qdss_stm);
0086 DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_sys_tcu_cfg);
0087 DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie);
0088 DEFINE_QBCM(bcm_sn6, "SN6", false, &qhm_qdss_bam, &xm_qdss_etr);
0089 DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc);
0090 DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_memnoc);
0091 DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc_pcie);
0092 DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_ipa, &xm_ipa2pcie_slv);
0093
0094 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
0095     &bcm_mc0,
0096 };
0097
0098 static struct qcom_icc_node * const mc_virt_nodes[] = {
0099     [MASTER_LLCC] = &llcc_mc,
0100     [SLAVE_EBI1] = &ebi,
0101 };
0102
0103 static const struct qcom_icc_desc sdx65_mc_virt = {
0104     .nodes = mc_virt_nodes,
0105     .num_nodes = ARRAY_SIZE(mc_virt_nodes),
0106     .bcms = mc_virt_bcms,
0107     .num_bcms = ARRAY_SIZE(mc_virt_bcms),
0108 };
0109
0110 static struct qcom_icc_bcm * const mem_noc_bcms[] = {
0111     &bcm_sh0,
0112     &bcm_sh1,
0113     &bcm_sh3,
0114 };
0115
0116 static struct qcom_icc_node * const mem_noc_nodes[] = {
0117     [MASTER_TCU_0] = &acm_tcu,
0118     [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
0119     [MASTER_APPSS_PROC] = &xm_apps_rdwr,
0120     [SLAVE_LLCC] = &qns_llcc,
0121     [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
0122     [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
0123 };
0124
0125 static const struct qcom_icc_desc sdx65_mem_noc = {
0126     .nodes = mem_noc_nodes,
0127     .num_nodes = ARRAY_SIZE(mem_noc_nodes),
0128     .bcms = mem_noc_bcms,
0129     .num_bcms = ARRAY_SIZE(mem_noc_bcms),
0130 };
0131
0132 static struct qcom_icc_bcm * const system_noc_bcms[] = {
0133     &bcm_ce0,
0134     &bcm_pn0,
0135     &bcm_pn1,
0136     &bcm_pn2,
0137     &bcm_pn3,
0138     &bcm_pn4,
0139     &bcm_sn0,
0140     &bcm_sn1,
0141     &bcm_sn2,
0142     &bcm_sn3,
0143     &bcm_sn5,
0144     &bcm_sn6,
0145     &bcm_sn7,
0146     &bcm_sn8,
0147     &bcm_sn9,
0148     &bcm_sn10,
0149 };
0150
0151 static struct qcom_icc_node * const system_noc_nodes[] = {
0152     [MASTER_AUDIO] = &qhm_audio,
0153     [MASTER_BLSP_1] = &qhm_blsp1,
0154     [MASTER_QDSS_BAM] = &qhm_qdss_bam,
0155     [MASTER_QPIC] = &qhm_qpic,
0156     [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
0157     [MASTER_SPMI_FETCHER] = &qhm_spmi_fetcher1,
0158     [MASTER_ANOC_SNOC] = &qnm_aggre_noc,
0159     [MASTER_IPA] = &qnm_ipa,
0160     [MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
0161     [MASTER_MEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie,
0162     [MASTER_CRYPTO] = &qxm_crypto,
0163     [MASTER_IPA_PCIE] = &xm_ipa2pcie_slv,
0164     [MASTER_PCIE_0] = &xm_pcie,
0165     [MASTER_QDSS_ETR] = &xm_qdss_etr,
0166     [MASTER_SDCC_1] = &xm_sdc1,
0167     [MASTER_USB3] = &xm_usb3,
0168     [SLAVE_AOSS] = &qhs_aoss,
0169     [SLAVE_APPSS] = &qhs_apss,
0170     [SLAVE_AUDIO] = &qhs_audio,
0171     [SLAVE_BLSP_1] = &qhs_blsp1,
0172     [SLAVE_CLK_CTL] = &qhs_clk_ctl,
0173     [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
0174     [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
0175     [SLAVE_ECC_CFG] = &qhs_ecc_cfg,
0176     [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
0177     [SLAVE_IPA_CFG] = &qhs_ipa,
0178     [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
0179     [SLAVE_PCIE_PARF] = &qhs_pcie_parf,
0180     [SLAVE_PDM] = &qhs_pdm,
0181     [SLAVE_PRNG] = &qhs_prng,
0182     [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
0183     [SLAVE_QPIC] = &qhs_qpic,
0184     [SLAVE_SDCC_1] = &qhs_sdc1,
0185     [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
0186     [SLAVE_SPMI_FETCHER] = &qhs_spmi_fetcher,
0187     [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex,
0188     [SLAVE_TCSR] = &qhs_tcsr,
0189     [SLAVE_TLMM] = &qhs_tlmm,
0190     [SLAVE_USB3] = &qhs_usb3,
0191     [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy,
0192     [SLAVE_ANOC_SNOC] = &qns_aggre_noc,
0193     [SLAVE_SNOC_MEM_NOC_GC] = &qns_snoc_memnoc,
0194     [SLAVE_IMEM] = &qxs_imem,
0195     [SLAVE_SERVICE_SNOC] = &srvc_snoc,
0196     [SLAVE_PCIE_0] = &xs_pcie,
0197     [SLAVE_QDSS_STM] = &xs_qdss_stm,
0198     [SLAVE_TCU] = &xs_sys_tcu_cfg,
0199 };
0200
0201 static const struct qcom_icc_desc sdx65_system_noc = {
0202     .nodes = system_noc_nodes,
0203     .num_nodes = ARRAY_SIZE(system_noc_nodes),
0204     .bcms = system_noc_bcms,
0205     .num_bcms = ARRAY_SIZE(system_noc_bcms),
0206 };
0207
0208 static const struct of_device_id qnoc_of_match[] = {
0209     { .compatible = "qcom,sdx65-mc-virt",
0210       .data = &sdx65_mc_virt},
0211     { .compatible = "qcom,sdx65-mem-noc",
0212       .data = &sdx65_mem_noc},
0213     { .compatible = "qcom,sdx65-system-noc",
0214       .data = &sdx65_system_noc},
0215     { }
0216 };
0217 MODULE_DEVICE_TABLE(of, qnoc_of_match);
0218
0219 static struct platform_driver qnoc_driver = {
0220     .probe = qcom_icc_rpmh_probe,
0221     .remove = qcom_icc_rpmh_remove,
0222     .driver = {
0223         .name = "qnoc-sdx65",
0224         .of_match_table = qnoc_of_match,
0225         .sync_state = icc_sync_state,
0226     },
0227 };
0228 module_platform_driver(qnoc_driver);
0229
0230 MODULE_DESCRIPTION("Qualcomm SDX65 NoC driver");
0231 MODULE_LICENSE("GPL v2");