interconnect/qcom/sdx55.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Qualcomm SDX55 interconnect driver
0004  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
0005  *
0006  * Copyright (c) 2021, Linaro Ltd.
0007  *
0008  */
0009
0010 #include <linux/device.h>
0011 #include <linux/interconnect.h>
0012 #include <linux/interconnect-provider.h>
0013 #include <linux/module.h>
0014 #include <linux/of_platform.h>
0015 #include <dt-bindings/interconnect/qcom,sdx55.h>
0016
0017 #include "bcm-voter.h"
0018 #include "icc-rpmh.h"
0019 #include "sdx55.h"
0020
0021 DEFINE_QNODE(llcc_mc, SDX55_MASTER_LLCC, 4, 4, SDX55_SLAVE_EBI_CH0);
0022 DEFINE_QNODE(acm_tcu, SDX55_MASTER_TCU_0, 1, 8, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC);
0023 DEFINE_QNODE(qnm_snoc_gc, SDX55_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDX55_SLAVE_LLCC);
0024 DEFINE_QNODE(xm_apps_rdwr, SDX55_MASTER_AMPSS_M0, 1, 16, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC);
0025 DEFINE_QNODE(qhm_audio, SDX55_MASTER_AUDIO, 1, 4, SDX55_SLAVE_ANOC_SNOC);
0026 DEFINE_QNODE(qhm_blsp1, SDX55_MASTER_BLSP_1, 1, 4, SDX55_SLAVE_ANOC_SNOC);
0027 DEFINE_QNODE(qhm_qdss_bam, SDX55_MASTER_QDSS_BAM, 1, 4, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
0028 DEFINE_QNODE(qhm_qpic, SDX55_MASTER_QPIC, 1, 4, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO);
0029 DEFINE_QNODE(qhm_snoc_cfg, SDX55_MASTER_SNOC_CFG, 1, 4, SDX55_SLAVE_SERVICE_SNOC);
0030 DEFINE_QNODE(qhm_spmi_fetcher1, SDX55_MASTER_SPMI_FETCHER, 1, 4, SDX55_SLAVE_AOSS, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP);
0031 DEFINE_QNODE(qnm_aggre_noc, SDX55_MASTER_ANOC_SNOC, 1, 8, SDX55_SLAVE_PCIE_0, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_USB3, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_APPSS, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
0032 DEFINE_QNODE(qnm_ipa, SDX55_MASTER_IPA, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_TLMM, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
0033 DEFINE_QNODE(qnm_memnoc, SDX55_MASTER_MEM_NOC_SNOC, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_APPSS,  SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
0034 DEFINE_QNODE(qnm_memnoc_pcie, SDX55_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX55_SLAVE_PCIE_0);
0035 DEFINE_QNODE(qxm_crypto, SDX55_MASTER_CRYPTO_CORE_0, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP);
0036 DEFINE_QNODE(xm_emac, SDX55_MASTER_EMAC, 1, 8, SDX55_SLAVE_ANOC_SNOC);
0037 DEFINE_QNODE(xm_ipa2pcie_slv, SDX55_MASTER_IPA_PCIE, 1, 8, SDX55_SLAVE_PCIE_0);
0038 DEFINE_QNODE(xm_pcie, SDX55_MASTER_PCIE, 1, 8, SDX55_SLAVE_ANOC_SNOC);
0039 DEFINE_QNODE(xm_qdss_etr, SDX55_MASTER_QDSS_ETR, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
0040 DEFINE_QNODE(xm_sdc1, SDX55_MASTER_SDCC_1, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO);
0041 DEFINE_QNODE(xm_usb3, SDX55_MASTER_USB3, 1, 8, SDX55_SLAVE_ANOC_SNOC);
0042 DEFINE_QNODE(ebi, SDX55_SLAVE_EBI_CH0, 1, 4);
0043 DEFINE_QNODE(qns_llcc, SDX55_SLAVE_LLCC, 1, 16, SDX55_SLAVE_EBI_CH0);
0044 DEFINE_QNODE(qns_memnoc_snoc, SDX55_SLAVE_MEM_NOC_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_SNOC);
0045 DEFINE_QNODE(qns_sys_pcie, SDX55_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_PCIE_SNOC);
0046 DEFINE_QNODE(qhs_aop, SDX55_SLAVE_AOP, 1, 4);
0047 DEFINE_QNODE(qhs_aoss, SDX55_SLAVE_AOSS, 1, 4);
0048 DEFINE_QNODE(qhs_apss, SDX55_SLAVE_APPSS, 1, 4);
0049 DEFINE_QNODE(qhs_audio, SDX55_SLAVE_AUDIO, 1, 4);
0050 DEFINE_QNODE(qhs_blsp1, SDX55_SLAVE_BLSP_1, 1, 4);
0051 DEFINE_QNODE(qhs_clk_ctl, SDX55_SLAVE_CLK_CTL, 1, 4);
0052 DEFINE_QNODE(qhs_crypto0_cfg, SDX55_SLAVE_CRYPTO_0_CFG, 1, 4);
0053 DEFINE_QNODE(qhs_ddrss_cfg, SDX55_SLAVE_CNOC_DDRSS, 1, 4);
0054 DEFINE_QNODE(qhs_ecc_cfg, SDX55_SLAVE_ECC_CFG, 1, 4);
0055 DEFINE_QNODE(qhs_emac_cfg, SDX55_SLAVE_EMAC_CFG, 1, 4);
0056 DEFINE_QNODE(qhs_imem_cfg, SDX55_SLAVE_IMEM_CFG, 1, 4);
0057 DEFINE_QNODE(qhs_ipa, SDX55_SLAVE_IPA_CFG, 1, 4);
0058 DEFINE_QNODE(qhs_mss_cfg, SDX55_SLAVE_CNOC_MSS, 1, 4);
0059 DEFINE_QNODE(qhs_pcie_parf, SDX55_SLAVE_PCIE_PARF, 1, 4);
0060 DEFINE_QNODE(qhs_pdm, SDX55_SLAVE_PDM, 1, 4);
0061 DEFINE_QNODE(qhs_prng, SDX55_SLAVE_PRNG, 1, 4);
0062 DEFINE_QNODE(qhs_qdss_cfg, SDX55_SLAVE_QDSS_CFG, 1, 4);
0063 DEFINE_QNODE(qhs_qpic, SDX55_SLAVE_QPIC, 1, 4);
0064 DEFINE_QNODE(qhs_sdc1, SDX55_SLAVE_SDCC_1, 1, 4);
0065 DEFINE_QNODE(qhs_snoc_cfg, SDX55_SLAVE_SNOC_CFG, 1, 4, SDX55_MASTER_SNOC_CFG);
0066 DEFINE_QNODE(qhs_spmi_fetcher, SDX55_SLAVE_SPMI_FETCHER, 1, 4);
0067 DEFINE_QNODE(qhs_spmi_vgi_coex, SDX55_SLAVE_SPMI_VGI_COEX, 1, 4);
0068 DEFINE_QNODE(qhs_tcsr, SDX55_SLAVE_TCSR, 1, 4);
0069 DEFINE_QNODE(qhs_tlmm, SDX55_SLAVE_TLMM, 1, 4);
0070 DEFINE_QNODE(qhs_usb3, SDX55_SLAVE_USB3, 1, 4);
0071 DEFINE_QNODE(qhs_usb3_phy, SDX55_SLAVE_USB3_PHY_CFG, 1, 4);
0072 DEFINE_QNODE(qns_aggre_noc, SDX55_SLAVE_ANOC_SNOC, 1, 8, SDX55_MASTER_ANOC_SNOC);
0073 DEFINE_QNODE(qns_snoc_memnoc, SDX55_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDX55_MASTER_SNOC_GC_MEM_NOC);
0074 DEFINE_QNODE(qxs_imem, SDX55_SLAVE_OCIMEM, 1, 8);
0075 DEFINE_QNODE(srvc_snoc, SDX55_SLAVE_SERVICE_SNOC, 1, 4);
0076 DEFINE_QNODE(xs_pcie, SDX55_SLAVE_PCIE_0, 1, 8);
0077 DEFINE_QNODE(xs_qdss_stm, SDX55_SLAVE_QDSS_STM, 1, 4);
0078 DEFINE_QNODE(xs_sys_tcu_cfg, SDX55_SLAVE_TCU, 1, 8);
0079
0080 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
0081 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
0082 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
0083 DEFINE_QBCM(bcm_pn0, "PN0", false, &qhm_snoc_cfg);
0084 DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr);
0085 DEFINE_QBCM(bcm_sh4, "SH4", false, &qns_memnoc_snoc, &qns_sys_pcie);
0086 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc);
0087 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
0088 DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1);
0089 DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1);
0090 DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_qdss_stm);
0091 DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic);
0092 DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_sys_tcu_cfg);
0093 DEFINE_QBCM(bcm_pn5, "PN5", false, &qxm_crypto);
0094 DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie);
0095 DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3,
0096         &qns_aggre_noc);
0097 DEFINE_QBCM(bcm_sn8, "SN8", false, &qhm_qdss_bam, &xm_qdss_etr);
0098 DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc);
0099 DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_memnoc_pcie);
0100 DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_ipa, &xm_ipa2pcie_slv);
0101
0102 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
0103     &bcm_mc0,
0104 };
0105
0106 static struct qcom_icc_node * const mc_virt_nodes[] = {
0107     [MASTER_LLCC] = &llcc_mc,
0108     [SLAVE_EBI_CH0] = &ebi,
0109 };
0110
0111 static const struct qcom_icc_desc sdx55_mc_virt = {
0112     .nodes = mc_virt_nodes,
0113     .num_nodes = ARRAY_SIZE(mc_virt_nodes),
0114     .bcms = mc_virt_bcms,
0115     .num_bcms = ARRAY_SIZE(mc_virt_bcms),
0116 };
0117
0118 static struct qcom_icc_bcm * const mem_noc_bcms[] = {
0119     &bcm_sh0,
0120     &bcm_sh3,
0121     &bcm_sh4,
0122 };
0123
0124 static struct qcom_icc_node * const mem_noc_nodes[] = {
0125     [MASTER_TCU_0] = &acm_tcu,
0126     [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
0127     [MASTER_AMPSS_M0] = &xm_apps_rdwr,
0128     [SLAVE_LLCC] = &qns_llcc,
0129     [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
0130     [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
0131 };
0132
0133 static const struct qcom_icc_desc sdx55_mem_noc = {
0134     .nodes = mem_noc_nodes,
0135     .num_nodes = ARRAY_SIZE(mem_noc_nodes),
0136     .bcms = mem_noc_bcms,
0137     .num_bcms = ARRAY_SIZE(mem_noc_bcms),
0138 };
0139
0140 static struct qcom_icc_bcm * const system_noc_bcms[] = {
0141     &bcm_ce0,
0142     &bcm_pn0,
0143     &bcm_pn1,
0144     &bcm_pn2,
0145     &bcm_pn3,
0146     &bcm_pn5,
0147     &bcm_sn0,
0148     &bcm_sn1,
0149     &bcm_sn3,
0150     &bcm_sn4,
0151     &bcm_sn6,
0152     &bcm_sn7,
0153     &bcm_sn8,
0154     &bcm_sn9,
0155     &bcm_sn10,
0156     &bcm_sn11,
0157 };
0158
0159 static struct qcom_icc_node * const system_noc_nodes[] = {
0160     [MASTER_AUDIO] = &qhm_audio,
0161     [MASTER_BLSP_1] = &qhm_blsp1,
0162     [MASTER_QDSS_BAM] = &qhm_qdss_bam,
0163     [MASTER_QPIC] = &qhm_qpic,
0164     [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
0165     [MASTER_SPMI_FETCHER] = &qhm_spmi_fetcher1,
0166     [MASTER_ANOC_SNOC] = &qnm_aggre_noc,
0167     [MASTER_IPA] = &qnm_ipa,
0168     [MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
0169     [MASTER_MEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie,
0170     [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
0171     [MASTER_EMAC] = &xm_emac,
0172     [MASTER_IPA_PCIE] = &xm_ipa2pcie_slv,
0173     [MASTER_PCIE] = &xm_pcie,
0174     [MASTER_QDSS_ETR] = &xm_qdss_etr,
0175     [MASTER_SDCC_1] = &xm_sdc1,
0176     [MASTER_USB3] = &xm_usb3,
0177     [SLAVE_AOP] = &qhs_aop,
0178     [SLAVE_AOSS] = &qhs_aoss,
0179     [SLAVE_APPSS] = &qhs_apss,
0180     [SLAVE_AUDIO] = &qhs_audio,
0181     [SLAVE_BLSP_1] = &qhs_blsp1,
0182     [SLAVE_CLK_CTL] = &qhs_clk_ctl,
0183     [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
0184     [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
0185     [SLAVE_ECC_CFG] = &qhs_ecc_cfg,
0186     [SLAVE_EMAC_CFG] = &qhs_emac_cfg,
0187     [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
0188     [SLAVE_IPA_CFG] = &qhs_ipa,
0189     [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
0190     [SLAVE_PCIE_PARF] = &qhs_pcie_parf,
0191     [SLAVE_PDM] = &qhs_pdm,
0192     [SLAVE_PRNG] = &qhs_prng,
0193     [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
0194     [SLAVE_QPIC] = &qhs_qpic,
0195     [SLAVE_SDCC_1] = &qhs_sdc1,
0196     [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
0197     [SLAVE_SPMI_FETCHER] = &qhs_spmi_fetcher,
0198     [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex,
0199     [SLAVE_TCSR] = &qhs_tcsr,
0200     [SLAVE_TLMM] = &qhs_tlmm,
0201     [SLAVE_USB3] = &qhs_usb3,
0202     [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy,
0203     [SLAVE_ANOC_SNOC] = &qns_aggre_noc,
0204     [SLAVE_SNOC_MEM_NOC_GC] = &qns_snoc_memnoc,
0205     [SLAVE_OCIMEM] = &qxs_imem,
0206     [SLAVE_SERVICE_SNOC] = &srvc_snoc,
0207     [SLAVE_PCIE_0] = &xs_pcie,
0208     [SLAVE_QDSS_STM] = &xs_qdss_stm,
0209     [SLAVE_TCU] = &xs_sys_tcu_cfg,
0210 };
0211
0212 static const struct qcom_icc_desc sdx55_system_noc = {
0213     .nodes = system_noc_nodes,
0214     .num_nodes = ARRAY_SIZE(system_noc_nodes),
0215     .bcms = system_noc_bcms,
0216     .num_bcms = ARRAY_SIZE(system_noc_bcms),
0217 };
0218
0219 static const struct of_device_id qnoc_of_match[] = {
0220     { .compatible = "qcom,sdx55-mc-virt",
0221       .data = &sdx55_mc_virt},
0222     { .compatible = "qcom,sdx55-mem-noc",
0223       .data = &sdx55_mem_noc},
0224     { .compatible = "qcom,sdx55-system-noc",
0225       .data = &sdx55_system_noc},
0226     { }
0227 };
0228 MODULE_DEVICE_TABLE(of, qnoc_of_match);
0229
0230 static struct platform_driver qnoc_driver = {
0231     .probe = qcom_icc_rpmh_probe,
0232     .remove = qcom_icc_rpmh_remove,
0233     .driver = {
0234         .name = "qnoc-sdx55",
0235         .of_match_table = qnoc_of_match,
0236         .sync_state = icc_sync_state,
0237     },
0238 };
0239 module_platform_driver(qnoc_driver);
0240
0241 MODULE_DESCRIPTION("Qualcomm SDX55 NoC driver");
0242 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
0243 MODULE_LICENSE("GPL v2");