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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #include <linux/device.h>
0007 #include <linux/interconnect.h>
0008 #include <linux/interconnect-provider.h>
0009 #include <linux/module.h>
0010 #include <linux/of_device.h>
0011 
0012 #include <dt-bindings/interconnect/qcom,sdm845.h>
0013 
0014 #include "bcm-voter.h"
0015 #include "icc-rpmh.h"
0016 #include "sdm845.h"
0017 
0018 DEFINE_QNODE(qhm_a1noc_cfg, SDM845_MASTER_A1NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A1NOC);
0019 DEFINE_QNODE(qhm_qup1, SDM845_MASTER_BLSP_1, 1, 4, SDM845_SLAVE_A1NOC_SNOC);
0020 DEFINE_QNODE(qhm_tsif, SDM845_MASTER_TSIF, 1, 4, SDM845_SLAVE_A1NOC_SNOC);
0021 DEFINE_QNODE(xm_sdc2, SDM845_MASTER_SDCC_2, 1, 8, SDM845_SLAVE_A1NOC_SNOC);
0022 DEFINE_QNODE(xm_sdc4, SDM845_MASTER_SDCC_4, 1, 8, SDM845_SLAVE_A1NOC_SNOC);
0023 DEFINE_QNODE(xm_ufs_card, SDM845_MASTER_UFS_CARD, 1, 8, SDM845_SLAVE_A1NOC_SNOC);
0024 DEFINE_QNODE(xm_ufs_mem, SDM845_MASTER_UFS_MEM, 1, 8, SDM845_SLAVE_A1NOC_SNOC);
0025 DEFINE_QNODE(xm_pcie_0, SDM845_MASTER_PCIE_0, 1, 8, SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC);
0026 DEFINE_QNODE(qhm_a2noc_cfg, SDM845_MASTER_A2NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A2NOC);
0027 DEFINE_QNODE(qhm_qdss_bam, SDM845_MASTER_QDSS_BAM, 1, 4, SDM845_SLAVE_A2NOC_SNOC);
0028 DEFINE_QNODE(qhm_qup2, SDM845_MASTER_BLSP_2, 1, 4, SDM845_SLAVE_A2NOC_SNOC);
0029 DEFINE_QNODE(qnm_cnoc, SDM845_MASTER_CNOC_A2NOC, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
0030 DEFINE_QNODE(qxm_crypto, SDM845_MASTER_CRYPTO, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
0031 DEFINE_QNODE(qxm_ipa, SDM845_MASTER_IPA, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
0032 DEFINE_QNODE(xm_pcie3_1, SDM845_MASTER_PCIE_1, 1, 8, SDM845_SLAVE_ANOC_PCIE_SNOC);
0033 DEFINE_QNODE(xm_qdss_etr, SDM845_MASTER_QDSS_ETR, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
0034 DEFINE_QNODE(xm_usb3_0, SDM845_MASTER_USB3_0, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
0035 DEFINE_QNODE(xm_usb3_1, SDM845_MASTER_USB3_1, 1, 8, SDM845_SLAVE_A2NOC_SNOC);
0036 DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM845_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP);
0037 DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM845_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP);
0038 DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM845_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP);
0039 DEFINE_QNODE(qhm_spdm, SDM845_MASTER_SPDM, 1, 4, SDM845_SLAVE_CNOC_A2NOC);
0040 DEFINE_QNODE(qhm_tic, SDM845_MASTER_TIC, 1, 4, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_CNOC_A2NOC, SDM845_SLAVE_SERVICE_CNOC);
0041 DEFINE_QNODE(qnm_snoc, SDM845_MASTER_SNOC_CNOC, 1, 8, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_SERVICE_CNOC);
0042 DEFINE_QNODE(xm_qdss_dap, SDM845_MASTER_QDSS_DAP, 1, 8, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_CNOC_A2NOC, SDM845_SLAVE_SERVICE_CNOC);
0043 DEFINE_QNODE(qhm_cnoc, SDM845_MASTER_CNOC_DC_NOC, 1, 4, SDM845_SLAVE_LLCC_CFG, SDM845_SLAVE_MEM_NOC_CFG);
0044 DEFINE_QNODE(acm_l3, SDM845_MASTER_APPSS_PROC, 1, 16, SDM845_SLAVE_GNOC_SNOC, SDM845_SLAVE_GNOC_MEM_NOC, SDM845_SLAVE_SERVICE_GNOC);
0045 DEFINE_QNODE(pm_gnoc_cfg, SDM845_MASTER_GNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_GNOC);
0046 DEFINE_QNODE(llcc_mc, SDM845_MASTER_LLCC, 4, 4, SDM845_SLAVE_EBI1);
0047 DEFINE_QNODE(acm_tcu, SDM845_MASTER_TCU_0, 1, 8, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC);
0048 DEFINE_QNODE(qhm_memnoc_cfg, SDM845_MASTER_MEM_NOC_CFG, 1, 4, SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, SDM845_SLAVE_SERVICE_MEM_NOC);
0049 DEFINE_QNODE(qnm_apps, SDM845_MASTER_GNOC_MEM_NOC, 2, 32, SDM845_SLAVE_LLCC);
0050 DEFINE_QNODE(qnm_mnoc_hf, SDM845_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC);
0051 DEFINE_QNODE(qnm_mnoc_sf, SDM845_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC);
0052 DEFINE_QNODE(qnm_snoc_gc, SDM845_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM845_SLAVE_LLCC);
0053 DEFINE_QNODE(qnm_snoc_sf, SDM845_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC);
0054 DEFINE_QNODE(qxm_gpu, SDM845_MASTER_GFX3D, 2, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC);
0055 DEFINE_QNODE(qhm_mnoc_cfg, SDM845_MASTER_CNOC_MNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_MNOC);
0056 DEFINE_QNODE(qxm_camnoc_hf0, SDM845_MASTER_CAMNOC_HF0, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC);
0057 DEFINE_QNODE(qxm_camnoc_hf1, SDM845_MASTER_CAMNOC_HF1, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC);
0058 DEFINE_QNODE(qxm_camnoc_sf, SDM845_MASTER_CAMNOC_SF, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC);
0059 DEFINE_QNODE(qxm_mdp0, SDM845_MASTER_MDP0, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC);
0060 DEFINE_QNODE(qxm_mdp1, SDM845_MASTER_MDP1, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC);
0061 DEFINE_QNODE(qxm_rot, SDM845_MASTER_ROTATOR, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC);
0062 DEFINE_QNODE(qxm_venus0, SDM845_MASTER_VIDEO_P0, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC);
0063 DEFINE_QNODE(qxm_venus1, SDM845_MASTER_VIDEO_P1, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC);
0064 DEFINE_QNODE(qxm_venus_arm9, SDM845_MASTER_VIDEO_PROC, 1, 8, SDM845_SLAVE_MNOC_SF_MEM_NOC);
0065 DEFINE_QNODE(qhm_snoc_cfg, SDM845_MASTER_SNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_SNOC);
0066 DEFINE_QNODE(qnm_aggre1_noc, SDM845_MASTER_A1NOC_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM);
0067 DEFINE_QNODE(qnm_aggre2_noc, SDM845_MASTER_A2NOC_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_PCIE_0, SDM845_SLAVE_PCIE_1, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM, SDM845_SLAVE_TCU);
0068 DEFINE_QNODE(qnm_gladiator_sodv, SDM845_MASTER_GNOC_SNOC, 1, 8, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_IMEM, SDM845_SLAVE_PCIE_0, SDM845_SLAVE_PCIE_1, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM, SDM845_SLAVE_TCU);
0069 DEFINE_QNODE(qnm_memnoc, SDM845_MASTER_MEM_NOC_SNOC, 1, 8, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_IMEM, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM);
0070 DEFINE_QNODE(qnm_pcie_anoc, SDM845_MASTER_ANOC_PCIE_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_QDSS_STM);
0071 DEFINE_QNODE(qxm_pimem, SDM845_MASTER_PIMEM, 1, 8, SDM845_SLAVE_SNOC_MEM_NOC_GC, SDM845_SLAVE_IMEM);
0072 DEFINE_QNODE(xm_gic, SDM845_MASTER_GIC, 1, 8, SDM845_SLAVE_SNOC_MEM_NOC_GC, SDM845_SLAVE_IMEM);
0073 DEFINE_QNODE(qns_a1noc_snoc, SDM845_SLAVE_A1NOC_SNOC, 1, 16, SDM845_MASTER_A1NOC_SNOC);
0074 DEFINE_QNODE(srvc_aggre1_noc, SDM845_SLAVE_SERVICE_A1NOC, 1, 4, 0);
0075 DEFINE_QNODE(qns_pcie_a1noc_snoc, SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, 1, 16, SDM845_MASTER_ANOC_PCIE_SNOC);
0076 DEFINE_QNODE(qns_a2noc_snoc, SDM845_SLAVE_A2NOC_SNOC, 1, 16, SDM845_MASTER_A2NOC_SNOC);
0077 DEFINE_QNODE(qns_pcie_snoc, SDM845_SLAVE_ANOC_PCIE_SNOC, 1, 16, SDM845_MASTER_ANOC_PCIE_SNOC);
0078 DEFINE_QNODE(srvc_aggre2_noc, SDM845_SLAVE_SERVICE_A2NOC, 1, 4);
0079 DEFINE_QNODE(qns_camnoc_uncomp, SDM845_SLAVE_CAMNOC_UNCOMP, 1, 32);
0080 DEFINE_QNODE(qhs_a1_noc_cfg, SDM845_SLAVE_A1NOC_CFG, 1, 4, SDM845_MASTER_A1NOC_CFG);
0081 DEFINE_QNODE(qhs_a2_noc_cfg, SDM845_SLAVE_A2NOC_CFG, 1, 4, SDM845_MASTER_A2NOC_CFG);
0082 DEFINE_QNODE(qhs_aop, SDM845_SLAVE_AOP, 1, 4);
0083 DEFINE_QNODE(qhs_aoss, SDM845_SLAVE_AOSS, 1, 4);
0084 DEFINE_QNODE(qhs_camera_cfg, SDM845_SLAVE_CAMERA_CFG, 1, 4);
0085 DEFINE_QNODE(qhs_clk_ctl, SDM845_SLAVE_CLK_CTL, 1, 4);
0086 DEFINE_QNODE(qhs_compute_dsp_cfg, SDM845_SLAVE_CDSP_CFG, 1, 4);
0087 DEFINE_QNODE(qhs_cpr_cx, SDM845_SLAVE_RBCPR_CX_CFG, 1, 4);
0088 DEFINE_QNODE(qhs_crypto0_cfg, SDM845_SLAVE_CRYPTO_0_CFG, 1, 4);
0089 DEFINE_QNODE(qhs_dcc_cfg, SDM845_SLAVE_DCC_CFG, 1, 4, SDM845_MASTER_CNOC_DC_NOC);
0090 DEFINE_QNODE(qhs_ddrss_cfg, SDM845_SLAVE_CNOC_DDRSS, 1, 4);
0091 DEFINE_QNODE(qhs_display_cfg, SDM845_SLAVE_DISPLAY_CFG, 1, 4);
0092 DEFINE_QNODE(qhs_glm, SDM845_SLAVE_GLM, 1, 4);
0093 DEFINE_QNODE(qhs_gpuss_cfg, SDM845_SLAVE_GFX3D_CFG, 1, 8);
0094 DEFINE_QNODE(qhs_imem_cfg, SDM845_SLAVE_IMEM_CFG, 1, 4);
0095 DEFINE_QNODE(qhs_ipa, SDM845_SLAVE_IPA_CFG, 1, 4);
0096 DEFINE_QNODE(qhs_mnoc_cfg, SDM845_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM845_MASTER_CNOC_MNOC_CFG);
0097 DEFINE_QNODE(qhs_pcie0_cfg, SDM845_SLAVE_PCIE_0_CFG, 1, 4);
0098 DEFINE_QNODE(qhs_pcie_gen3_cfg, SDM845_SLAVE_PCIE_1_CFG, 1, 4);
0099 DEFINE_QNODE(qhs_pdm, SDM845_SLAVE_PDM, 1, 4);
0100 DEFINE_QNODE(qhs_phy_refgen_south, SDM845_SLAVE_SOUTH_PHY_CFG, 1, 4);
0101 DEFINE_QNODE(qhs_pimem_cfg, SDM845_SLAVE_PIMEM_CFG, 1, 4);
0102 DEFINE_QNODE(qhs_prng, SDM845_SLAVE_PRNG, 1, 4);
0103 DEFINE_QNODE(qhs_qdss_cfg, SDM845_SLAVE_QDSS_CFG, 1, 4);
0104 DEFINE_QNODE(qhs_qupv3_north, SDM845_SLAVE_BLSP_2, 1, 4);
0105 DEFINE_QNODE(qhs_qupv3_south, SDM845_SLAVE_BLSP_1, 1, 4);
0106 DEFINE_QNODE(qhs_sdc2, SDM845_SLAVE_SDCC_2, 1, 4);
0107 DEFINE_QNODE(qhs_sdc4, SDM845_SLAVE_SDCC_4, 1, 4);
0108 DEFINE_QNODE(qhs_snoc_cfg, SDM845_SLAVE_SNOC_CFG, 1, 4, SDM845_MASTER_SNOC_CFG);
0109 DEFINE_QNODE(qhs_spdm, SDM845_SLAVE_SPDM_WRAPPER, 1, 4);
0110 DEFINE_QNODE(qhs_spss_cfg, SDM845_SLAVE_SPSS_CFG, 1, 4);
0111 DEFINE_QNODE(qhs_tcsr, SDM845_SLAVE_TCSR, 1, 4);
0112 DEFINE_QNODE(qhs_tlmm_north, SDM845_SLAVE_TLMM_NORTH, 1, 4);
0113 DEFINE_QNODE(qhs_tlmm_south, SDM845_SLAVE_TLMM_SOUTH, 1, 4);
0114 DEFINE_QNODE(qhs_tsif, SDM845_SLAVE_TSIF, 1, 4);
0115 DEFINE_QNODE(qhs_ufs_card_cfg, SDM845_SLAVE_UFS_CARD_CFG, 1, 4);
0116 DEFINE_QNODE(qhs_ufs_mem_cfg, SDM845_SLAVE_UFS_MEM_CFG, 1, 4);
0117 DEFINE_QNODE(qhs_usb3_0, SDM845_SLAVE_USB3_0, 1, 4);
0118 DEFINE_QNODE(qhs_usb3_1, SDM845_SLAVE_USB3_1, 1, 4);
0119 DEFINE_QNODE(qhs_venus_cfg, SDM845_SLAVE_VENUS_CFG, 1, 4);
0120 DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM845_SLAVE_VSENSE_CTRL_CFG, 1, 4);
0121 DEFINE_QNODE(qns_cnoc_a2noc, SDM845_SLAVE_CNOC_A2NOC, 1, 8, SDM845_MASTER_CNOC_A2NOC);
0122 DEFINE_QNODE(srvc_cnoc, SDM845_SLAVE_SERVICE_CNOC, 1, 4);
0123 DEFINE_QNODE(qhs_llcc, SDM845_SLAVE_LLCC_CFG, 1, 4);
0124 DEFINE_QNODE(qhs_memnoc, SDM845_SLAVE_MEM_NOC_CFG, 1, 4, SDM845_MASTER_MEM_NOC_CFG);
0125 DEFINE_QNODE(qns_gladiator_sodv, SDM845_SLAVE_GNOC_SNOC, 1, 8, SDM845_MASTER_GNOC_SNOC);
0126 DEFINE_QNODE(qns_gnoc_memnoc, SDM845_SLAVE_GNOC_MEM_NOC, 2, 32, SDM845_MASTER_GNOC_MEM_NOC);
0127 DEFINE_QNODE(srvc_gnoc, SDM845_SLAVE_SERVICE_GNOC, 1, 4);
0128 DEFINE_QNODE(ebi, SDM845_SLAVE_EBI1, 4, 4);
0129 DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
0130 DEFINE_QNODE(qns_apps_io, SDM845_SLAVE_MEM_NOC_GNOC, 1, 32);
0131 DEFINE_QNODE(qns_llcc, SDM845_SLAVE_LLCC, 4, 16, SDM845_MASTER_LLCC);
0132 DEFINE_QNODE(qns_memnoc_snoc, SDM845_SLAVE_MEM_NOC_SNOC, 1, 8, SDM845_MASTER_MEM_NOC_SNOC);
0133 DEFINE_QNODE(srvc_memnoc, SDM845_SLAVE_SERVICE_MEM_NOC, 1, 4);
0134 DEFINE_QNODE(qns2_mem_noc, SDM845_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM845_MASTER_MNOC_SF_MEM_NOC);
0135 DEFINE_QNODE(qns_mem_noc_hf, SDM845_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM845_MASTER_MNOC_HF_MEM_NOC);
0136 DEFINE_QNODE(srvc_mnoc, SDM845_SLAVE_SERVICE_MNOC, 1, 4);
0137 DEFINE_QNODE(qhs_apss, SDM845_SLAVE_APPSS, 1, 8);
0138 DEFINE_QNODE(qns_cnoc, SDM845_SLAVE_SNOC_CNOC, 1, 8, SDM845_MASTER_SNOC_CNOC);
0139 DEFINE_QNODE(qns_memnoc_gc, SDM845_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM845_MASTER_SNOC_GC_MEM_NOC);
0140 DEFINE_QNODE(qns_memnoc_sf, SDM845_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM845_MASTER_SNOC_SF_MEM_NOC);
0141 DEFINE_QNODE(qxs_imem, SDM845_SLAVE_IMEM, 1, 8);
0142 DEFINE_QNODE(qxs_pcie, SDM845_SLAVE_PCIE_0, 1, 8);
0143 DEFINE_QNODE(qxs_pcie_gen3, SDM845_SLAVE_PCIE_1, 1, 8);
0144 DEFINE_QNODE(qxs_pimem, SDM845_SLAVE_PIMEM, 1, 8);
0145 DEFINE_QNODE(srvc_snoc, SDM845_SLAVE_SERVICE_SNOC, 1, 4);
0146 DEFINE_QNODE(xs_qdss_stm, SDM845_SLAVE_QDSS_STM, 1, 4);
0147 DEFINE_QNODE(xs_sys_tcu_cfg, SDM845_SLAVE_TCU, 1, 8);
0148 
0149 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
0150 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
0151 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
0152 DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
0153 DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io);
0154 DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
0155 DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc);
0156 DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc);
0157 DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu);
0158 DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
0159 DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps);
0160 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf);
0161 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
0162 DEFINE_QBCM(bcm_cn0, "CN0", false, &qhm_spdm, &qhm_tic, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pcie0_cfg, &qhs_pcie_gen3_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
0163 DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2);
0164 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
0165 DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc);
0166 DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc);
0167 DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem);
0168 DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
0169 DEFINE_QBCM(bcm_sn6, "SN6", false, &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg);
0170 DEFINE_QBCM(bcm_sn7, "SN7", false, &qxs_pcie);
0171 DEFINE_QBCM(bcm_sn8, "SN8", false, &qxs_pcie_gen3);
0172 DEFINE_QBCM(bcm_sn9, "SN9", false, &srvc_aggre1_noc, &qnm_aggre1_noc);
0173 DEFINE_QBCM(bcm_sn11, "SN11", false, &srvc_aggre2_noc, &qnm_aggre2_noc);
0174 DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gladiator_sodv, &xm_gic);
0175 DEFINE_QBCM(bcm_sn14, "SN14", false, &qnm_pcie_anoc);
0176 DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc);
0177 
0178 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
0179     &bcm_sn9,
0180     &bcm_qup0,
0181 };
0182 
0183 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
0184     [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
0185     [MASTER_TSIF] = &qhm_tsif,
0186     [MASTER_SDCC_2] = &xm_sdc2,
0187     [MASTER_SDCC_4] = &xm_sdc4,
0188     [MASTER_UFS_CARD] = &xm_ufs_card,
0189     [MASTER_UFS_MEM] = &xm_ufs_mem,
0190     [MASTER_PCIE_0] = &xm_pcie_0,
0191     [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
0192     [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
0193     [SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc,
0194     [MASTER_QUP_1] = &qhm_qup1,
0195 };
0196 
0197 static const struct qcom_icc_desc sdm845_aggre1_noc = {
0198     .nodes = aggre1_noc_nodes,
0199     .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
0200     .bcms = aggre1_noc_bcms,
0201     .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
0202 };
0203 
0204 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
0205     &bcm_ce0,
0206     &bcm_sn11,
0207     &bcm_qup0,
0208 };
0209 
0210 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
0211     [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
0212     [MASTER_QDSS_BAM] = &qhm_qdss_bam,
0213     [MASTER_CNOC_A2NOC] = &qnm_cnoc,
0214     [MASTER_CRYPTO] = &qxm_crypto,
0215     [MASTER_IPA] = &qxm_ipa,
0216     [MASTER_PCIE_1] = &xm_pcie3_1,
0217     [MASTER_QDSS_ETR] = &xm_qdss_etr,
0218     [MASTER_USB3_0] = &xm_usb3_0,
0219     [MASTER_USB3_1] = &xm_usb3_1,
0220     [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
0221     [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc,
0222     [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
0223     [MASTER_QUP_2] = &qhm_qup2,
0224 };
0225 
0226 static const struct qcom_icc_desc sdm845_aggre2_noc = {
0227     .nodes = aggre2_noc_nodes,
0228     .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
0229     .bcms = aggre2_noc_bcms,
0230     .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
0231 };
0232 
0233 static struct qcom_icc_bcm * const config_noc_bcms[] = {
0234     &bcm_cn0,
0235 };
0236 
0237 static struct qcom_icc_node * const config_noc_nodes[] = {
0238     [MASTER_SPDM] = &qhm_spdm,
0239     [MASTER_TIC] = &qhm_tic,
0240     [MASTER_SNOC_CNOC] = &qnm_snoc,
0241     [MASTER_QDSS_DAP] = &xm_qdss_dap,
0242     [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
0243     [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
0244     [SLAVE_AOP] = &qhs_aop,
0245     [SLAVE_AOSS] = &qhs_aoss,
0246     [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
0247     [SLAVE_CLK_CTL] = &qhs_clk_ctl,
0248     [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg,
0249     [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
0250     [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
0251     [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
0252     [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
0253     [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
0254     [SLAVE_GLM] = &qhs_glm,
0255     [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
0256     [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
0257     [SLAVE_IPA_CFG] = &qhs_ipa,
0258     [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
0259     [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
0260     [SLAVE_PCIE_1_CFG] = &qhs_pcie_gen3_cfg,
0261     [SLAVE_PDM] = &qhs_pdm,
0262     [SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south,
0263     [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
0264     [SLAVE_PRNG] = &qhs_prng,
0265     [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
0266     [SLAVE_BLSP_2] = &qhs_qupv3_north,
0267     [SLAVE_BLSP_1] = &qhs_qupv3_south,
0268     [SLAVE_SDCC_2] = &qhs_sdc2,
0269     [SLAVE_SDCC_4] = &qhs_sdc4,
0270     [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
0271     [SLAVE_SPDM_WRAPPER] = &qhs_spdm,
0272     [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
0273     [SLAVE_TCSR] = &qhs_tcsr,
0274     [SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
0275     [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
0276     [SLAVE_TSIF] = &qhs_tsif,
0277     [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
0278     [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
0279     [SLAVE_USB3_0] = &qhs_usb3_0,
0280     [SLAVE_USB3_1] = &qhs_usb3_1,
0281     [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
0282     [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
0283     [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
0284     [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
0285 };
0286 
0287 static const struct qcom_icc_desc sdm845_config_noc = {
0288     .nodes = config_noc_nodes,
0289     .num_nodes = ARRAY_SIZE(config_noc_nodes),
0290     .bcms = config_noc_bcms,
0291     .num_bcms = ARRAY_SIZE(config_noc_bcms),
0292 };
0293 
0294 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
0295 };
0296 
0297 static struct qcom_icc_node * const dc_noc_nodes[] = {
0298     [MASTER_CNOC_DC_NOC] = &qhm_cnoc,
0299     [SLAVE_LLCC_CFG] = &qhs_llcc,
0300     [SLAVE_MEM_NOC_CFG] = &qhs_memnoc,
0301 };
0302 
0303 static const struct qcom_icc_desc sdm845_dc_noc = {
0304     .nodes = dc_noc_nodes,
0305     .num_nodes = ARRAY_SIZE(dc_noc_nodes),
0306     .bcms = dc_noc_bcms,
0307     .num_bcms = ARRAY_SIZE(dc_noc_bcms),
0308 };
0309 
0310 static struct qcom_icc_bcm * const gladiator_noc_bcms[] = {
0311 };
0312 
0313 static struct qcom_icc_node * const gladiator_noc_nodes[] = {
0314     [MASTER_APPSS_PROC] = &acm_l3,
0315     [MASTER_GNOC_CFG] = &pm_gnoc_cfg,
0316     [SLAVE_GNOC_SNOC] = &qns_gladiator_sodv,
0317     [SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc,
0318     [SLAVE_SERVICE_GNOC] = &srvc_gnoc,
0319 };
0320 
0321 static const struct qcom_icc_desc sdm845_gladiator_noc = {
0322     .nodes = gladiator_noc_nodes,
0323     .num_nodes = ARRAY_SIZE(gladiator_noc_nodes),
0324     .bcms = gladiator_noc_bcms,
0325     .num_bcms = ARRAY_SIZE(gladiator_noc_bcms),
0326 };
0327 
0328 static struct qcom_icc_bcm * const mem_noc_bcms[] = {
0329     &bcm_mc0,
0330     &bcm_acv,
0331     &bcm_sh0,
0332     &bcm_sh1,
0333     &bcm_sh2,
0334     &bcm_sh3,
0335     &bcm_sh5,
0336 };
0337 
0338 static struct qcom_icc_node * const mem_noc_nodes[] = {
0339     [MASTER_TCU_0] = &acm_tcu,
0340     [MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg,
0341     [MASTER_GNOC_MEM_NOC] = &qnm_apps,
0342     [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
0343     [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
0344     [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
0345     [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
0346     [MASTER_GFX3D] = &qxm_gpu,
0347     [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
0348     [SLAVE_MEM_NOC_GNOC] = &qns_apps_io,
0349     [SLAVE_LLCC] = &qns_llcc,
0350     [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
0351     [SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc,
0352     [MASTER_LLCC] = &llcc_mc,
0353     [SLAVE_EBI1] = &ebi,
0354 };
0355 
0356 static const struct qcom_icc_desc sdm845_mem_noc = {
0357     .nodes = mem_noc_nodes,
0358     .num_nodes = ARRAY_SIZE(mem_noc_nodes),
0359     .bcms = mem_noc_bcms,
0360     .num_bcms = ARRAY_SIZE(mem_noc_bcms),
0361 };
0362 
0363 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
0364     &bcm_mm0,
0365     &bcm_mm1,
0366     &bcm_mm2,
0367     &bcm_mm3,
0368 };
0369 
0370 static struct qcom_icc_node * const mmss_noc_nodes[] = {
0371     [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
0372     [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
0373     [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
0374     [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
0375     [MASTER_MDP0] = &qxm_mdp0,
0376     [MASTER_MDP1] = &qxm_mdp1,
0377     [MASTER_ROTATOR] = &qxm_rot,
0378     [MASTER_VIDEO_P0] = &qxm_venus0,
0379     [MASTER_VIDEO_P1] = &qxm_venus1,
0380     [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
0381     [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
0382     [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
0383     [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
0384     [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
0385     [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
0386     [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
0387     [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
0388 };
0389 
0390 static const struct qcom_icc_desc sdm845_mmss_noc = {
0391     .nodes = mmss_noc_nodes,
0392     .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
0393     .bcms = mmss_noc_bcms,
0394     .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
0395 };
0396 
0397 static struct qcom_icc_bcm * const system_noc_bcms[] = {
0398     &bcm_sn0,
0399     &bcm_sn1,
0400     &bcm_sn2,
0401     &bcm_sn3,
0402     &bcm_sn4,
0403     &bcm_sn5,
0404     &bcm_sn6,
0405     &bcm_sn7,
0406     &bcm_sn8,
0407     &bcm_sn9,
0408     &bcm_sn11,
0409     &bcm_sn12,
0410     &bcm_sn14,
0411     &bcm_sn15,
0412 };
0413 
0414 static struct qcom_icc_node * const system_noc_nodes[] = {
0415     [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
0416     [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
0417     [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
0418     [MASTER_GNOC_SNOC] = &qnm_gladiator_sodv,
0419     [MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
0420     [MASTER_ANOC_PCIE_SNOC] = &qnm_pcie_anoc,
0421     [MASTER_PIMEM] = &qxm_pimem,
0422     [MASTER_GIC] = &xm_gic,
0423     [SLAVE_APPSS] = &qhs_apss,
0424     [SLAVE_SNOC_CNOC] = &qns_cnoc,
0425     [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc,
0426     [SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf,
0427     [SLAVE_IMEM] = &qxs_imem,
0428     [SLAVE_PCIE_0] = &qxs_pcie,
0429     [SLAVE_PCIE_1] = &qxs_pcie_gen3,
0430     [SLAVE_PIMEM] = &qxs_pimem,
0431     [SLAVE_SERVICE_SNOC] = &srvc_snoc,
0432     [SLAVE_QDSS_STM] = &xs_qdss_stm,
0433     [SLAVE_TCU] = &xs_sys_tcu_cfg,
0434 };
0435 
0436 static const struct qcom_icc_desc sdm845_system_noc = {
0437     .nodes = system_noc_nodes,
0438     .num_nodes = ARRAY_SIZE(system_noc_nodes),
0439     .bcms = system_noc_bcms,
0440     .num_bcms = ARRAY_SIZE(system_noc_bcms),
0441 };
0442 
0443 static const struct of_device_id qnoc_of_match[] = {
0444     { .compatible = "qcom,sdm845-aggre1-noc",
0445       .data = &sdm845_aggre1_noc},
0446     { .compatible = "qcom,sdm845-aggre2-noc",
0447       .data = &sdm845_aggre2_noc},
0448     { .compatible = "qcom,sdm845-config-noc",
0449       .data = &sdm845_config_noc},
0450     { .compatible = "qcom,sdm845-dc-noc",
0451       .data = &sdm845_dc_noc},
0452     { .compatible = "qcom,sdm845-gladiator-noc",
0453       .data = &sdm845_gladiator_noc},
0454     { .compatible = "qcom,sdm845-mem-noc",
0455       .data = &sdm845_mem_noc},
0456     { .compatible = "qcom,sdm845-mmss-noc",
0457       .data = &sdm845_mmss_noc},
0458     { .compatible = "qcom,sdm845-system-noc",
0459       .data = &sdm845_system_noc},
0460     { }
0461 };
0462 MODULE_DEVICE_TABLE(of, qnoc_of_match);
0463 
0464 static struct platform_driver qnoc_driver = {
0465     .probe = qcom_icc_rpmh_probe,
0466     .remove = qcom_icc_rpmh_remove,
0467     .driver = {
0468         .name = "qnoc-sdm845",
0469         .of_match_table = qnoc_of_match,
0470         .sync_state = icc_sync_state,
0471     },
0472 };
0473 module_platform_driver(qnoc_driver);
0474 
0475 MODULE_AUTHOR("David Dai <daidavid1@codeaurora.org>");
0476 MODULE_DESCRIPTION("Qualcomm sdm845 NoC driver");
0477 MODULE_LICENSE("GPL v2");
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