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0007 #include <dt-bindings/interconnect/qcom,sdm660.h>
0008 #include <linux/clk.h>
0009 #include <linux/device.h>
0010 #include <linux/interconnect-provider.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/of_device.h>
0014 #include <linux/of_platform.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/regmap.h>
0017 #include <linux/slab.h>
0018
0019 #include "icc-rpm.h"
0020 #include "smd-rpm.h"
0021
0022 enum {
0023 SDM660_MASTER_IPA = 1,
0024 SDM660_MASTER_CNOC_A2NOC,
0025 SDM660_MASTER_SDCC_1,
0026 SDM660_MASTER_SDCC_2,
0027 SDM660_MASTER_BLSP_1,
0028 SDM660_MASTER_BLSP_2,
0029 SDM660_MASTER_UFS,
0030 SDM660_MASTER_USB_HS,
0031 SDM660_MASTER_USB3,
0032 SDM660_MASTER_CRYPTO_C0,
0033 SDM660_MASTER_GNOC_BIMC,
0034 SDM660_MASTER_OXILI,
0035 SDM660_MASTER_MNOC_BIMC,
0036 SDM660_MASTER_SNOC_BIMC,
0037 SDM660_MASTER_PIMEM,
0038 SDM660_MASTER_SNOC_CNOC,
0039 SDM660_MASTER_QDSS_DAP,
0040 SDM660_MASTER_APPS_PROC,
0041 SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
0042 SDM660_MASTER_CNOC_MNOC_CFG,
0043 SDM660_MASTER_CPP,
0044 SDM660_MASTER_JPEG,
0045 SDM660_MASTER_MDP_P0,
0046 SDM660_MASTER_MDP_P1,
0047 SDM660_MASTER_VENUS,
0048 SDM660_MASTER_VFE,
0049 SDM660_MASTER_QDSS_ETR,
0050 SDM660_MASTER_QDSS_BAM,
0051 SDM660_MASTER_SNOC_CFG,
0052 SDM660_MASTER_BIMC_SNOC,
0053 SDM660_MASTER_A2NOC_SNOC,
0054 SDM660_MASTER_GNOC_SNOC,
0055
0056 SDM660_SLAVE_A2NOC_SNOC,
0057 SDM660_SLAVE_EBI,
0058 SDM660_SLAVE_HMSS_L3,
0059 SDM660_SLAVE_BIMC_SNOC,
0060 SDM660_SLAVE_CNOC_A2NOC,
0061 SDM660_SLAVE_MPM,
0062 SDM660_SLAVE_PMIC_ARB,
0063 SDM660_SLAVE_TLMM_NORTH,
0064 SDM660_SLAVE_TCSR,
0065 SDM660_SLAVE_PIMEM_CFG,
0066 SDM660_SLAVE_IMEM_CFG,
0067 SDM660_SLAVE_MESSAGE_RAM,
0068 SDM660_SLAVE_GLM,
0069 SDM660_SLAVE_BIMC_CFG,
0070 SDM660_SLAVE_PRNG,
0071 SDM660_SLAVE_SPDM,
0072 SDM660_SLAVE_QDSS_CFG,
0073 SDM660_SLAVE_CNOC_MNOC_CFG,
0074 SDM660_SLAVE_SNOC_CFG,
0075 SDM660_SLAVE_QM_CFG,
0076 SDM660_SLAVE_CLK_CTL,
0077 SDM660_SLAVE_MSS_CFG,
0078 SDM660_SLAVE_TLMM_SOUTH,
0079 SDM660_SLAVE_UFS_CFG,
0080 SDM660_SLAVE_A2NOC_CFG,
0081 SDM660_SLAVE_A2NOC_SMMU_CFG,
0082 SDM660_SLAVE_GPUSS_CFG,
0083 SDM660_SLAVE_AHB2PHY,
0084 SDM660_SLAVE_BLSP_1,
0085 SDM660_SLAVE_SDCC_1,
0086 SDM660_SLAVE_SDCC_2,
0087 SDM660_SLAVE_TLMM_CENTER,
0088 SDM660_SLAVE_BLSP_2,
0089 SDM660_SLAVE_PDM,
0090 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
0091 SDM660_SLAVE_USB_HS,
0092 SDM660_SLAVE_USB3_0,
0093 SDM660_SLAVE_SRVC_CNOC,
0094 SDM660_SLAVE_GNOC_BIMC,
0095 SDM660_SLAVE_GNOC_SNOC,
0096 SDM660_SLAVE_CAMERA_CFG,
0097 SDM660_SLAVE_CAMERA_THROTTLE_CFG,
0098 SDM660_SLAVE_MISC_CFG,
0099 SDM660_SLAVE_VENUS_THROTTLE_CFG,
0100 SDM660_SLAVE_VENUS_CFG,
0101 SDM660_SLAVE_MMSS_CLK_XPU_CFG,
0102 SDM660_SLAVE_MMSS_CLK_CFG,
0103 SDM660_SLAVE_MNOC_MPU_CFG,
0104 SDM660_SLAVE_DISPLAY_CFG,
0105 SDM660_SLAVE_CSI_PHY_CFG,
0106 SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
0107 SDM660_SLAVE_SMMU_CFG,
0108 SDM660_SLAVE_MNOC_BIMC,
0109 SDM660_SLAVE_SRVC_MNOC,
0110 SDM660_SLAVE_HMSS,
0111 SDM660_SLAVE_LPASS,
0112 SDM660_SLAVE_WLAN,
0113 SDM660_SLAVE_CDSP,
0114 SDM660_SLAVE_IPA,
0115 SDM660_SLAVE_SNOC_BIMC,
0116 SDM660_SLAVE_SNOC_CNOC,
0117 SDM660_SLAVE_IMEM,
0118 SDM660_SLAVE_PIMEM,
0119 SDM660_SLAVE_QDSS_STM,
0120 SDM660_SLAVE_SRVC_SNOC,
0121
0122 SDM660_A2NOC,
0123 SDM660_BIMC,
0124 SDM660_CNOC,
0125 SDM660_GNOC,
0126 SDM660_MNOC,
0127 SDM660_SNOC,
0128 };
0129
0130 static const char * const bus_mm_clocks[] = {
0131 "bus",
0132 "bus_a",
0133 "iface",
0134 };
0135
0136 static const char * const bus_a2noc_clocks[] = {
0137 "bus",
0138 "bus_a",
0139 "ipa",
0140 "ufs_axi",
0141 "aggre2_ufs_axi",
0142 "aggre2_usb3_axi",
0143 "cfg_noc_usb2_axi",
0144 };
0145
0146 static const u16 mas_ipa_links[] = {
0147 SDM660_SLAVE_A2NOC_SNOC
0148 };
0149
0150 static struct qcom_icc_node mas_ipa = {
0151 .name = "mas_ipa",
0152 .id = SDM660_MASTER_IPA,
0153 .buswidth = 8,
0154 .mas_rpm_id = 59,
0155 .slv_rpm_id = -1,
0156 .qos.ap_owned = true,
0157 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0158 .qos.areq_prio = 1,
0159 .qos.prio_level = 1,
0160 .qos.qos_port = 3,
0161 .num_links = ARRAY_SIZE(mas_ipa_links),
0162 .links = mas_ipa_links,
0163 };
0164
0165 static const u16 mas_cnoc_a2noc_links[] = {
0166 SDM660_SLAVE_A2NOC_SNOC
0167 };
0168
0169 static struct qcom_icc_node mas_cnoc_a2noc = {
0170 .name = "mas_cnoc_a2noc",
0171 .id = SDM660_MASTER_CNOC_A2NOC,
0172 .buswidth = 8,
0173 .mas_rpm_id = 146,
0174 .slv_rpm_id = -1,
0175 .qos.ap_owned = true,
0176 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0177 .num_links = ARRAY_SIZE(mas_cnoc_a2noc_links),
0178 .links = mas_cnoc_a2noc_links,
0179 };
0180
0181 static const u16 mas_sdcc_1_links[] = {
0182 SDM660_SLAVE_A2NOC_SNOC
0183 };
0184
0185 static struct qcom_icc_node mas_sdcc_1 = {
0186 .name = "mas_sdcc_1",
0187 .id = SDM660_MASTER_SDCC_1,
0188 .buswidth = 8,
0189 .mas_rpm_id = 33,
0190 .slv_rpm_id = -1,
0191 .num_links = ARRAY_SIZE(mas_sdcc_1_links),
0192 .links = mas_sdcc_1_links,
0193 };
0194
0195 static const u16 mas_sdcc_2_links[] = {
0196 SDM660_SLAVE_A2NOC_SNOC
0197 };
0198
0199 static struct qcom_icc_node mas_sdcc_2 = {
0200 .name = "mas_sdcc_2",
0201 .id = SDM660_MASTER_SDCC_2,
0202 .buswidth = 8,
0203 .mas_rpm_id = 35,
0204 .slv_rpm_id = -1,
0205 .num_links = ARRAY_SIZE(mas_sdcc_2_links),
0206 .links = mas_sdcc_2_links,
0207 };
0208
0209 static const u16 mas_blsp_1_links[] = {
0210 SDM660_SLAVE_A2NOC_SNOC
0211 };
0212
0213 static struct qcom_icc_node mas_blsp_1 = {
0214 .name = "mas_blsp_1",
0215 .id = SDM660_MASTER_BLSP_1,
0216 .buswidth = 4,
0217 .mas_rpm_id = 41,
0218 .slv_rpm_id = -1,
0219 .num_links = ARRAY_SIZE(mas_blsp_1_links),
0220 .links = mas_blsp_1_links,
0221 };
0222
0223 static const u16 mas_blsp_2_links[] = {
0224 SDM660_SLAVE_A2NOC_SNOC
0225 };
0226
0227 static struct qcom_icc_node mas_blsp_2 = {
0228 .name = "mas_blsp_2",
0229 .id = SDM660_MASTER_BLSP_2,
0230 .buswidth = 4,
0231 .mas_rpm_id = 39,
0232 .slv_rpm_id = -1,
0233 .num_links = ARRAY_SIZE(mas_blsp_2_links),
0234 .links = mas_blsp_2_links,
0235 };
0236
0237 static const u16 mas_ufs_links[] = {
0238 SDM660_SLAVE_A2NOC_SNOC
0239 };
0240
0241 static struct qcom_icc_node mas_ufs = {
0242 .name = "mas_ufs",
0243 .id = SDM660_MASTER_UFS,
0244 .buswidth = 8,
0245 .mas_rpm_id = 68,
0246 .slv_rpm_id = -1,
0247 .qos.ap_owned = true,
0248 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0249 .qos.areq_prio = 1,
0250 .qos.prio_level = 1,
0251 .qos.qos_port = 4,
0252 .num_links = ARRAY_SIZE(mas_ufs_links),
0253 .links = mas_ufs_links,
0254 };
0255
0256 static const u16 mas_usb_hs_links[] = {
0257 SDM660_SLAVE_A2NOC_SNOC
0258 };
0259
0260 static struct qcom_icc_node mas_usb_hs = {
0261 .name = "mas_usb_hs",
0262 .id = SDM660_MASTER_USB_HS,
0263 .buswidth = 8,
0264 .mas_rpm_id = 42,
0265 .slv_rpm_id = -1,
0266 .qos.ap_owned = true,
0267 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0268 .qos.areq_prio = 1,
0269 .qos.prio_level = 1,
0270 .qos.qos_port = 1,
0271 .num_links = ARRAY_SIZE(mas_usb_hs_links),
0272 .links = mas_usb_hs_links,
0273 };
0274
0275 static const u16 mas_usb3_links[] = {
0276 SDM660_SLAVE_A2NOC_SNOC
0277 };
0278
0279 static struct qcom_icc_node mas_usb3 = {
0280 .name = "mas_usb3",
0281 .id = SDM660_MASTER_USB3,
0282 .buswidth = 8,
0283 .mas_rpm_id = 32,
0284 .slv_rpm_id = -1,
0285 .qos.ap_owned = true,
0286 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0287 .qos.areq_prio = 1,
0288 .qos.prio_level = 1,
0289 .qos.qos_port = 2,
0290 .num_links = ARRAY_SIZE(mas_usb3_links),
0291 .links = mas_usb3_links,
0292 };
0293
0294 static const u16 mas_crypto_links[] = {
0295 SDM660_SLAVE_A2NOC_SNOC
0296 };
0297
0298 static struct qcom_icc_node mas_crypto = {
0299 .name = "mas_crypto",
0300 .id = SDM660_MASTER_CRYPTO_C0,
0301 .buswidth = 8,
0302 .mas_rpm_id = 23,
0303 .slv_rpm_id = -1,
0304 .qos.ap_owned = true,
0305 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0306 .qos.areq_prio = 1,
0307 .qos.prio_level = 1,
0308 .qos.qos_port = 11,
0309 .num_links = ARRAY_SIZE(mas_crypto_links),
0310 .links = mas_crypto_links,
0311 };
0312
0313 static const u16 mas_gnoc_bimc_links[] = {
0314 SDM660_SLAVE_EBI
0315 };
0316
0317 static struct qcom_icc_node mas_gnoc_bimc = {
0318 .name = "mas_gnoc_bimc",
0319 .id = SDM660_MASTER_GNOC_BIMC,
0320 .buswidth = 4,
0321 .mas_rpm_id = 144,
0322 .slv_rpm_id = -1,
0323 .qos.ap_owned = true,
0324 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0325 .qos.areq_prio = 0,
0326 .qos.prio_level = 0,
0327 .qos.qos_port = 0,
0328 .num_links = ARRAY_SIZE(mas_gnoc_bimc_links),
0329 .links = mas_gnoc_bimc_links,
0330 };
0331
0332 static const u16 mas_oxili_links[] = {
0333 SDM660_SLAVE_HMSS_L3,
0334 SDM660_SLAVE_EBI,
0335 SDM660_SLAVE_BIMC_SNOC
0336 };
0337
0338 static struct qcom_icc_node mas_oxili = {
0339 .name = "mas_oxili",
0340 .id = SDM660_MASTER_OXILI,
0341 .buswidth = 4,
0342 .mas_rpm_id = 6,
0343 .slv_rpm_id = -1,
0344 .qos.ap_owned = true,
0345 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0346 .qos.areq_prio = 0,
0347 .qos.prio_level = 0,
0348 .qos.qos_port = 1,
0349 .num_links = ARRAY_SIZE(mas_oxili_links),
0350 .links = mas_oxili_links,
0351 };
0352
0353 static const u16 mas_mnoc_bimc_links[] = {
0354 SDM660_SLAVE_HMSS_L3,
0355 SDM660_SLAVE_EBI,
0356 SDM660_SLAVE_BIMC_SNOC
0357 };
0358
0359 static struct qcom_icc_node mas_mnoc_bimc = {
0360 .name = "mas_mnoc_bimc",
0361 .id = SDM660_MASTER_MNOC_BIMC,
0362 .buswidth = 4,
0363 .mas_rpm_id = 2,
0364 .slv_rpm_id = -1,
0365 .qos.ap_owned = true,
0366 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0367 .qos.areq_prio = 0,
0368 .qos.prio_level = 0,
0369 .qos.qos_port = 2,
0370 .num_links = ARRAY_SIZE(mas_mnoc_bimc_links),
0371 .links = mas_mnoc_bimc_links,
0372 };
0373
0374 static const u16 mas_snoc_bimc_links[] = {
0375 SDM660_SLAVE_HMSS_L3,
0376 SDM660_SLAVE_EBI
0377 };
0378
0379 static struct qcom_icc_node mas_snoc_bimc = {
0380 .name = "mas_snoc_bimc",
0381 .id = SDM660_MASTER_SNOC_BIMC,
0382 .buswidth = 4,
0383 .mas_rpm_id = 3,
0384 .slv_rpm_id = -1,
0385 .num_links = ARRAY_SIZE(mas_snoc_bimc_links),
0386 .links = mas_snoc_bimc_links,
0387 };
0388
0389 static const u16 mas_pimem_links[] = {
0390 SDM660_SLAVE_HMSS_L3,
0391 SDM660_SLAVE_EBI
0392 };
0393
0394 static struct qcom_icc_node mas_pimem = {
0395 .name = "mas_pimem",
0396 .id = SDM660_MASTER_PIMEM,
0397 .buswidth = 4,
0398 .mas_rpm_id = 113,
0399 .slv_rpm_id = -1,
0400 .qos.ap_owned = true,
0401 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0402 .qos.areq_prio = 1,
0403 .qos.prio_level = 1,
0404 .qos.qos_port = 4,
0405 .num_links = ARRAY_SIZE(mas_pimem_links),
0406 .links = mas_pimem_links,
0407 };
0408
0409 static const u16 mas_snoc_cnoc_links[] = {
0410 SDM660_SLAVE_CLK_CTL,
0411 SDM660_SLAVE_QDSS_CFG,
0412 SDM660_SLAVE_QM_CFG,
0413 SDM660_SLAVE_SRVC_CNOC,
0414 SDM660_SLAVE_UFS_CFG,
0415 SDM660_SLAVE_TCSR,
0416 SDM660_SLAVE_A2NOC_SMMU_CFG,
0417 SDM660_SLAVE_SNOC_CFG,
0418 SDM660_SLAVE_TLMM_SOUTH,
0419 SDM660_SLAVE_MPM,
0420 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
0421 SDM660_SLAVE_SDCC_2,
0422 SDM660_SLAVE_SDCC_1,
0423 SDM660_SLAVE_SPDM,
0424 SDM660_SLAVE_PMIC_ARB,
0425 SDM660_SLAVE_PRNG,
0426 SDM660_SLAVE_MSS_CFG,
0427 SDM660_SLAVE_GPUSS_CFG,
0428 SDM660_SLAVE_IMEM_CFG,
0429 SDM660_SLAVE_USB3_0,
0430 SDM660_SLAVE_A2NOC_CFG,
0431 SDM660_SLAVE_TLMM_NORTH,
0432 SDM660_SLAVE_USB_HS,
0433 SDM660_SLAVE_PDM,
0434 SDM660_SLAVE_TLMM_CENTER,
0435 SDM660_SLAVE_AHB2PHY,
0436 SDM660_SLAVE_BLSP_2,
0437 SDM660_SLAVE_BLSP_1,
0438 SDM660_SLAVE_PIMEM_CFG,
0439 SDM660_SLAVE_GLM,
0440 SDM660_SLAVE_MESSAGE_RAM,
0441 SDM660_SLAVE_BIMC_CFG,
0442 SDM660_SLAVE_CNOC_MNOC_CFG
0443 };
0444
0445 static struct qcom_icc_node mas_snoc_cnoc = {
0446 .name = "mas_snoc_cnoc",
0447 .id = SDM660_MASTER_SNOC_CNOC,
0448 .buswidth = 8,
0449 .mas_rpm_id = 52,
0450 .slv_rpm_id = -1,
0451 .qos.ap_owned = true,
0452 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0453 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links),
0454 .links = mas_snoc_cnoc_links,
0455 };
0456
0457 static const u16 mas_qdss_dap_links[] = {
0458 SDM660_SLAVE_CLK_CTL,
0459 SDM660_SLAVE_QDSS_CFG,
0460 SDM660_SLAVE_QM_CFG,
0461 SDM660_SLAVE_SRVC_CNOC,
0462 SDM660_SLAVE_UFS_CFG,
0463 SDM660_SLAVE_TCSR,
0464 SDM660_SLAVE_A2NOC_SMMU_CFG,
0465 SDM660_SLAVE_SNOC_CFG,
0466 SDM660_SLAVE_TLMM_SOUTH,
0467 SDM660_SLAVE_MPM,
0468 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
0469 SDM660_SLAVE_SDCC_2,
0470 SDM660_SLAVE_SDCC_1,
0471 SDM660_SLAVE_SPDM,
0472 SDM660_SLAVE_PMIC_ARB,
0473 SDM660_SLAVE_PRNG,
0474 SDM660_SLAVE_MSS_CFG,
0475 SDM660_SLAVE_GPUSS_CFG,
0476 SDM660_SLAVE_IMEM_CFG,
0477 SDM660_SLAVE_USB3_0,
0478 SDM660_SLAVE_A2NOC_CFG,
0479 SDM660_SLAVE_TLMM_NORTH,
0480 SDM660_SLAVE_USB_HS,
0481 SDM660_SLAVE_PDM,
0482 SDM660_SLAVE_TLMM_CENTER,
0483 SDM660_SLAVE_AHB2PHY,
0484 SDM660_SLAVE_BLSP_2,
0485 SDM660_SLAVE_BLSP_1,
0486 SDM660_SLAVE_PIMEM_CFG,
0487 SDM660_SLAVE_GLM,
0488 SDM660_SLAVE_MESSAGE_RAM,
0489 SDM660_SLAVE_CNOC_A2NOC,
0490 SDM660_SLAVE_BIMC_CFG,
0491 SDM660_SLAVE_CNOC_MNOC_CFG
0492 };
0493
0494 static struct qcom_icc_node mas_qdss_dap = {
0495 .name = "mas_qdss_dap",
0496 .id = SDM660_MASTER_QDSS_DAP,
0497 .buswidth = 8,
0498 .mas_rpm_id = 49,
0499 .slv_rpm_id = -1,
0500 .qos.ap_owned = true,
0501 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0502 .num_links = ARRAY_SIZE(mas_qdss_dap_links),
0503 .links = mas_qdss_dap_links,
0504 };
0505
0506 static const u16 mas_apss_proc_links[] = {
0507 SDM660_SLAVE_GNOC_SNOC,
0508 SDM660_SLAVE_GNOC_BIMC
0509 };
0510
0511 static struct qcom_icc_node mas_apss_proc = {
0512 .name = "mas_apss_proc",
0513 .id = SDM660_MASTER_APPS_PROC,
0514 .buswidth = 16,
0515 .mas_rpm_id = 0,
0516 .slv_rpm_id = -1,
0517 .qos.ap_owned = true,
0518 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0519 .num_links = ARRAY_SIZE(mas_apss_proc_links),
0520 .links = mas_apss_proc_links,
0521 };
0522
0523 static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = {
0524 SDM660_SLAVE_VENUS_THROTTLE_CFG,
0525 SDM660_SLAVE_VENUS_CFG,
0526 SDM660_SLAVE_CAMERA_THROTTLE_CFG,
0527 SDM660_SLAVE_SMMU_CFG,
0528 SDM660_SLAVE_CAMERA_CFG,
0529 SDM660_SLAVE_CSI_PHY_CFG,
0530 SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
0531 SDM660_SLAVE_DISPLAY_CFG,
0532 SDM660_SLAVE_MMSS_CLK_CFG,
0533 SDM660_SLAVE_MNOC_MPU_CFG,
0534 SDM660_SLAVE_MISC_CFG,
0535 SDM660_SLAVE_MMSS_CLK_XPU_CFG
0536 };
0537
0538 static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = {
0539 .name = "mas_cnoc_mnoc_mmss_cfg",
0540 .id = SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
0541 .buswidth = 8,
0542 .mas_rpm_id = 4,
0543 .slv_rpm_id = -1,
0544 .qos.ap_owned = true,
0545 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0546 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links),
0547 .links = mas_cnoc_mnoc_mmss_cfg_links,
0548 };
0549
0550 static const u16 mas_cnoc_mnoc_cfg_links[] = {
0551 SDM660_SLAVE_SRVC_MNOC
0552 };
0553
0554 static struct qcom_icc_node mas_cnoc_mnoc_cfg = {
0555 .name = "mas_cnoc_mnoc_cfg",
0556 .id = SDM660_MASTER_CNOC_MNOC_CFG,
0557 .buswidth = 4,
0558 .mas_rpm_id = 5,
0559 .slv_rpm_id = -1,
0560 .qos.ap_owned = true,
0561 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0562 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links),
0563 .links = mas_cnoc_mnoc_cfg_links,
0564 };
0565
0566 static const u16 mas_cpp_links[] = {
0567 SDM660_SLAVE_MNOC_BIMC
0568 };
0569
0570 static struct qcom_icc_node mas_cpp = {
0571 .name = "mas_cpp",
0572 .id = SDM660_MASTER_CPP,
0573 .buswidth = 16,
0574 .mas_rpm_id = 115,
0575 .slv_rpm_id = -1,
0576 .qos.ap_owned = true,
0577 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0578 .qos.areq_prio = 0,
0579 .qos.prio_level = 0,
0580 .qos.qos_port = 4,
0581 .num_links = ARRAY_SIZE(mas_cpp_links),
0582 .links = mas_cpp_links,
0583 };
0584
0585 static const u16 mas_jpeg_links[] = {
0586 SDM660_SLAVE_MNOC_BIMC
0587 };
0588
0589 static struct qcom_icc_node mas_jpeg = {
0590 .name = "mas_jpeg",
0591 .id = SDM660_MASTER_JPEG,
0592 .buswidth = 16,
0593 .mas_rpm_id = 7,
0594 .slv_rpm_id = -1,
0595 .qos.ap_owned = true,
0596 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0597 .qos.areq_prio = 0,
0598 .qos.prio_level = 0,
0599 .qos.qos_port = 6,
0600 .num_links = ARRAY_SIZE(mas_jpeg_links),
0601 .links = mas_jpeg_links,
0602 };
0603
0604 static const u16 mas_mdp_p0_links[] = {
0605 SDM660_SLAVE_MNOC_BIMC
0606 };
0607
0608 static struct qcom_icc_node mas_mdp_p0 = {
0609 .name = "mas_mdp_p0",
0610 .id = SDM660_MASTER_MDP_P0,
0611 .buswidth = 16,
0612 .mas_rpm_id = 8,
0613 .slv_rpm_id = -1,
0614 .qos.ap_owned = true,
0615 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0616 .qos.areq_prio = 0,
0617 .qos.prio_level = 0,
0618 .qos.qos_port = 0,
0619 .num_links = ARRAY_SIZE(mas_mdp_p0_links),
0620 .links = mas_mdp_p0_links,
0621 };
0622
0623 static const u16 mas_mdp_p1_links[] = {
0624 SDM660_SLAVE_MNOC_BIMC
0625 };
0626
0627 static struct qcom_icc_node mas_mdp_p1 = {
0628 .name = "mas_mdp_p1",
0629 .id = SDM660_MASTER_MDP_P1,
0630 .buswidth = 16,
0631 .mas_rpm_id = 61,
0632 .slv_rpm_id = -1,
0633 .qos.ap_owned = true,
0634 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0635 .qos.areq_prio = 0,
0636 .qos.prio_level = 0,
0637 .qos.qos_port = 1,
0638 .num_links = ARRAY_SIZE(mas_mdp_p1_links),
0639 .links = mas_mdp_p1_links,
0640 };
0641
0642 static const u16 mas_venus_links[] = {
0643 SDM660_SLAVE_MNOC_BIMC
0644 };
0645
0646 static struct qcom_icc_node mas_venus = {
0647 .name = "mas_venus",
0648 .id = SDM660_MASTER_VENUS,
0649 .buswidth = 16,
0650 .mas_rpm_id = 9,
0651 .slv_rpm_id = -1,
0652 .qos.ap_owned = true,
0653 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0654 .qos.areq_prio = 0,
0655 .qos.prio_level = 0,
0656 .qos.qos_port = 1,
0657 .num_links = ARRAY_SIZE(mas_venus_links),
0658 .links = mas_venus_links,
0659 };
0660
0661 static const u16 mas_vfe_links[] = {
0662 SDM660_SLAVE_MNOC_BIMC
0663 };
0664
0665 static struct qcom_icc_node mas_vfe = {
0666 .name = "mas_vfe",
0667 .id = SDM660_MASTER_VFE,
0668 .buswidth = 16,
0669 .mas_rpm_id = 11,
0670 .slv_rpm_id = -1,
0671 .qos.ap_owned = true,
0672 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0673 .qos.areq_prio = 0,
0674 .qos.prio_level = 0,
0675 .qos.qos_port = 5,
0676 .num_links = ARRAY_SIZE(mas_vfe_links),
0677 .links = mas_vfe_links,
0678 };
0679
0680 static const u16 mas_qdss_etr_links[] = {
0681 SDM660_SLAVE_PIMEM,
0682 SDM660_SLAVE_IMEM,
0683 SDM660_SLAVE_SNOC_CNOC,
0684 SDM660_SLAVE_SNOC_BIMC
0685 };
0686
0687 static struct qcom_icc_node mas_qdss_etr = {
0688 .name = "mas_qdss_etr",
0689 .id = SDM660_MASTER_QDSS_ETR,
0690 .buswidth = 8,
0691 .mas_rpm_id = 31,
0692 .slv_rpm_id = -1,
0693 .qos.ap_owned = true,
0694 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0695 .qos.areq_prio = 1,
0696 .qos.prio_level = 1,
0697 .qos.qos_port = 1,
0698 .num_links = ARRAY_SIZE(mas_qdss_etr_links),
0699 .links = mas_qdss_etr_links,
0700 };
0701
0702 static const u16 mas_qdss_bam_links[] = {
0703 SDM660_SLAVE_PIMEM,
0704 SDM660_SLAVE_IMEM,
0705 SDM660_SLAVE_SNOC_CNOC,
0706 SDM660_SLAVE_SNOC_BIMC
0707 };
0708
0709 static struct qcom_icc_node mas_qdss_bam = {
0710 .name = "mas_qdss_bam",
0711 .id = SDM660_MASTER_QDSS_BAM,
0712 .buswidth = 4,
0713 .mas_rpm_id = 19,
0714 .slv_rpm_id = -1,
0715 .qos.ap_owned = true,
0716 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0717 .qos.areq_prio = 1,
0718 .qos.prio_level = 1,
0719 .qos.qos_port = 0,
0720 .num_links = ARRAY_SIZE(mas_qdss_bam_links),
0721 .links = mas_qdss_bam_links,
0722 };
0723
0724 static const u16 mas_snoc_cfg_links[] = {
0725 SDM660_SLAVE_SRVC_SNOC
0726 };
0727
0728 static struct qcom_icc_node mas_snoc_cfg = {
0729 .name = "mas_snoc_cfg",
0730 .id = SDM660_MASTER_SNOC_CFG,
0731 .buswidth = 4,
0732 .mas_rpm_id = 20,
0733 .slv_rpm_id = -1,
0734 .num_links = ARRAY_SIZE(mas_snoc_cfg_links),
0735 .links = mas_snoc_cfg_links,
0736 };
0737
0738 static const u16 mas_bimc_snoc_links[] = {
0739 SDM660_SLAVE_PIMEM,
0740 SDM660_SLAVE_IPA,
0741 SDM660_SLAVE_QDSS_STM,
0742 SDM660_SLAVE_LPASS,
0743 SDM660_SLAVE_HMSS,
0744 SDM660_SLAVE_CDSP,
0745 SDM660_SLAVE_SNOC_CNOC,
0746 SDM660_SLAVE_WLAN,
0747 SDM660_SLAVE_IMEM
0748 };
0749
0750 static struct qcom_icc_node mas_bimc_snoc = {
0751 .name = "mas_bimc_snoc",
0752 .id = SDM660_MASTER_BIMC_SNOC,
0753 .buswidth = 8,
0754 .mas_rpm_id = 21,
0755 .slv_rpm_id = -1,
0756 .num_links = ARRAY_SIZE(mas_bimc_snoc_links),
0757 .links = mas_bimc_snoc_links,
0758 };
0759
0760 static const u16 mas_gnoc_snoc_links[] = {
0761 SDM660_SLAVE_PIMEM,
0762 SDM660_SLAVE_IPA,
0763 SDM660_SLAVE_QDSS_STM,
0764 SDM660_SLAVE_LPASS,
0765 SDM660_SLAVE_HMSS,
0766 SDM660_SLAVE_CDSP,
0767 SDM660_SLAVE_SNOC_CNOC,
0768 SDM660_SLAVE_WLAN,
0769 SDM660_SLAVE_IMEM
0770 };
0771
0772 static struct qcom_icc_node mas_gnoc_snoc = {
0773 .name = "mas_gnoc_snoc",
0774 .id = SDM660_MASTER_GNOC_SNOC,
0775 .buswidth = 8,
0776 .mas_rpm_id = 150,
0777 .slv_rpm_id = -1,
0778 .num_links = ARRAY_SIZE(mas_gnoc_snoc_links),
0779 .links = mas_gnoc_snoc_links,
0780 };
0781
0782 static const u16 mas_a2noc_snoc_links[] = {
0783 SDM660_SLAVE_PIMEM,
0784 SDM660_SLAVE_IPA,
0785 SDM660_SLAVE_QDSS_STM,
0786 SDM660_SLAVE_LPASS,
0787 SDM660_SLAVE_HMSS,
0788 SDM660_SLAVE_SNOC_BIMC,
0789 SDM660_SLAVE_CDSP,
0790 SDM660_SLAVE_SNOC_CNOC,
0791 SDM660_SLAVE_WLAN,
0792 SDM660_SLAVE_IMEM
0793 };
0794
0795 static struct qcom_icc_node mas_a2noc_snoc = {
0796 .name = "mas_a2noc_snoc",
0797 .id = SDM660_MASTER_A2NOC_SNOC,
0798 .buswidth = 16,
0799 .mas_rpm_id = 112,
0800 .slv_rpm_id = -1,
0801 .num_links = ARRAY_SIZE(mas_a2noc_snoc_links),
0802 .links = mas_a2noc_snoc_links,
0803 };
0804
0805 static const u16 slv_a2noc_snoc_links[] = {
0806 SDM660_MASTER_A2NOC_SNOC
0807 };
0808
0809 static struct qcom_icc_node slv_a2noc_snoc = {
0810 .name = "slv_a2noc_snoc",
0811 .id = SDM660_SLAVE_A2NOC_SNOC,
0812 .buswidth = 16,
0813 .mas_rpm_id = -1,
0814 .slv_rpm_id = 143,
0815 .num_links = ARRAY_SIZE(slv_a2noc_snoc_links),
0816 .links = slv_a2noc_snoc_links,
0817 };
0818
0819 static struct qcom_icc_node slv_ebi = {
0820 .name = "slv_ebi",
0821 .id = SDM660_SLAVE_EBI,
0822 .buswidth = 4,
0823 .mas_rpm_id = -1,
0824 .slv_rpm_id = 0,
0825 };
0826
0827 static struct qcom_icc_node slv_hmss_l3 = {
0828 .name = "slv_hmss_l3",
0829 .id = SDM660_SLAVE_HMSS_L3,
0830 .buswidth = 4,
0831 .mas_rpm_id = -1,
0832 .slv_rpm_id = 160,
0833 };
0834
0835 static const u16 slv_bimc_snoc_links[] = {
0836 SDM660_MASTER_BIMC_SNOC
0837 };
0838
0839 static struct qcom_icc_node slv_bimc_snoc = {
0840 .name = "slv_bimc_snoc",
0841 .id = SDM660_SLAVE_BIMC_SNOC,
0842 .buswidth = 4,
0843 .mas_rpm_id = -1,
0844 .slv_rpm_id = 2,
0845 .num_links = ARRAY_SIZE(slv_bimc_snoc_links),
0846 .links = slv_bimc_snoc_links,
0847 };
0848
0849 static const u16 slv_cnoc_a2noc_links[] = {
0850 SDM660_MASTER_CNOC_A2NOC
0851 };
0852
0853 static struct qcom_icc_node slv_cnoc_a2noc = {
0854 .name = "slv_cnoc_a2noc",
0855 .id = SDM660_SLAVE_CNOC_A2NOC,
0856 .buswidth = 8,
0857 .mas_rpm_id = -1,
0858 .slv_rpm_id = 208,
0859 .qos.ap_owned = true,
0860 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0861 .num_links = ARRAY_SIZE(slv_cnoc_a2noc_links),
0862 .links = slv_cnoc_a2noc_links,
0863 };
0864
0865 static struct qcom_icc_node slv_mpm = {
0866 .name = "slv_mpm",
0867 .id = SDM660_SLAVE_MPM,
0868 .buswidth = 4,
0869 .mas_rpm_id = -1,
0870 .slv_rpm_id = 62,
0871 .qos.ap_owned = true,
0872 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0873 };
0874
0875 static struct qcom_icc_node slv_pmic_arb = {
0876 .name = "slv_pmic_arb",
0877 .id = SDM660_SLAVE_PMIC_ARB,
0878 .buswidth = 4,
0879 .mas_rpm_id = -1,
0880 .slv_rpm_id = 59,
0881 .qos.ap_owned = true,
0882 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0883 };
0884
0885 static struct qcom_icc_node slv_tlmm_north = {
0886 .name = "slv_tlmm_north",
0887 .id = SDM660_SLAVE_TLMM_NORTH,
0888 .buswidth = 8,
0889 .mas_rpm_id = -1,
0890 .slv_rpm_id = 214,
0891 .qos.ap_owned = true,
0892 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0893 };
0894
0895 static struct qcom_icc_node slv_tcsr = {
0896 .name = "slv_tcsr",
0897 .id = SDM660_SLAVE_TCSR,
0898 .buswidth = 4,
0899 .mas_rpm_id = -1,
0900 .slv_rpm_id = 50,
0901 .qos.ap_owned = true,
0902 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0903 };
0904
0905 static struct qcom_icc_node slv_pimem_cfg = {
0906 .name = "slv_pimem_cfg",
0907 .id = SDM660_SLAVE_PIMEM_CFG,
0908 .buswidth = 4,
0909 .mas_rpm_id = -1,
0910 .slv_rpm_id = 167,
0911 .qos.ap_owned = true,
0912 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0913 };
0914
0915 static struct qcom_icc_node slv_imem_cfg = {
0916 .name = "slv_imem_cfg",
0917 .id = SDM660_SLAVE_IMEM_CFG,
0918 .buswidth = 4,
0919 .mas_rpm_id = -1,
0920 .slv_rpm_id = 54,
0921 .qos.ap_owned = true,
0922 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0923 };
0924
0925 static struct qcom_icc_node slv_message_ram = {
0926 .name = "slv_message_ram",
0927 .id = SDM660_SLAVE_MESSAGE_RAM,
0928 .buswidth = 4,
0929 .mas_rpm_id = -1,
0930 .slv_rpm_id = 55,
0931 .qos.ap_owned = true,
0932 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0933 };
0934
0935 static struct qcom_icc_node slv_glm = {
0936 .name = "slv_glm",
0937 .id = SDM660_SLAVE_GLM,
0938 .buswidth = 4,
0939 .mas_rpm_id = -1,
0940 .slv_rpm_id = 209,
0941 .qos.ap_owned = true,
0942 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0943 };
0944
0945 static struct qcom_icc_node slv_bimc_cfg = {
0946 .name = "slv_bimc_cfg",
0947 .id = SDM660_SLAVE_BIMC_CFG,
0948 .buswidth = 4,
0949 .mas_rpm_id = -1,
0950 .slv_rpm_id = 56,
0951 .qos.ap_owned = true,
0952 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0953 };
0954
0955 static struct qcom_icc_node slv_prng = {
0956 .name = "slv_prng",
0957 .id = SDM660_SLAVE_PRNG,
0958 .buswidth = 4,
0959 .mas_rpm_id = -1,
0960 .slv_rpm_id = 44,
0961 .qos.ap_owned = true,
0962 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0963 };
0964
0965 static struct qcom_icc_node slv_spdm = {
0966 .name = "slv_spdm",
0967 .id = SDM660_SLAVE_SPDM,
0968 .buswidth = 4,
0969 .mas_rpm_id = -1,
0970 .slv_rpm_id = 60,
0971 .qos.ap_owned = true,
0972 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0973 };
0974
0975 static struct qcom_icc_node slv_qdss_cfg = {
0976 .name = "slv_qdss_cfg",
0977 .id = SDM660_SLAVE_QDSS_CFG,
0978 .buswidth = 4,
0979 .mas_rpm_id = -1,
0980 .slv_rpm_id = 63,
0981 .qos.ap_owned = true,
0982 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0983 };
0984
0985 static const u16 slv_cnoc_mnoc_cfg_links[] = {
0986 SDM660_MASTER_CNOC_MNOC_CFG
0987 };
0988
0989 static struct qcom_icc_node slv_cnoc_mnoc_cfg = {
0990 .name = "slv_cnoc_mnoc_cfg",
0991 .id = SDM660_SLAVE_CNOC_MNOC_CFG,
0992 .buswidth = 4,
0993 .mas_rpm_id = -1,
0994 .slv_rpm_id = 66,
0995 .qos.ap_owned = true,
0996 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0997 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links),
0998 .links = slv_cnoc_mnoc_cfg_links,
0999 };
1000
1001 static struct qcom_icc_node slv_snoc_cfg = {
1002 .name = "slv_snoc_cfg",
1003 .id = SDM660_SLAVE_SNOC_CFG,
1004 .buswidth = 4,
1005 .mas_rpm_id = -1,
1006 .slv_rpm_id = 70,
1007 .qos.ap_owned = true,
1008 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1009 };
1010
1011 static struct qcom_icc_node slv_qm_cfg = {
1012 .name = "slv_qm_cfg",
1013 .id = SDM660_SLAVE_QM_CFG,
1014 .buswidth = 4,
1015 .mas_rpm_id = -1,
1016 .slv_rpm_id = 212,
1017 .qos.ap_owned = true,
1018 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1019 };
1020
1021 static struct qcom_icc_node slv_clk_ctl = {
1022 .name = "slv_clk_ctl",
1023 .id = SDM660_SLAVE_CLK_CTL,
1024 .buswidth = 4,
1025 .mas_rpm_id = -1,
1026 .slv_rpm_id = 47,
1027 .qos.ap_owned = true,
1028 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1029 };
1030
1031 static struct qcom_icc_node slv_mss_cfg = {
1032 .name = "slv_mss_cfg",
1033 .id = SDM660_SLAVE_MSS_CFG,
1034 .buswidth = 4,
1035 .mas_rpm_id = -1,
1036 .slv_rpm_id = 48,
1037 .qos.ap_owned = true,
1038 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1039 };
1040
1041 static struct qcom_icc_node slv_tlmm_south = {
1042 .name = "slv_tlmm_south",
1043 .id = SDM660_SLAVE_TLMM_SOUTH,
1044 .buswidth = 4,
1045 .mas_rpm_id = -1,
1046 .slv_rpm_id = 217,
1047 .qos.ap_owned = true,
1048 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1049 };
1050
1051 static struct qcom_icc_node slv_ufs_cfg = {
1052 .name = "slv_ufs_cfg",
1053 .id = SDM660_SLAVE_UFS_CFG,
1054 .buswidth = 4,
1055 .mas_rpm_id = -1,
1056 .slv_rpm_id = 92,
1057 .qos.ap_owned = true,
1058 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1059 };
1060
1061 static struct qcom_icc_node slv_a2noc_cfg = {
1062 .name = "slv_a2noc_cfg",
1063 .id = SDM660_SLAVE_A2NOC_CFG,
1064 .buswidth = 4,
1065 .mas_rpm_id = -1,
1066 .slv_rpm_id = 150,
1067 .qos.ap_owned = true,
1068 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1069 };
1070
1071 static struct qcom_icc_node slv_a2noc_smmu_cfg = {
1072 .name = "slv_a2noc_smmu_cfg",
1073 .id = SDM660_SLAVE_A2NOC_SMMU_CFG,
1074 .buswidth = 8,
1075 .mas_rpm_id = -1,
1076 .slv_rpm_id = 152,
1077 .qos.ap_owned = true,
1078 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1079 };
1080
1081 static struct qcom_icc_node slv_gpuss_cfg = {
1082 .name = "slv_gpuss_cfg",
1083 .id = SDM660_SLAVE_GPUSS_CFG,
1084 .buswidth = 8,
1085 .mas_rpm_id = -1,
1086 .slv_rpm_id = 11,
1087 .qos.ap_owned = true,
1088 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1089 };
1090
1091 static struct qcom_icc_node slv_ahb2phy = {
1092 .name = "slv_ahb2phy",
1093 .id = SDM660_SLAVE_AHB2PHY,
1094 .buswidth = 4,
1095 .mas_rpm_id = -1,
1096 .slv_rpm_id = 163,
1097 .qos.ap_owned = true,
1098 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1099 };
1100
1101 static struct qcom_icc_node slv_blsp_1 = {
1102 .name = "slv_blsp_1",
1103 .id = SDM660_SLAVE_BLSP_1,
1104 .buswidth = 4,
1105 .mas_rpm_id = -1,
1106 .slv_rpm_id = 39,
1107 .qos.ap_owned = true,
1108 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1109 };
1110
1111 static struct qcom_icc_node slv_sdcc_1 = {
1112 .name = "slv_sdcc_1",
1113 .id = SDM660_SLAVE_SDCC_1,
1114 .buswidth = 4,
1115 .mas_rpm_id = -1,
1116 .slv_rpm_id = 31,
1117 .qos.ap_owned = true,
1118 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1119 };
1120
1121 static struct qcom_icc_node slv_sdcc_2 = {
1122 .name = "slv_sdcc_2",
1123 .id = SDM660_SLAVE_SDCC_2,
1124 .buswidth = 4,
1125 .mas_rpm_id = -1,
1126 .slv_rpm_id = 33,
1127 .qos.ap_owned = true,
1128 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1129 };
1130
1131 static struct qcom_icc_node slv_tlmm_center = {
1132 .name = "slv_tlmm_center",
1133 .id = SDM660_SLAVE_TLMM_CENTER,
1134 .buswidth = 4,
1135 .mas_rpm_id = -1,
1136 .slv_rpm_id = 218,
1137 .qos.ap_owned = true,
1138 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1139 };
1140
1141 static struct qcom_icc_node slv_blsp_2 = {
1142 .name = "slv_blsp_2",
1143 .id = SDM660_SLAVE_BLSP_2,
1144 .buswidth = 4,
1145 .mas_rpm_id = -1,
1146 .slv_rpm_id = 37,
1147 .qos.ap_owned = true,
1148 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1149 };
1150
1151 static struct qcom_icc_node slv_pdm = {
1152 .name = "slv_pdm",
1153 .id = SDM660_SLAVE_PDM,
1154 .buswidth = 4,
1155 .mas_rpm_id = -1,
1156 .slv_rpm_id = 41,
1157 .qos.ap_owned = true,
1158 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1159 };
1160
1161 static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = {
1162 SDM660_MASTER_CNOC_MNOC_MMSS_CFG
1163 };
1164
1165 static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = {
1166 .name = "slv_cnoc_mnoc_mmss_cfg",
1167 .id = SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
1168 .buswidth = 8,
1169 .mas_rpm_id = -1,
1170 .slv_rpm_id = 58,
1171 .qos.ap_owned = true,
1172 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1173 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links),
1174 .links = slv_cnoc_mnoc_mmss_cfg_links,
1175 };
1176
1177 static struct qcom_icc_node slv_usb_hs = {
1178 .name = "slv_usb_hs",
1179 .id = SDM660_SLAVE_USB_HS,
1180 .buswidth = 4,
1181 .mas_rpm_id = -1,
1182 .slv_rpm_id = 40,
1183 .qos.ap_owned = true,
1184 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1185 };
1186
1187 static struct qcom_icc_node slv_usb3_0 = {
1188 .name = "slv_usb3_0",
1189 .id = SDM660_SLAVE_USB3_0,
1190 .buswidth = 4,
1191 .mas_rpm_id = -1,
1192 .slv_rpm_id = 22,
1193 .qos.ap_owned = true,
1194 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1195 };
1196
1197 static struct qcom_icc_node slv_srvc_cnoc = {
1198 .name = "slv_srvc_cnoc",
1199 .id = SDM660_SLAVE_SRVC_CNOC,
1200 .buswidth = 4,
1201 .mas_rpm_id = -1,
1202 .slv_rpm_id = 76,
1203 .qos.ap_owned = true,
1204 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1205 };
1206
1207 static const u16 slv_gnoc_bimc_links[] = {
1208 SDM660_MASTER_GNOC_BIMC
1209 };
1210
1211 static struct qcom_icc_node slv_gnoc_bimc = {
1212 .name = "slv_gnoc_bimc",
1213 .id = SDM660_SLAVE_GNOC_BIMC,
1214 .buswidth = 16,
1215 .mas_rpm_id = -1,
1216 .slv_rpm_id = 210,
1217 .qos.ap_owned = true,
1218 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1219 .num_links = ARRAY_SIZE(slv_gnoc_bimc_links),
1220 .links = slv_gnoc_bimc_links,
1221 };
1222
1223 static const u16 slv_gnoc_snoc_links[] = {
1224 SDM660_MASTER_GNOC_SNOC
1225 };
1226
1227 static struct qcom_icc_node slv_gnoc_snoc = {
1228 .name = "slv_gnoc_snoc",
1229 .id = SDM660_SLAVE_GNOC_SNOC,
1230 .buswidth = 8,
1231 .mas_rpm_id = -1,
1232 .slv_rpm_id = 211,
1233 .qos.ap_owned = true,
1234 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1235 .num_links = ARRAY_SIZE(slv_gnoc_snoc_links),
1236 .links = slv_gnoc_snoc_links,
1237 };
1238
1239 static struct qcom_icc_node slv_camera_cfg = {
1240 .name = "slv_camera_cfg",
1241 .id = SDM660_SLAVE_CAMERA_CFG,
1242 .buswidth = 4,
1243 .mas_rpm_id = -1,
1244 .slv_rpm_id = 3,
1245 .qos.ap_owned = true,
1246 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1247 };
1248
1249 static struct qcom_icc_node slv_camera_throttle_cfg = {
1250 .name = "slv_camera_throttle_cfg",
1251 .id = SDM660_SLAVE_CAMERA_THROTTLE_CFG,
1252 .buswidth = 4,
1253 .mas_rpm_id = -1,
1254 .slv_rpm_id = 154,
1255 .qos.ap_owned = true,
1256 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1257 };
1258
1259 static struct qcom_icc_node slv_misc_cfg = {
1260 .name = "slv_misc_cfg",
1261 .id = SDM660_SLAVE_MISC_CFG,
1262 .buswidth = 4,
1263 .mas_rpm_id = -1,
1264 .slv_rpm_id = 8,
1265 .qos.ap_owned = true,
1266 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1267 };
1268
1269 static struct qcom_icc_node slv_venus_throttle_cfg = {
1270 .name = "slv_venus_throttle_cfg",
1271 .id = SDM660_SLAVE_VENUS_THROTTLE_CFG,
1272 .buswidth = 4,
1273 .mas_rpm_id = -1,
1274 .slv_rpm_id = 178,
1275 .qos.ap_owned = true,
1276 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1277 };
1278
1279 static struct qcom_icc_node slv_venus_cfg = {
1280 .name = "slv_venus_cfg",
1281 .id = SDM660_SLAVE_VENUS_CFG,
1282 .buswidth = 4,
1283 .mas_rpm_id = -1,
1284 .slv_rpm_id = 10,
1285 .qos.ap_owned = true,
1286 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1287 };
1288
1289 static struct qcom_icc_node slv_mmss_clk_xpu_cfg = {
1290 .name = "slv_mmss_clk_xpu_cfg",
1291 .id = SDM660_SLAVE_MMSS_CLK_XPU_CFG,
1292 .buswidth = 4,
1293 .mas_rpm_id = -1,
1294 .slv_rpm_id = 13,
1295 .qos.ap_owned = true,
1296 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1297 };
1298
1299 static struct qcom_icc_node slv_mmss_clk_cfg = {
1300 .name = "slv_mmss_clk_cfg",
1301 .id = SDM660_SLAVE_MMSS_CLK_CFG,
1302 .buswidth = 4,
1303 .mas_rpm_id = -1,
1304 .slv_rpm_id = 12,
1305 .qos.ap_owned = true,
1306 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1307 };
1308
1309 static struct qcom_icc_node slv_mnoc_mpu_cfg = {
1310 .name = "slv_mnoc_mpu_cfg",
1311 .id = SDM660_SLAVE_MNOC_MPU_CFG,
1312 .buswidth = 4,
1313 .mas_rpm_id = -1,
1314 .slv_rpm_id = 14,
1315 .qos.ap_owned = true,
1316 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1317 };
1318
1319 static struct qcom_icc_node slv_display_cfg = {
1320 .name = "slv_display_cfg",
1321 .id = SDM660_SLAVE_DISPLAY_CFG,
1322 .buswidth = 4,
1323 .mas_rpm_id = -1,
1324 .slv_rpm_id = 4,
1325 .qos.ap_owned = true,
1326 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1327 };
1328
1329 static struct qcom_icc_node slv_csi_phy_cfg = {
1330 .name = "slv_csi_phy_cfg",
1331 .id = SDM660_SLAVE_CSI_PHY_CFG,
1332 .buswidth = 4,
1333 .mas_rpm_id = -1,
1334 .slv_rpm_id = 224,
1335 .qos.ap_owned = true,
1336 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1337 };
1338
1339 static struct qcom_icc_node slv_display_throttle_cfg = {
1340 .name = "slv_display_throttle_cfg",
1341 .id = SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
1342 .buswidth = 4,
1343 .mas_rpm_id = -1,
1344 .slv_rpm_id = 156,
1345 .qos.ap_owned = true,
1346 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1347 };
1348
1349 static struct qcom_icc_node slv_smmu_cfg = {
1350 .name = "slv_smmu_cfg",
1351 .id = SDM660_SLAVE_SMMU_CFG,
1352 .buswidth = 8,
1353 .mas_rpm_id = -1,
1354 .slv_rpm_id = 205,
1355 .qos.ap_owned = true,
1356 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1357 };
1358
1359 static const u16 slv_mnoc_bimc_links[] = {
1360 SDM660_MASTER_MNOC_BIMC
1361 };
1362
1363 static struct qcom_icc_node slv_mnoc_bimc = {
1364 .name = "slv_mnoc_bimc",
1365 .id = SDM660_SLAVE_MNOC_BIMC,
1366 .buswidth = 16,
1367 .mas_rpm_id = -1,
1368 .slv_rpm_id = 16,
1369 .qos.ap_owned = true,
1370 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1371 .num_links = ARRAY_SIZE(slv_mnoc_bimc_links),
1372 .links = slv_mnoc_bimc_links,
1373 };
1374
1375 static struct qcom_icc_node slv_srvc_mnoc = {
1376 .name = "slv_srvc_mnoc",
1377 .id = SDM660_SLAVE_SRVC_MNOC,
1378 .buswidth = 8,
1379 .mas_rpm_id = -1,
1380 .slv_rpm_id = 17,
1381 .qos.ap_owned = true,
1382 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1383 };
1384
1385 static struct qcom_icc_node slv_hmss = {
1386 .name = "slv_hmss",
1387 .id = SDM660_SLAVE_HMSS,
1388 .buswidth = 8,
1389 .mas_rpm_id = -1,
1390 .slv_rpm_id = 20,
1391 .qos.ap_owned = true,
1392 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1393 };
1394
1395 static struct qcom_icc_node slv_lpass = {
1396 .name = "slv_lpass",
1397 .id = SDM660_SLAVE_LPASS,
1398 .buswidth = 4,
1399 .mas_rpm_id = -1,
1400 .slv_rpm_id = 21,
1401 .qos.ap_owned = true,
1402 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1403 };
1404
1405 static struct qcom_icc_node slv_wlan = {
1406 .name = "slv_wlan",
1407 .id = SDM660_SLAVE_WLAN,
1408 .buswidth = 4,
1409 .mas_rpm_id = -1,
1410 .slv_rpm_id = 206,
1411 };
1412
1413 static struct qcom_icc_node slv_cdsp = {
1414 .name = "slv_cdsp",
1415 .id = SDM660_SLAVE_CDSP,
1416 .buswidth = 4,
1417 .mas_rpm_id = -1,
1418 .slv_rpm_id = 221,
1419 .qos.ap_owned = true,
1420 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1421 };
1422
1423 static struct qcom_icc_node slv_ipa = {
1424 .name = "slv_ipa",
1425 .id = SDM660_SLAVE_IPA,
1426 .buswidth = 4,
1427 .mas_rpm_id = -1,
1428 .slv_rpm_id = 183,
1429 .qos.ap_owned = true,
1430 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1431 };
1432
1433 static const u16 slv_snoc_bimc_links[] = {
1434 SDM660_MASTER_SNOC_BIMC
1435 };
1436
1437 static struct qcom_icc_node slv_snoc_bimc = {
1438 .name = "slv_snoc_bimc",
1439 .id = SDM660_SLAVE_SNOC_BIMC,
1440 .buswidth = 16,
1441 .mas_rpm_id = -1,
1442 .slv_rpm_id = 24,
1443 .num_links = ARRAY_SIZE(slv_snoc_bimc_links),
1444 .links = slv_snoc_bimc_links,
1445 };
1446
1447 static const u16 slv_snoc_cnoc_links[] = {
1448 SDM660_MASTER_SNOC_CNOC
1449 };
1450
1451 static struct qcom_icc_node slv_snoc_cnoc = {
1452 .name = "slv_snoc_cnoc",
1453 .id = SDM660_SLAVE_SNOC_CNOC,
1454 .buswidth = 8,
1455 .mas_rpm_id = -1,
1456 .slv_rpm_id = 25,
1457 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links),
1458 .links = slv_snoc_cnoc_links,
1459 };
1460
1461 static struct qcom_icc_node slv_imem = {
1462 .name = "slv_imem",
1463 .id = SDM660_SLAVE_IMEM,
1464 .buswidth = 8,
1465 .mas_rpm_id = -1,
1466 .slv_rpm_id = 26,
1467 };
1468
1469 static struct qcom_icc_node slv_pimem = {
1470 .name = "slv_pimem",
1471 .id = SDM660_SLAVE_PIMEM,
1472 .buswidth = 8,
1473 .mas_rpm_id = -1,
1474 .slv_rpm_id = 166,
1475 };
1476
1477 static struct qcom_icc_node slv_qdss_stm = {
1478 .name = "slv_qdss_stm",
1479 .id = SDM660_SLAVE_QDSS_STM,
1480 .buswidth = 4,
1481 .mas_rpm_id = -1,
1482 .slv_rpm_id = 30,
1483 };
1484
1485 static struct qcom_icc_node slv_srvc_snoc = {
1486 .name = "slv_srvc_snoc",
1487 .id = SDM660_SLAVE_SRVC_SNOC,
1488 .buswidth = 16,
1489 .mas_rpm_id = -1,
1490 .slv_rpm_id = 29,
1491 };
1492
1493 static struct qcom_icc_node * const sdm660_a2noc_nodes[] = {
1494 [MASTER_IPA] = &mas_ipa,
1495 [MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc,
1496 [MASTER_SDCC_1] = &mas_sdcc_1,
1497 [MASTER_SDCC_2] = &mas_sdcc_2,
1498 [MASTER_BLSP_1] = &mas_blsp_1,
1499 [MASTER_BLSP_2] = &mas_blsp_2,
1500 [MASTER_UFS] = &mas_ufs,
1501 [MASTER_USB_HS] = &mas_usb_hs,
1502 [MASTER_USB3] = &mas_usb3,
1503 [MASTER_CRYPTO_C0] = &mas_crypto,
1504 [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
1505 };
1506
1507 static const struct regmap_config sdm660_a2noc_regmap_config = {
1508 .reg_bits = 32,
1509 .reg_stride = 4,
1510 .val_bits = 32,
1511 .max_register = 0x20000,
1512 .fast_io = true,
1513 };
1514
1515 static const struct qcom_icc_desc sdm660_a2noc = {
1516 .type = QCOM_ICC_NOC,
1517 .nodes = sdm660_a2noc_nodes,
1518 .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes),
1519 .clocks = bus_a2noc_clocks,
1520 .num_clocks = ARRAY_SIZE(bus_a2noc_clocks),
1521 .regmap_cfg = &sdm660_a2noc_regmap_config,
1522 };
1523
1524 static struct qcom_icc_node * const sdm660_bimc_nodes[] = {
1525 [MASTER_GNOC_BIMC] = &mas_gnoc_bimc,
1526 [MASTER_OXILI] = &mas_oxili,
1527 [MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
1528 [MASTER_SNOC_BIMC] = &mas_snoc_bimc,
1529 [MASTER_PIMEM] = &mas_pimem,
1530 [SLAVE_EBI] = &slv_ebi,
1531 [SLAVE_HMSS_L3] = &slv_hmss_l3,
1532 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
1533 };
1534
1535 static const struct regmap_config sdm660_bimc_regmap_config = {
1536 .reg_bits = 32,
1537 .reg_stride = 4,
1538 .val_bits = 32,
1539 .max_register = 0x80000,
1540 .fast_io = true,
1541 };
1542
1543 static const struct qcom_icc_desc sdm660_bimc = {
1544 .type = QCOM_ICC_BIMC,
1545 .nodes = sdm660_bimc_nodes,
1546 .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes),
1547 .regmap_cfg = &sdm660_bimc_regmap_config,
1548 };
1549
1550 static struct qcom_icc_node * const sdm660_cnoc_nodes[] = {
1551 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
1552 [MASTER_QDSS_DAP] = &mas_qdss_dap,
1553 [SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc,
1554 [SLAVE_MPM] = &slv_mpm,
1555 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1556 [SLAVE_TLMM_NORTH] = &slv_tlmm_north,
1557 [SLAVE_TCSR] = &slv_tcsr,
1558 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
1559 [SLAVE_IMEM_CFG] = &slv_imem_cfg,
1560 [SLAVE_MESSAGE_RAM] = &slv_message_ram,
1561 [SLAVE_GLM] = &slv_glm,
1562 [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1563 [SLAVE_PRNG] = &slv_prng,
1564 [SLAVE_SPDM] = &slv_spdm,
1565 [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1566 [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
1567 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1568 [SLAVE_QM_CFG] = &slv_qm_cfg,
1569 [SLAVE_CLK_CTL] = &slv_clk_ctl,
1570 [SLAVE_MSS_CFG] = &slv_mss_cfg,
1571 [SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
1572 [SLAVE_UFS_CFG] = &slv_ufs_cfg,
1573 [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
1574 [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
1575 [SLAVE_GPUSS_CFG] = &slv_gpuss_cfg,
1576 [SLAVE_AHB2PHY] = &slv_ahb2phy,
1577 [SLAVE_BLSP_1] = &slv_blsp_1,
1578 [SLAVE_SDCC_1] = &slv_sdcc_1,
1579 [SLAVE_SDCC_2] = &slv_sdcc_2,
1580 [SLAVE_TLMM_CENTER] = &slv_tlmm_center,
1581 [SLAVE_BLSP_2] = &slv_blsp_2,
1582 [SLAVE_PDM] = &slv_pdm,
1583 [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg,
1584 [SLAVE_USB_HS] = &slv_usb_hs,
1585 [SLAVE_USB3_0] = &slv_usb3_0,
1586 [SLAVE_SRVC_CNOC] = &slv_srvc_cnoc,
1587 };
1588
1589 static const struct regmap_config sdm660_cnoc_regmap_config = {
1590 .reg_bits = 32,
1591 .reg_stride = 4,
1592 .val_bits = 32,
1593 .max_register = 0x10000,
1594 .fast_io = true,
1595 };
1596
1597 static const struct qcom_icc_desc sdm660_cnoc = {
1598 .type = QCOM_ICC_NOC,
1599 .nodes = sdm660_cnoc_nodes,
1600 .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes),
1601 .regmap_cfg = &sdm660_cnoc_regmap_config,
1602 };
1603
1604 static struct qcom_icc_node * const sdm660_gnoc_nodes[] = {
1605 [MASTER_APSS_PROC] = &mas_apss_proc,
1606 [SLAVE_GNOC_BIMC] = &slv_gnoc_bimc,
1607 [SLAVE_GNOC_SNOC] = &slv_gnoc_snoc,
1608 };
1609
1610 static const struct regmap_config sdm660_gnoc_regmap_config = {
1611 .reg_bits = 32,
1612 .reg_stride = 4,
1613 .val_bits = 32,
1614 .max_register = 0xe000,
1615 .fast_io = true,
1616 };
1617
1618 static const struct qcom_icc_desc sdm660_gnoc = {
1619 .type = QCOM_ICC_NOC,
1620 .nodes = sdm660_gnoc_nodes,
1621 .num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
1622 .regmap_cfg = &sdm660_gnoc_regmap_config,
1623 };
1624
1625 static struct qcom_icc_node * const sdm660_mnoc_nodes[] = {
1626 [MASTER_CPP] = &mas_cpp,
1627 [MASTER_JPEG] = &mas_jpeg,
1628 [MASTER_MDP_P0] = &mas_mdp_p0,
1629 [MASTER_MDP_P1] = &mas_mdp_p1,
1630 [MASTER_VENUS] = &mas_venus,
1631 [MASTER_VFE] = &mas_vfe,
1632 [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
1633 [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
1634 [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1635 [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
1636 [SLAVE_MISC_CFG] = &slv_misc_cfg,
1637 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
1638 [SLAVE_VENUS_CFG] = &slv_venus_cfg,
1639 [SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg,
1640 [SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg,
1641 [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
1642 [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1643 [SLAVE_CSI_PHY_CFG] = &slv_csi_phy_cfg,
1644 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
1645 [SLAVE_SMMU_CFG] = &slv_smmu_cfg,
1646 [SLAVE_SRVC_MNOC] = &slv_srvc_mnoc,
1647 [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
1648 };
1649
1650 static const struct regmap_config sdm660_mnoc_regmap_config = {
1651 .reg_bits = 32,
1652 .reg_stride = 4,
1653 .val_bits = 32,
1654 .max_register = 0x10000,
1655 .fast_io = true,
1656 };
1657
1658 static const struct qcom_icc_desc sdm660_mnoc = {
1659 .type = QCOM_ICC_NOC,
1660 .nodes = sdm660_mnoc_nodes,
1661 .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes),
1662 .clocks = bus_mm_clocks,
1663 .num_clocks = ARRAY_SIZE(bus_mm_clocks),
1664 .regmap_cfg = &sdm660_mnoc_regmap_config,
1665 };
1666
1667 static struct qcom_icc_node * const sdm660_snoc_nodes[] = {
1668 [MASTER_QDSS_ETR] = &mas_qdss_etr,
1669 [MASTER_QDSS_BAM] = &mas_qdss_bam,
1670 [MASTER_SNOC_CFG] = &mas_snoc_cfg,
1671 [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
1672 [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
1673 [MASTER_GNOC_SNOC] = &mas_gnoc_snoc,
1674 [SLAVE_HMSS] = &slv_hmss,
1675 [SLAVE_LPASS] = &slv_lpass,
1676 [SLAVE_WLAN] = &slv_wlan,
1677 [SLAVE_CDSP] = &slv_cdsp,
1678 [SLAVE_IPA] = &slv_ipa,
1679 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
1680 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
1681 [SLAVE_IMEM] = &slv_imem,
1682 [SLAVE_PIMEM] = &slv_pimem,
1683 [SLAVE_QDSS_STM] = &slv_qdss_stm,
1684 [SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
1685 };
1686
1687 static const struct regmap_config sdm660_snoc_regmap_config = {
1688 .reg_bits = 32,
1689 .reg_stride = 4,
1690 .val_bits = 32,
1691 .max_register = 0x20000,
1692 .fast_io = true,
1693 };
1694
1695 static const struct qcom_icc_desc sdm660_snoc = {
1696 .type = QCOM_ICC_NOC,
1697 .nodes = sdm660_snoc_nodes,
1698 .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes),
1699 .regmap_cfg = &sdm660_snoc_regmap_config,
1700 };
1701
1702 static const struct of_device_id sdm660_noc_of_match[] = {
1703 { .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc },
1704 { .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc },
1705 { .compatible = "qcom,sdm660-cnoc", .data = &sdm660_cnoc },
1706 { .compatible = "qcom,sdm660-gnoc", .data = &sdm660_gnoc },
1707 { .compatible = "qcom,sdm660-mnoc", .data = &sdm660_mnoc },
1708 { .compatible = "qcom,sdm660-snoc", .data = &sdm660_snoc },
1709 { },
1710 };
1711 MODULE_DEVICE_TABLE(of, sdm660_noc_of_match);
1712
1713 static struct platform_driver sdm660_noc_driver = {
1714 .probe = qnoc_probe,
1715 .remove = qnoc_remove,
1716 .driver = {
1717 .name = "qnoc-sdm660",
1718 .of_match_table = sdm660_noc_of_match,
1719 },
1720 };
1721 module_platform_driver(sdm660_noc_driver);
1722 MODULE_DESCRIPTION("Qualcomm sdm660 NoC driver");
1723 MODULE_LICENSE("GPL v2");
