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0007 #include <linux/device.h>
0008 #include <linux/interconnect.h>
0009 #include <linux/interconnect-provider.h>
0010 #include <linux/module.h>
0011 #include <linux/of_platform.h>
0012 #include <dt-bindings/interconnect/qcom,sc7180.h>
0013
0014 #include "bcm-voter.h"
0015 #include "icc-rpmh.h"
0016 #include "sc7180.h"
0017
0018 DEFINE_QNODE(qhm_a1noc_cfg, SC7180_MASTER_A1NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A1NOC);
0019 DEFINE_QNODE(qhm_qspi, SC7180_MASTER_QSPI, 1, 4, SC7180_SLAVE_A1NOC_SNOC);
0020 DEFINE_QNODE(qhm_qup_0, SC7180_MASTER_QUP_0, 1, 4, SC7180_SLAVE_A1NOC_SNOC);
0021 DEFINE_QNODE(xm_sdc2, SC7180_MASTER_SDCC_2, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
0022 DEFINE_QNODE(xm_emmc, SC7180_MASTER_EMMC, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
0023 DEFINE_QNODE(xm_ufs_mem, SC7180_MASTER_UFS_MEM, 1, 8, SC7180_SLAVE_A1NOC_SNOC);
0024 DEFINE_QNODE(qhm_a2noc_cfg, SC7180_MASTER_A2NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A2NOC);
0025 DEFINE_QNODE(qhm_qdss_bam, SC7180_MASTER_QDSS_BAM, 1, 4, SC7180_SLAVE_A2NOC_SNOC);
0026 DEFINE_QNODE(qhm_qup_1, SC7180_MASTER_QUP_1, 1, 4, SC7180_SLAVE_A2NOC_SNOC);
0027 DEFINE_QNODE(qxm_crypto, SC7180_MASTER_CRYPTO, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
0028 DEFINE_QNODE(qxm_ipa, SC7180_MASTER_IPA, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
0029 DEFINE_QNODE(xm_qdss_etr, SC7180_MASTER_QDSS_ETR, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
0030 DEFINE_QNODE(qhm_usb3, SC7180_MASTER_USB3, 1, 8, SC7180_SLAVE_A2NOC_SNOC);
0031 DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SC7180_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
0032 DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SC7180_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
0033 DEFINE_QNODE(qxm_camnoc_sf_uncomp, SC7180_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP);
0034 DEFINE_QNODE(qnm_npu, SC7180_MASTER_NPU, 2, 32, SC7180_SLAVE_CDSP_GEM_NOC);
0035 DEFINE_QNODE(qxm_npu_dsp, SC7180_MASTER_NPU_PROC, 1, 8, SC7180_SLAVE_CDSP_GEM_NOC);
0036 DEFINE_QNODE(qnm_snoc, SC7180_MASTER_SNOC_CNOC, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM,
0037 SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG, SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC);
0038 DEFINE_QNODE(xm_qdss_dap, SC7180_MASTER_QDSS_DAP, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM, SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG,
0039 SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC);
0040 DEFINE_QNODE(qhm_cnoc_dc_noc, SC7180_MASTER_CNOC_DC_NOC, 1, 4, SC7180_SLAVE_GEM_NOC_CFG, SC7180_SLAVE_LLCC_CFG);
0041 DEFINE_QNODE(acm_apps0, SC7180_MASTER_APPSS_PROC, 1, 16, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
0042 DEFINE_QNODE(acm_sys_tcu, SC7180_MASTER_SYS_TCU, 1, 8, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
0043 DEFINE_QNODE(qhm_gemnoc_cfg, SC7180_MASTER_GEM_NOC_CFG, 1, 4, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, SC7180_SLAVE_SERVICE_GEM_NOC);
0044 DEFINE_QNODE(qnm_cmpnoc, SC7180_MASTER_COMPUTE_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
0045 DEFINE_QNODE(qnm_mnoc_hf, SC7180_MASTER_MNOC_HF_MEM_NOC, 1, 32, SC7180_SLAVE_LLCC);
0046 DEFINE_QNODE(qnm_mnoc_sf, SC7180_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
0047 DEFINE_QNODE(qnm_snoc_gc, SC7180_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC7180_SLAVE_LLCC);
0048 DEFINE_QNODE(qnm_snoc_sf, SC7180_MASTER_SNOC_SF_MEM_NOC, 1, 16, SC7180_SLAVE_LLCC);
0049 DEFINE_QNODE(qxm_gpu, SC7180_MASTER_GFX3D, 2, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
0050 DEFINE_QNODE(llcc_mc, SC7180_MASTER_LLCC, 2, 4, SC7180_SLAVE_EBI1);
0051 DEFINE_QNODE(qhm_mnoc_cfg, SC7180_MASTER_CNOC_MNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_MNOC);
0052 DEFINE_QNODE(qxm_camnoc_hf0, SC7180_MASTER_CAMNOC_HF0, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
0053 DEFINE_QNODE(qxm_camnoc_hf1, SC7180_MASTER_CAMNOC_HF1, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
0054 DEFINE_QNODE(qxm_camnoc_sf, SC7180_MASTER_CAMNOC_SF, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC);
0055 DEFINE_QNODE(qxm_mdp0, SC7180_MASTER_MDP0, 1, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
0056 DEFINE_QNODE(qxm_rot, SC7180_MASTER_ROTATOR, 1, 16, SC7180_SLAVE_MNOC_SF_MEM_NOC);
0057 DEFINE_QNODE(qxm_venus0, SC7180_MASTER_VIDEO_P0, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC);
0058 DEFINE_QNODE(qxm_venus_arm9, SC7180_MASTER_VIDEO_PROC, 1, 8, SC7180_SLAVE_MNOC_SF_MEM_NOC);
0059 DEFINE_QNODE(amm_npu_sys, SC7180_MASTER_NPU_SYS, 2, 32, SC7180_SLAVE_NPU_COMPUTE_NOC);
0060 DEFINE_QNODE(qhm_npu_cfg, SC7180_MASTER_NPU_NOC_CFG, 1, 4, SC7180_SLAVE_NPU_CAL_DP0, SC7180_SLAVE_NPU_CP, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, SC7180_SLAVE_NPU_DPM, SC7180_SLAVE_ISENSE_CFG, SC7180_SLAVE_NPU_LLM_CFG, SC7180_SLAVE_NPU_TCM, SC7180_SLAVE_SERVICE_NPU_NOC);
0061 DEFINE_QNODE(qup_core_master_1, SC7180_MASTER_QUP_CORE_0, 1, 4, SC7180_SLAVE_QUP_CORE_0);
0062 DEFINE_QNODE(qup_core_master_2, SC7180_MASTER_QUP_CORE_1, 1, 4, SC7180_SLAVE_QUP_CORE_1);
0063 DEFINE_QNODE(qhm_snoc_cfg, SC7180_MASTER_SNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_SNOC);
0064 DEFINE_QNODE(qnm_aggre1_noc, SC7180_MASTER_A1NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM);
0065 DEFINE_QNODE(qnm_aggre2_noc, SC7180_MASTER_A2NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU);
0066 DEFINE_QNODE(qnm_gemnoc, SC7180_MASTER_GEM_NOC_SNOC, 1, 8, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU);
0067 DEFINE_QNODE(qxm_pimem, SC7180_MASTER_PIMEM, 1, 8, SC7180_SLAVE_SNOC_GEM_NOC_GC, SC7180_SLAVE_IMEM);
0068 DEFINE_QNODE(qns_a1noc_snoc, SC7180_SLAVE_A1NOC_SNOC, 1, 16, SC7180_MASTER_A1NOC_SNOC);
0069 DEFINE_QNODE(srvc_aggre1_noc, SC7180_SLAVE_SERVICE_A1NOC, 1, 4);
0070 DEFINE_QNODE(qns_a2noc_snoc, SC7180_SLAVE_A2NOC_SNOC, 1, 16, SC7180_MASTER_A2NOC_SNOC);
0071 DEFINE_QNODE(srvc_aggre2_noc, SC7180_SLAVE_SERVICE_A2NOC, 1, 4);
0072 DEFINE_QNODE(qns_camnoc_uncomp, SC7180_SLAVE_CAMNOC_UNCOMP, 1, 32);
0073 DEFINE_QNODE(qns_cdsp_gemnoc, SC7180_SLAVE_CDSP_GEM_NOC, 1, 32, SC7180_MASTER_COMPUTE_NOC);
0074 DEFINE_QNODE(qhs_a1_noc_cfg, SC7180_SLAVE_A1NOC_CFG, 1, 4, SC7180_MASTER_A1NOC_CFG);
0075 DEFINE_QNODE(qhs_a2_noc_cfg, SC7180_SLAVE_A2NOC_CFG, 1, 4, SC7180_MASTER_A2NOC_CFG);
0076 DEFINE_QNODE(qhs_ahb2phy0, SC7180_SLAVE_AHB2PHY_SOUTH, 1, 4);
0077 DEFINE_QNODE(qhs_ahb2phy2, SC7180_SLAVE_AHB2PHY_CENTER, 1, 4);
0078 DEFINE_QNODE(qhs_aop, SC7180_SLAVE_AOP, 1, 4);
0079 DEFINE_QNODE(qhs_aoss, SC7180_SLAVE_AOSS, 1, 4);
0080 DEFINE_QNODE(qhs_boot_rom, SC7180_SLAVE_BOOT_ROM, 1, 4);
0081 DEFINE_QNODE(qhs_camera_cfg, SC7180_SLAVE_CAMERA_CFG, 1, 4);
0082 DEFINE_QNODE(qhs_camera_nrt_throttle_cfg, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4);
0083 DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4);
0084 DEFINE_QNODE(qhs_clk_ctl, SC7180_SLAVE_CLK_CTL, 1, 4);
0085 DEFINE_QNODE(qhs_cpr_cx, SC7180_SLAVE_RBCPR_CX_CFG, 1, 4);
0086 DEFINE_QNODE(qhs_cpr_mx, SC7180_SLAVE_RBCPR_MX_CFG, 1, 4);
0087 DEFINE_QNODE(qhs_crypto0_cfg, SC7180_SLAVE_CRYPTO_0_CFG, 1, 4);
0088 DEFINE_QNODE(qhs_dcc_cfg, SC7180_SLAVE_DCC_CFG, 1, 4);
0089 DEFINE_QNODE(qhs_ddrss_cfg, SC7180_SLAVE_CNOC_DDRSS, 1, 4, SC7180_MASTER_CNOC_DC_NOC);
0090 DEFINE_QNODE(qhs_display_cfg, SC7180_SLAVE_DISPLAY_CFG, 1, 4);
0091 DEFINE_QNODE(qhs_display_rt_throttle_cfg, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, 1, 4);
0092 DEFINE_QNODE(qhs_display_throttle_cfg, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4);
0093 DEFINE_QNODE(qhs_emmc_cfg, SC7180_SLAVE_EMMC_CFG, 1, 4);
0094 DEFINE_QNODE(qhs_glm, SC7180_SLAVE_GLM, 1, 4);
0095 DEFINE_QNODE(qhs_gpuss_cfg, SC7180_SLAVE_GFX3D_CFG, 1, 8);
0096 DEFINE_QNODE(qhs_imem_cfg, SC7180_SLAVE_IMEM_CFG, 1, 4);
0097 DEFINE_QNODE(qhs_ipa, SC7180_SLAVE_IPA_CFG, 1, 4);
0098 DEFINE_QNODE(qhs_mnoc_cfg, SC7180_SLAVE_CNOC_MNOC_CFG, 1, 4, SC7180_MASTER_CNOC_MNOC_CFG);
0099 DEFINE_QNODE(qhs_mss_cfg, SC7180_SLAVE_CNOC_MSS, 1, 4);
0100 DEFINE_QNODE(qhs_npu_cfg, SC7180_SLAVE_NPU_CFG, 1, 4, SC7180_MASTER_NPU_NOC_CFG);
0101 DEFINE_QNODE(qhs_npu_dma_throttle_cfg, SC7180_SLAVE_NPU_DMA_BWMON_CFG, 1, 4);
0102 DEFINE_QNODE(qhs_npu_dsp_throttle_cfg, SC7180_SLAVE_NPU_PROC_BWMON_CFG, 1, 4);
0103 DEFINE_QNODE(qhs_pdm, SC7180_SLAVE_PDM, 1, 4);
0104 DEFINE_QNODE(qhs_pimem_cfg, SC7180_SLAVE_PIMEM_CFG, 1, 4);
0105 DEFINE_QNODE(qhs_prng, SC7180_SLAVE_PRNG, 1, 4);
0106 DEFINE_QNODE(qhs_qdss_cfg, SC7180_SLAVE_QDSS_CFG, 1, 4);
0107 DEFINE_QNODE(qhs_qm_cfg, SC7180_SLAVE_QM_CFG, 1, 4);
0108 DEFINE_QNODE(qhs_qm_mpu_cfg, SC7180_SLAVE_QM_MPU_CFG, 1, 4);
0109 DEFINE_QNODE(qhs_qspi, SC7180_SLAVE_QSPI_0, 1, 4);
0110 DEFINE_QNODE(qhs_qup0, SC7180_SLAVE_QUP_0, 1, 4);
0111 DEFINE_QNODE(qhs_qup1, SC7180_SLAVE_QUP_1, 1, 4);
0112 DEFINE_QNODE(qhs_sdc2, SC7180_SLAVE_SDCC_2, 1, 4);
0113 DEFINE_QNODE(qhs_security, SC7180_SLAVE_SECURITY, 1, 4);
0114 DEFINE_QNODE(qhs_snoc_cfg, SC7180_SLAVE_SNOC_CFG, 1, 4, SC7180_MASTER_SNOC_CFG);
0115 DEFINE_QNODE(qhs_tcsr, SC7180_SLAVE_TCSR, 1, 4);
0116 DEFINE_QNODE(qhs_tlmm_1, SC7180_SLAVE_TLMM_WEST, 1, 4);
0117 DEFINE_QNODE(qhs_tlmm_2, SC7180_SLAVE_TLMM_NORTH, 1, 4);
0118 DEFINE_QNODE(qhs_tlmm_3, SC7180_SLAVE_TLMM_SOUTH, 1, 4);
0119 DEFINE_QNODE(qhs_ufs_mem_cfg, SC7180_SLAVE_UFS_MEM_CFG, 1, 4);
0120 DEFINE_QNODE(qhs_usb3, SC7180_SLAVE_USB3, 1, 4);
0121 DEFINE_QNODE(qhs_venus_cfg, SC7180_SLAVE_VENUS_CFG, 1, 4);
0122 DEFINE_QNODE(qhs_venus_throttle_cfg, SC7180_SLAVE_VENUS_THROTTLE_CFG, 1, 4);
0123 DEFINE_QNODE(qhs_vsense_ctrl_cfg, SC7180_SLAVE_VSENSE_CTRL_CFG, 1, 4);
0124 DEFINE_QNODE(srvc_cnoc, SC7180_SLAVE_SERVICE_CNOC, 1, 4);
0125 DEFINE_QNODE(qhs_gemnoc, SC7180_SLAVE_GEM_NOC_CFG, 1, 4, SC7180_MASTER_GEM_NOC_CFG);
0126 DEFINE_QNODE(qhs_llcc, SC7180_SLAVE_LLCC_CFG, 1, 4);
0127 DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
0128 DEFINE_QNODE(qns_gem_noc_snoc, SC7180_SLAVE_GEM_NOC_SNOC, 1, 8, SC7180_MASTER_GEM_NOC_SNOC);
0129 DEFINE_QNODE(qns_llcc, SC7180_SLAVE_LLCC, 1, 16, SC7180_MASTER_LLCC);
0130 DEFINE_QNODE(srvc_gemnoc, SC7180_SLAVE_SERVICE_GEM_NOC, 1, 4);
0131 DEFINE_QNODE(ebi, SC7180_SLAVE_EBI1, 2, 4);
0132 DEFINE_QNODE(qns_mem_noc_hf, SC7180_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_HF_MEM_NOC);
0133 DEFINE_QNODE(qns_mem_noc_sf, SC7180_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_SF_MEM_NOC);
0134 DEFINE_QNODE(srvc_mnoc, SC7180_SLAVE_SERVICE_MNOC, 1, 4);
0135 DEFINE_QNODE(qhs_cal_dp0, SC7180_SLAVE_NPU_CAL_DP0, 1, 4);
0136 DEFINE_QNODE(qhs_cp, SC7180_SLAVE_NPU_CP, 1, 4);
0137 DEFINE_QNODE(qhs_dma_bwmon, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
0138 DEFINE_QNODE(qhs_dpm, SC7180_SLAVE_NPU_DPM, 1, 4);
0139 DEFINE_QNODE(qhs_isense, SC7180_SLAVE_ISENSE_CFG, 1, 4);
0140 DEFINE_QNODE(qhs_llm, SC7180_SLAVE_NPU_LLM_CFG, 1, 4);
0141 DEFINE_QNODE(qhs_tcm, SC7180_SLAVE_NPU_TCM, 1, 4);
0142 DEFINE_QNODE(qns_npu_sys, SC7180_SLAVE_NPU_COMPUTE_NOC, 2, 32);
0143 DEFINE_QNODE(srvc_noc, SC7180_SLAVE_SERVICE_NPU_NOC, 1, 4);
0144 DEFINE_QNODE(qup_core_slave_1, SC7180_SLAVE_QUP_CORE_0, 1, 4);
0145 DEFINE_QNODE(qup_core_slave_2, SC7180_SLAVE_QUP_CORE_1, 1, 4);
0146 DEFINE_QNODE(qhs_apss, SC7180_SLAVE_APPSS, 1, 8);
0147 DEFINE_QNODE(qns_cnoc, SC7180_SLAVE_SNOC_CNOC, 1, 8, SC7180_MASTER_SNOC_CNOC);
0148 DEFINE_QNODE(qns_gemnoc_gc, SC7180_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SC7180_MASTER_SNOC_GC_MEM_NOC);
0149 DEFINE_QNODE(qns_gemnoc_sf, SC7180_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SC7180_MASTER_SNOC_SF_MEM_NOC);
0150 DEFINE_QNODE(qxs_imem, SC7180_SLAVE_IMEM, 1, 8);
0151 DEFINE_QNODE(qxs_pimem, SC7180_SLAVE_PIMEM, 1, 8);
0152 DEFINE_QNODE(srvc_snoc, SC7180_SLAVE_SERVICE_SNOC, 1, 4);
0153 DEFINE_QNODE(xs_qdss_stm, SC7180_SLAVE_QDSS_STM, 1, 4);
0154 DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8);
0155
0156 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
0157 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
0158 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
0159 DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
0160 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
0161 DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc);
0162 DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9);
0163 DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
0164 DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
0165 DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup_core_master_1, &qup_core_master_2);
0166 DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
0167 DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps0);
0168 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
0169 DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc);
0170 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
0171 DEFINE_QBCM(bcm_cn1, "CN1", false, &qhm_qspi, &xm_sdc2, &xm_emmc, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2);
0172 DEFINE_QBCM(bcm_sn2, "SN2", false, &qxm_pimem, &qns_gemnoc_gc);
0173 DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
0174 DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
0175 DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp);
0176 DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
0177 DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
0178 DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc);
0179 DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc);
0180
0181 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
0182 &bcm_cn1,
0183 };
0184
0185 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
0186 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
0187 [MASTER_QSPI] = &qhm_qspi,
0188 [MASTER_QUP_0] = &qhm_qup_0,
0189 [MASTER_SDCC_2] = &xm_sdc2,
0190 [MASTER_EMMC] = &xm_emmc,
0191 [MASTER_UFS_MEM] = &xm_ufs_mem,
0192 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
0193 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
0194 };
0195
0196 static const struct qcom_icc_desc sc7180_aggre1_noc = {
0197 .nodes = aggre1_noc_nodes,
0198 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
0199 .bcms = aggre1_noc_bcms,
0200 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
0201 };
0202
0203 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
0204 &bcm_ce0,
0205 };
0206
0207 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
0208 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
0209 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
0210 [MASTER_QUP_1] = &qhm_qup_1,
0211 [MASTER_USB3] = &qhm_usb3,
0212 [MASTER_CRYPTO] = &qxm_crypto,
0213 [MASTER_IPA] = &qxm_ipa,
0214 [MASTER_QDSS_ETR] = &xm_qdss_etr,
0215 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
0216 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
0217 };
0218
0219 static const struct qcom_icc_desc sc7180_aggre2_noc = {
0220 .nodes = aggre2_noc_nodes,
0221 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
0222 .bcms = aggre2_noc_bcms,
0223 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
0224 };
0225
0226 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
0227 &bcm_mm1,
0228 };
0229
0230 static struct qcom_icc_node * const camnoc_virt_nodes[] = {
0231 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
0232 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp,
0233 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
0234 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
0235 };
0236
0237 static const struct qcom_icc_desc sc7180_camnoc_virt = {
0238 .nodes = camnoc_virt_nodes,
0239 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
0240 .bcms = camnoc_virt_bcms,
0241 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
0242 };
0243
0244 static struct qcom_icc_bcm * const compute_noc_bcms[] = {
0245 &bcm_co0,
0246 &bcm_co2,
0247 &bcm_co3,
0248 };
0249
0250 static struct qcom_icc_node * const compute_noc_nodes[] = {
0251 [MASTER_NPU] = &qnm_npu,
0252 [MASTER_NPU_PROC] = &qxm_npu_dsp,
0253 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
0254 };
0255
0256 static const struct qcom_icc_desc sc7180_compute_noc = {
0257 .nodes = compute_noc_nodes,
0258 .num_nodes = ARRAY_SIZE(compute_noc_nodes),
0259 .bcms = compute_noc_bcms,
0260 .num_bcms = ARRAY_SIZE(compute_noc_bcms),
0261 };
0262
0263 static struct qcom_icc_bcm * const config_noc_bcms[] = {
0264 &bcm_cn0,
0265 &bcm_cn1,
0266 };
0267
0268 static struct qcom_icc_node * const config_noc_nodes[] = {
0269 [MASTER_SNOC_CNOC] = &qnm_snoc,
0270 [MASTER_QDSS_DAP] = &xm_qdss_dap,
0271 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
0272 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
0273 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
0274 [SLAVE_AHB2PHY_CENTER] = &qhs_ahb2phy2,
0275 [SLAVE_AOP] = &qhs_aop,
0276 [SLAVE_AOSS] = &qhs_aoss,
0277 [SLAVE_BOOT_ROM] = &qhs_boot_rom,
0278 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
0279 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
0280 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
0281 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
0282 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
0283 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
0284 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
0285 [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
0286 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
0287 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
0288 [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display_rt_throttle_cfg,
0289 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg,
0290 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
0291 [SLAVE_GLM] = &qhs_glm,
0292 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
0293 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
0294 [SLAVE_IPA_CFG] = &qhs_ipa,
0295 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
0296 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
0297 [SLAVE_NPU_CFG] = &qhs_npu_cfg,
0298 [SLAVE_NPU_DMA_BWMON_CFG] = &qhs_npu_dma_throttle_cfg,
0299 [SLAVE_NPU_PROC_BWMON_CFG] = &qhs_npu_dsp_throttle_cfg,
0300 [SLAVE_PDM] = &qhs_pdm,
0301 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
0302 [SLAVE_PRNG] = &qhs_prng,
0303 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
0304 [SLAVE_QM_CFG] = &qhs_qm_cfg,
0305 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
0306 [SLAVE_QSPI_0] = &qhs_qspi,
0307 [SLAVE_QUP_0] = &qhs_qup0,
0308 [SLAVE_QUP_1] = &qhs_qup1,
0309 [SLAVE_SDCC_2] = &qhs_sdc2,
0310 [SLAVE_SECURITY] = &qhs_security,
0311 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
0312 [SLAVE_TCSR] = &qhs_tcsr,
0313 [SLAVE_TLMM_WEST] = &qhs_tlmm_1,
0314 [SLAVE_TLMM_NORTH] = &qhs_tlmm_2,
0315 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_3,
0316 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
0317 [SLAVE_USB3] = &qhs_usb3,
0318 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
0319 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg,
0320 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
0321 [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
0322 };
0323
0324 static const struct qcom_icc_desc sc7180_config_noc = {
0325 .nodes = config_noc_nodes,
0326 .num_nodes = ARRAY_SIZE(config_noc_nodes),
0327 .bcms = config_noc_bcms,
0328 .num_bcms = ARRAY_SIZE(config_noc_bcms),
0329 };
0330
0331 static struct qcom_icc_node * const dc_noc_nodes[] = {
0332 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
0333 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
0334 [SLAVE_LLCC_CFG] = &qhs_llcc,
0335 };
0336
0337 static const struct qcom_icc_desc sc7180_dc_noc = {
0338 .nodes = dc_noc_nodes,
0339 .num_nodes = ARRAY_SIZE(dc_noc_nodes),
0340 };
0341
0342 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
0343 &bcm_sh0,
0344 &bcm_sh2,
0345 &bcm_sh3,
0346 &bcm_sh4,
0347 };
0348
0349 static struct qcom_icc_node * const gem_noc_nodes[] = {
0350 [MASTER_APPSS_PROC] = &acm_apps0,
0351 [MASTER_SYS_TCU] = &acm_sys_tcu,
0352 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
0353 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
0354 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
0355 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
0356 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
0357 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
0358 [MASTER_GFX3D] = &qxm_gpu,
0359 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
0360 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
0361 [SLAVE_LLCC] = &qns_llcc,
0362 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
0363 };
0364
0365 static const struct qcom_icc_desc sc7180_gem_noc = {
0366 .nodes = gem_noc_nodes,
0367 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
0368 .bcms = gem_noc_bcms,
0369 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
0370 };
0371
0372 static struct qcom_icc_bcm *mc_virt_bcms[] = {
0373 &bcm_acv,
0374 &bcm_mc0,
0375 };
0376
0377 static struct qcom_icc_node * const mc_virt_nodes[] = {
0378 [MASTER_LLCC] = &llcc_mc,
0379 [SLAVE_EBI1] = &ebi,
0380 };
0381
0382 static const struct qcom_icc_desc sc7180_mc_virt = {
0383 .nodes = mc_virt_nodes,
0384 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
0385 .bcms = mc_virt_bcms,
0386 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
0387 };
0388
0389 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
0390 &bcm_mm0,
0391 &bcm_mm1,
0392 &bcm_mm2,
0393 };
0394
0395 static struct qcom_icc_node * const mmss_noc_nodes[] = {
0396 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
0397 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0,
0398 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1,
0399 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
0400 [MASTER_MDP0] = &qxm_mdp0,
0401 [MASTER_ROTATOR] = &qxm_rot,
0402 [MASTER_VIDEO_P0] = &qxm_venus0,
0403 [MASTER_VIDEO_PROC] = &qxm_venus_arm9,
0404 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
0405 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
0406 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
0407 };
0408
0409 static const struct qcom_icc_desc sc7180_mmss_noc = {
0410 .nodes = mmss_noc_nodes,
0411 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
0412 .bcms = mmss_noc_bcms,
0413 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
0414 };
0415
0416 static struct qcom_icc_node * const npu_noc_nodes[] = {
0417 [MASTER_NPU_SYS] = &amm_npu_sys,
0418 [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg,
0419 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
0420 [SLAVE_NPU_CP] = &qhs_cp,
0421 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
0422 [SLAVE_NPU_DPM] = &qhs_dpm,
0423 [SLAVE_ISENSE_CFG] = &qhs_isense,
0424 [SLAVE_NPU_LLM_CFG] = &qhs_llm,
0425 [SLAVE_NPU_TCM] = &qhs_tcm,
0426 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
0427 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
0428 };
0429
0430 static const struct qcom_icc_desc sc7180_npu_noc = {
0431 .nodes = npu_noc_nodes,
0432 .num_nodes = ARRAY_SIZE(npu_noc_nodes),
0433 };
0434
0435 static struct qcom_icc_bcm * const qup_virt_bcms[] = {
0436 &bcm_qup0,
0437 };
0438
0439 static struct qcom_icc_node * const qup_virt_nodes[] = {
0440 [MASTER_QUP_CORE_0] = &qup_core_master_1,
0441 [MASTER_QUP_CORE_1] = &qup_core_master_2,
0442 [SLAVE_QUP_CORE_0] = &qup_core_slave_1,
0443 [SLAVE_QUP_CORE_1] = &qup_core_slave_2,
0444 };
0445
0446 static const struct qcom_icc_desc sc7180_qup_virt = {
0447 .nodes = qup_virt_nodes,
0448 .num_nodes = ARRAY_SIZE(qup_virt_nodes),
0449 .bcms = qup_virt_bcms,
0450 .num_bcms = ARRAY_SIZE(qup_virt_bcms),
0451 };
0452
0453 static struct qcom_icc_bcm * const system_noc_bcms[] = {
0454 &bcm_sn0,
0455 &bcm_sn1,
0456 &bcm_sn2,
0457 &bcm_sn3,
0458 &bcm_sn4,
0459 &bcm_sn7,
0460 &bcm_sn9,
0461 &bcm_sn12,
0462 };
0463
0464 static struct qcom_icc_node * const system_noc_nodes[] = {
0465 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
0466 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
0467 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
0468 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
0469 [MASTER_PIMEM] = &qxm_pimem,
0470 [SLAVE_APPSS] = &qhs_apss,
0471 [SLAVE_SNOC_CNOC] = &qns_cnoc,
0472 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
0473 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
0474 [SLAVE_IMEM] = &qxs_imem,
0475 [SLAVE_PIMEM] = &qxs_pimem,
0476 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
0477 [SLAVE_QDSS_STM] = &xs_qdss_stm,
0478 [SLAVE_TCU] = &xs_sys_tcu_cfg,
0479 };
0480
0481 static const struct qcom_icc_desc sc7180_system_noc = {
0482 .nodes = system_noc_nodes,
0483 .num_nodes = ARRAY_SIZE(system_noc_nodes),
0484 .bcms = system_noc_bcms,
0485 .num_bcms = ARRAY_SIZE(system_noc_bcms),
0486 };
0487
0488 static const struct of_device_id qnoc_of_match[] = {
0489 { .compatible = "qcom,sc7180-aggre1-noc",
0490 .data = &sc7180_aggre1_noc},
0491 { .compatible = "qcom,sc7180-aggre2-noc",
0492 .data = &sc7180_aggre2_noc},
0493 { .compatible = "qcom,sc7180-camnoc-virt",
0494 .data = &sc7180_camnoc_virt},
0495 { .compatible = "qcom,sc7180-compute-noc",
0496 .data = &sc7180_compute_noc},
0497 { .compatible = "qcom,sc7180-config-noc",
0498 .data = &sc7180_config_noc},
0499 { .compatible = "qcom,sc7180-dc-noc",
0500 .data = &sc7180_dc_noc},
0501 { .compatible = "qcom,sc7180-gem-noc",
0502 .data = &sc7180_gem_noc},
0503 { .compatible = "qcom,sc7180-mc-virt",
0504 .data = &sc7180_mc_virt},
0505 { .compatible = "qcom,sc7180-mmss-noc",
0506 .data = &sc7180_mmss_noc},
0507 { .compatible = "qcom,sc7180-npu-noc",
0508 .data = &sc7180_npu_noc},
0509 { .compatible = "qcom,sc7180-qup-virt",
0510 .data = &sc7180_qup_virt},
0511 { .compatible = "qcom,sc7180-system-noc",
0512 .data = &sc7180_system_noc},
0513 { }
0514 };
0515 MODULE_DEVICE_TABLE(of, qnoc_of_match);
0516
0517 static struct platform_driver qnoc_driver = {
0518 .probe = qcom_icc_rpmh_probe,
0519 .remove = qcom_icc_rpmh_remove,
0520 .driver = {
0521 .name = "qnoc-sc7180",
0522 .of_match_table = qnoc_of_match,
0523 .sync_state = icc_sync_state,
0524 },
0525 };
0526 module_platform_driver(qnoc_driver);
0527
0528 MODULE_DESCRIPTION("Qualcomm SC7180 NoC driver");
0529 MODULE_LICENSE("GPL v2");
