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0009 #include <dt-bindings/interconnect/qcom,qcm2290.h>
0010 #include <linux/clk.h>
0011 #include <linux/device.h>
0012 #include <linux/interconnect-provider.h>
0013 #include <linux/io.h>
0014 #include <linux/module.h>
0015 #include <linux/of_device.h>
0016 #include <linux/of_platform.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/regmap.h>
0019 #include <linux/slab.h>
0020
0021 #include "icc-rpm.h"
0022 #include "smd-rpm.h"
0023
0024 enum {
0025 QCM2290_MASTER_APPSS_PROC = 1,
0026 QCM2290_MASTER_SNOC_BIMC_RT,
0027 QCM2290_MASTER_SNOC_BIMC_NRT,
0028 QCM2290_MASTER_SNOC_BIMC,
0029 QCM2290_MASTER_TCU_0,
0030 QCM2290_MASTER_GFX3D,
0031 QCM2290_MASTER_SNOC_CNOC,
0032 QCM2290_MASTER_QDSS_DAP,
0033 QCM2290_MASTER_CRYPTO_CORE0,
0034 QCM2290_MASTER_SNOC_CFG,
0035 QCM2290_MASTER_TIC,
0036 QCM2290_MASTER_ANOC_SNOC,
0037 QCM2290_MASTER_BIMC_SNOC,
0038 QCM2290_MASTER_PIMEM,
0039 QCM2290_MASTER_QDSS_BAM,
0040 QCM2290_MASTER_QUP_0,
0041 QCM2290_MASTER_IPA,
0042 QCM2290_MASTER_QDSS_ETR,
0043 QCM2290_MASTER_SDCC_1,
0044 QCM2290_MASTER_SDCC_2,
0045 QCM2290_MASTER_QPIC,
0046 QCM2290_MASTER_USB3_0,
0047 QCM2290_MASTER_QUP_CORE_0,
0048 QCM2290_MASTER_CAMNOC_SF,
0049 QCM2290_MASTER_VIDEO_P0,
0050 QCM2290_MASTER_VIDEO_PROC,
0051 QCM2290_MASTER_CAMNOC_HF,
0052 QCM2290_MASTER_MDP0,
0053
0054 QCM2290_SLAVE_EBI1,
0055 QCM2290_SLAVE_BIMC_SNOC,
0056 QCM2290_SLAVE_BIMC_CFG,
0057 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG,
0058 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG,
0059 QCM2290_SLAVE_CAMERA_CFG,
0060 QCM2290_SLAVE_CLK_CTL,
0061 QCM2290_SLAVE_CRYPTO_0_CFG,
0062 QCM2290_SLAVE_DISPLAY_CFG,
0063 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG,
0064 QCM2290_SLAVE_GPU_CFG,
0065 QCM2290_SLAVE_HWKM,
0066 QCM2290_SLAVE_IMEM_CFG,
0067 QCM2290_SLAVE_IPA_CFG,
0068 QCM2290_SLAVE_LPASS,
0069 QCM2290_SLAVE_MESSAGE_RAM,
0070 QCM2290_SLAVE_PDM,
0071 QCM2290_SLAVE_PIMEM_CFG,
0072 QCM2290_SLAVE_PKA_WRAPPER,
0073 QCM2290_SLAVE_PMIC_ARB,
0074 QCM2290_SLAVE_PRNG,
0075 QCM2290_SLAVE_QDSS_CFG,
0076 QCM2290_SLAVE_QM_CFG,
0077 QCM2290_SLAVE_QM_MPU_CFG,
0078 QCM2290_SLAVE_QPIC,
0079 QCM2290_SLAVE_QUP_0,
0080 QCM2290_SLAVE_SDCC_1,
0081 QCM2290_SLAVE_SDCC_2,
0082 QCM2290_SLAVE_SNOC_CFG,
0083 QCM2290_SLAVE_TCSR,
0084 QCM2290_SLAVE_USB3,
0085 QCM2290_SLAVE_VENUS_CFG,
0086 QCM2290_SLAVE_VENUS_THROTTLE_CFG,
0087 QCM2290_SLAVE_VSENSE_CTRL_CFG,
0088 QCM2290_SLAVE_SERVICE_CNOC,
0089 QCM2290_SLAVE_APPSS,
0090 QCM2290_SLAVE_SNOC_CNOC,
0091 QCM2290_SLAVE_IMEM,
0092 QCM2290_SLAVE_PIMEM,
0093 QCM2290_SLAVE_SNOC_BIMC,
0094 QCM2290_SLAVE_SERVICE_SNOC,
0095 QCM2290_SLAVE_QDSS_STM,
0096 QCM2290_SLAVE_TCU,
0097 QCM2290_SLAVE_ANOC_SNOC,
0098 QCM2290_SLAVE_QUP_CORE_0,
0099 QCM2290_SLAVE_SNOC_BIMC_NRT,
0100 QCM2290_SLAVE_SNOC_BIMC_RT,
0101 };
0102
0103
0104 static const u16 mas_appss_proc_links[] = {
0105 QCM2290_SLAVE_EBI1,
0106 QCM2290_SLAVE_BIMC_SNOC,
0107 };
0108
0109 static struct qcom_icc_node mas_appss_proc = {
0110 .id = QCM2290_MASTER_APPSS_PROC,
0111 .name = "mas_apps_proc",
0112 .buswidth = 16,
0113 .qos.ap_owned = true,
0114 .qos.qos_port = 0,
0115 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0116 .qos.prio_level = 0,
0117 .qos.areq_prio = 0,
0118 .mas_rpm_id = 0,
0119 .slv_rpm_id = -1,
0120 .num_links = ARRAY_SIZE(mas_appss_proc_links),
0121 .links = mas_appss_proc_links,
0122 };
0123
0124 static const u16 mas_snoc_bimc_rt_links[] = {
0125 QCM2290_SLAVE_EBI1,
0126 };
0127
0128 static struct qcom_icc_node mas_snoc_bimc_rt = {
0129 .id = QCM2290_MASTER_SNOC_BIMC_RT,
0130 .name = "mas_snoc_bimc_rt",
0131 .buswidth = 16,
0132 .qos.ap_owned = true,
0133 .qos.qos_port = 2,
0134 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0135 .mas_rpm_id = 163,
0136 .slv_rpm_id = -1,
0137 .num_links = ARRAY_SIZE(mas_snoc_bimc_rt_links),
0138 .links = mas_snoc_bimc_rt_links,
0139 };
0140
0141 static const u16 mas_snoc_bimc_nrt_links[] = {
0142 QCM2290_SLAVE_EBI1,
0143 };
0144
0145 static struct qcom_icc_node mas_snoc_bimc_nrt = {
0146 .id = QCM2290_MASTER_SNOC_BIMC_NRT,
0147 .name = "mas_snoc_bimc_nrt",
0148 .buswidth = 16,
0149 .qos.ap_owned = true,
0150 .qos.qos_port = 2,
0151 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0152 .mas_rpm_id = 163,
0153 .slv_rpm_id = -1,
0154 .num_links = ARRAY_SIZE(mas_snoc_bimc_nrt_links),
0155 .links = mas_snoc_bimc_nrt_links,
0156 };
0157
0158 static const u16 mas_snoc_bimc_links[] = {
0159 QCM2290_SLAVE_EBI1,
0160 };
0161
0162 static struct qcom_icc_node mas_snoc_bimc = {
0163 .id = QCM2290_MASTER_SNOC_BIMC,
0164 .name = "mas_snoc_bimc",
0165 .buswidth = 16,
0166 .qos.ap_owned = true,
0167 .qos.qos_port = 2,
0168 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0169 .mas_rpm_id = 164,
0170 .slv_rpm_id = -1,
0171 .num_links = ARRAY_SIZE(mas_snoc_bimc_links),
0172 .links = mas_snoc_bimc_links,
0173 };
0174
0175 static const u16 mas_tcu_0_links[] = {
0176 QCM2290_SLAVE_EBI1,
0177 QCM2290_SLAVE_BIMC_SNOC,
0178 };
0179
0180 static struct qcom_icc_node mas_tcu_0 = {
0181 .id = QCM2290_MASTER_TCU_0,
0182 .name = "mas_tcu_0",
0183 .buswidth = 8,
0184 .qos.ap_owned = true,
0185 .qos.qos_port = 4,
0186 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0187 .qos.prio_level = 6,
0188 .qos.areq_prio = 6,
0189 .mas_rpm_id = 102,
0190 .slv_rpm_id = -1,
0191 .num_links = ARRAY_SIZE(mas_tcu_0_links),
0192 .links = mas_tcu_0_links,
0193 };
0194
0195 static const u16 mas_snoc_cnoc_links[] = {
0196 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG,
0197 QCM2290_SLAVE_SDCC_2,
0198 QCM2290_SLAVE_SDCC_1,
0199 QCM2290_SLAVE_QM_CFG,
0200 QCM2290_SLAVE_BIMC_CFG,
0201 QCM2290_SLAVE_USB3,
0202 QCM2290_SLAVE_QM_MPU_CFG,
0203 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG,
0204 QCM2290_SLAVE_QDSS_CFG,
0205 QCM2290_SLAVE_PDM,
0206 QCM2290_SLAVE_IPA_CFG,
0207 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG,
0208 QCM2290_SLAVE_TCSR,
0209 QCM2290_SLAVE_MESSAGE_RAM,
0210 QCM2290_SLAVE_PMIC_ARB,
0211 QCM2290_SLAVE_LPASS,
0212 QCM2290_SLAVE_DISPLAY_CFG,
0213 QCM2290_SLAVE_VENUS_CFG,
0214 QCM2290_SLAVE_GPU_CFG,
0215 QCM2290_SLAVE_IMEM_CFG,
0216 QCM2290_SLAVE_SNOC_CFG,
0217 QCM2290_SLAVE_SERVICE_CNOC,
0218 QCM2290_SLAVE_VENUS_THROTTLE_CFG,
0219 QCM2290_SLAVE_PKA_WRAPPER,
0220 QCM2290_SLAVE_HWKM,
0221 QCM2290_SLAVE_PRNG,
0222 QCM2290_SLAVE_VSENSE_CTRL_CFG,
0223 QCM2290_SLAVE_CRYPTO_0_CFG,
0224 QCM2290_SLAVE_PIMEM_CFG,
0225 QCM2290_SLAVE_QUP_0,
0226 QCM2290_SLAVE_CAMERA_CFG,
0227 QCM2290_SLAVE_CLK_CTL,
0228 QCM2290_SLAVE_QPIC,
0229 };
0230
0231 static struct qcom_icc_node mas_snoc_cnoc = {
0232 .id = QCM2290_MASTER_SNOC_CNOC,
0233 .name = "mas_snoc_cnoc",
0234 .buswidth = 8,
0235 .qos.ap_owned = true,
0236 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0237 .mas_rpm_id = 52,
0238 .slv_rpm_id = -1,
0239 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links),
0240 .links = mas_snoc_cnoc_links,
0241 };
0242
0243 static const u16 mas_qdss_dap_links[] = {
0244 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG,
0245 QCM2290_SLAVE_SDCC_2,
0246 QCM2290_SLAVE_SDCC_1,
0247 QCM2290_SLAVE_QM_CFG,
0248 QCM2290_SLAVE_BIMC_CFG,
0249 QCM2290_SLAVE_USB3,
0250 QCM2290_SLAVE_QM_MPU_CFG,
0251 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG,
0252 QCM2290_SLAVE_QDSS_CFG,
0253 QCM2290_SLAVE_PDM,
0254 QCM2290_SLAVE_IPA_CFG,
0255 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG,
0256 QCM2290_SLAVE_TCSR,
0257 QCM2290_SLAVE_MESSAGE_RAM,
0258 QCM2290_SLAVE_PMIC_ARB,
0259 QCM2290_SLAVE_LPASS,
0260 QCM2290_SLAVE_DISPLAY_CFG,
0261 QCM2290_SLAVE_VENUS_CFG,
0262 QCM2290_SLAVE_GPU_CFG,
0263 QCM2290_SLAVE_IMEM_CFG,
0264 QCM2290_SLAVE_SNOC_CFG,
0265 QCM2290_SLAVE_SERVICE_CNOC,
0266 QCM2290_SLAVE_VENUS_THROTTLE_CFG,
0267 QCM2290_SLAVE_PKA_WRAPPER,
0268 QCM2290_SLAVE_HWKM,
0269 QCM2290_SLAVE_PRNG,
0270 QCM2290_SLAVE_VSENSE_CTRL_CFG,
0271 QCM2290_SLAVE_CRYPTO_0_CFG,
0272 QCM2290_SLAVE_PIMEM_CFG,
0273 QCM2290_SLAVE_QUP_0,
0274 QCM2290_SLAVE_CAMERA_CFG,
0275 QCM2290_SLAVE_CLK_CTL,
0276 QCM2290_SLAVE_QPIC,
0277 };
0278
0279 static struct qcom_icc_node mas_qdss_dap = {
0280 .id = QCM2290_MASTER_QDSS_DAP,
0281 .name = "mas_qdss_dap",
0282 .buswidth = 8,
0283 .qos.ap_owned = true,
0284 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0285 .mas_rpm_id = 49,
0286 .slv_rpm_id = -1,
0287 .num_links = ARRAY_SIZE(mas_qdss_dap_links),
0288 .links = mas_qdss_dap_links,
0289 };
0290
0291 static const u16 mas_crypto_core0_links[] = {
0292 QCM2290_SLAVE_ANOC_SNOC
0293 };
0294
0295 static struct qcom_icc_node mas_crypto_core0 = {
0296 .id = QCM2290_MASTER_CRYPTO_CORE0,
0297 .name = "mas_crypto_core0",
0298 .buswidth = 8,
0299 .qos.ap_owned = true,
0300 .qos.qos_port = 22,
0301 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0302 .qos.areq_prio = 2,
0303 .mas_rpm_id = 23,
0304 .slv_rpm_id = -1,
0305 .num_links = ARRAY_SIZE(mas_crypto_core0_links),
0306 .links = mas_crypto_core0_links,
0307 };
0308
0309 static const u16 mas_qup_core_0_links[] = {
0310 QCM2290_SLAVE_QUP_CORE_0,
0311 };
0312
0313 static struct qcom_icc_node mas_qup_core_0 = {
0314 .id = QCM2290_MASTER_QUP_CORE_0,
0315 .name = "mas_qup_core_0",
0316 .buswidth = 4,
0317 .mas_rpm_id = 170,
0318 .slv_rpm_id = -1,
0319 .num_links = ARRAY_SIZE(mas_qup_core_0_links),
0320 .links = mas_qup_core_0_links,
0321 };
0322
0323 static const u16 mas_camnoc_sf_links[] = {
0324 QCM2290_SLAVE_SNOC_BIMC_NRT,
0325 };
0326
0327 static struct qcom_icc_node mas_camnoc_sf = {
0328 .id = QCM2290_MASTER_CAMNOC_SF,
0329 .name = "mas_camnoc_sf",
0330 .buswidth = 32,
0331 .qos.ap_owned = true,
0332 .qos.qos_port = 4,
0333 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0334 .qos.areq_prio = 3,
0335 .mas_rpm_id = 172,
0336 .slv_rpm_id = -1,
0337 .num_links = ARRAY_SIZE(mas_camnoc_sf_links),
0338 .links = mas_camnoc_sf_links,
0339 };
0340
0341 static const u16 mas_camnoc_hf_links[] = {
0342 QCM2290_SLAVE_SNOC_BIMC_RT,
0343 };
0344
0345 static struct qcom_icc_node mas_camnoc_hf = {
0346 .id = QCM2290_MASTER_CAMNOC_HF,
0347 .name = "mas_camnoc_hf",
0348 .buswidth = 32,
0349 .qos.ap_owned = true,
0350 .qos.qos_port = 10,
0351 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0352 .qos.areq_prio = 3,
0353 .qos.urg_fwd_en = true,
0354 .mas_rpm_id = 173,
0355 .slv_rpm_id = -1,
0356 .num_links = ARRAY_SIZE(mas_camnoc_hf_links),
0357 .links = mas_camnoc_hf_links,
0358 };
0359
0360 static const u16 mas_mdp0_links[] = {
0361 QCM2290_SLAVE_SNOC_BIMC_RT,
0362 };
0363
0364 static struct qcom_icc_node mas_mdp0 = {
0365 .id = QCM2290_MASTER_MDP0,
0366 .name = "mas_mdp0",
0367 .buswidth = 16,
0368 .qos.ap_owned = true,
0369 .qos.qos_port = 5,
0370 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0371 .qos.areq_prio = 3,
0372 .qos.urg_fwd_en = true,
0373 .mas_rpm_id = 8,
0374 .slv_rpm_id = -1,
0375 .num_links = ARRAY_SIZE(mas_mdp0_links),
0376 .links = mas_mdp0_links,
0377 };
0378
0379 static const u16 mas_video_p0_links[] = {
0380 QCM2290_SLAVE_SNOC_BIMC_NRT,
0381 };
0382
0383 static struct qcom_icc_node mas_video_p0 = {
0384 .id = QCM2290_MASTER_VIDEO_P0,
0385 .name = "mas_video_p0",
0386 .buswidth = 16,
0387 .qos.ap_owned = true,
0388 .qos.qos_port = 9,
0389 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0390 .qos.areq_prio = 3,
0391 .qos.urg_fwd_en = true,
0392 .mas_rpm_id = 9,
0393 .slv_rpm_id = -1,
0394 .num_links = ARRAY_SIZE(mas_video_p0_links),
0395 .links = mas_video_p0_links,
0396 };
0397
0398 static const u16 mas_video_proc_links[] = {
0399 QCM2290_SLAVE_SNOC_BIMC_NRT,
0400 };
0401
0402 static struct qcom_icc_node mas_video_proc = {
0403 .id = QCM2290_MASTER_VIDEO_PROC,
0404 .name = "mas_video_proc",
0405 .buswidth = 8,
0406 .qos.ap_owned = true,
0407 .qos.qos_port = 13,
0408 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0409 .qos.areq_prio = 4,
0410 .mas_rpm_id = 168,
0411 .slv_rpm_id = -1,
0412 .num_links = ARRAY_SIZE(mas_video_proc_links),
0413 .links = mas_video_proc_links,
0414 };
0415
0416 static const u16 mas_snoc_cfg_links[] = {
0417 QCM2290_SLAVE_SERVICE_SNOC,
0418 };
0419
0420 static struct qcom_icc_node mas_snoc_cfg = {
0421 .id = QCM2290_MASTER_SNOC_CFG,
0422 .name = "mas_snoc_cfg",
0423 .buswidth = 4,
0424 .qos.ap_owned = true,
0425 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0426 .mas_rpm_id = 20,
0427 .slv_rpm_id = -1,
0428 .num_links = ARRAY_SIZE(mas_snoc_cfg_links),
0429 .links = mas_snoc_cfg_links,
0430 };
0431
0432 static const u16 mas_tic_links[] = {
0433 QCM2290_SLAVE_PIMEM,
0434 QCM2290_SLAVE_IMEM,
0435 QCM2290_SLAVE_APPSS,
0436 QCM2290_SLAVE_SNOC_BIMC,
0437 QCM2290_SLAVE_SNOC_CNOC,
0438 QCM2290_SLAVE_TCU,
0439 QCM2290_SLAVE_QDSS_STM,
0440 };
0441
0442 static struct qcom_icc_node mas_tic = {
0443 .id = QCM2290_MASTER_TIC,
0444 .name = "mas_tic",
0445 .buswidth = 4,
0446 .qos.ap_owned = true,
0447 .qos.qos_port = 8,
0448 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0449 .qos.areq_prio = 2,
0450 .mas_rpm_id = 51,
0451 .slv_rpm_id = -1,
0452 .num_links = ARRAY_SIZE(mas_tic_links),
0453 .links = mas_tic_links,
0454 };
0455
0456 static const u16 mas_anoc_snoc_links[] = {
0457 QCM2290_SLAVE_PIMEM,
0458 QCM2290_SLAVE_IMEM,
0459 QCM2290_SLAVE_APPSS,
0460 QCM2290_SLAVE_SNOC_BIMC,
0461 QCM2290_SLAVE_SNOC_CNOC,
0462 QCM2290_SLAVE_TCU,
0463 QCM2290_SLAVE_QDSS_STM,
0464 };
0465
0466 static struct qcom_icc_node mas_anoc_snoc = {
0467 .id = QCM2290_MASTER_ANOC_SNOC,
0468 .name = "mas_anoc_snoc",
0469 .buswidth = 16,
0470 .mas_rpm_id = 110,
0471 .slv_rpm_id = -1,
0472 .num_links = ARRAY_SIZE(mas_anoc_snoc_links),
0473 .links = mas_anoc_snoc_links,
0474 };
0475
0476 static const u16 mas_bimc_snoc_links[] = {
0477 QCM2290_SLAVE_PIMEM,
0478 QCM2290_SLAVE_IMEM,
0479 QCM2290_SLAVE_APPSS,
0480 QCM2290_SLAVE_SNOC_CNOC,
0481 QCM2290_SLAVE_TCU,
0482 QCM2290_SLAVE_QDSS_STM,
0483 };
0484
0485 static struct qcom_icc_node mas_bimc_snoc = {
0486 .id = QCM2290_MASTER_BIMC_SNOC,
0487 .name = "mas_bimc_snoc",
0488 .buswidth = 8,
0489 .mas_rpm_id = 21,
0490 .slv_rpm_id = -1,
0491 .num_links = ARRAY_SIZE(mas_bimc_snoc_links),
0492 .links = mas_bimc_snoc_links,
0493 };
0494
0495 static const u16 mas_pimem_links[] = {
0496 QCM2290_SLAVE_IMEM,
0497 QCM2290_SLAVE_SNOC_BIMC,
0498 };
0499
0500 static struct qcom_icc_node mas_pimem = {
0501 .id = QCM2290_MASTER_PIMEM,
0502 .name = "mas_pimem",
0503 .buswidth = 8,
0504 .qos.ap_owned = true,
0505 .qos.qos_port = 20,
0506 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0507 .qos.areq_prio = 2,
0508 .mas_rpm_id = 113,
0509 .slv_rpm_id = -1,
0510 .num_links = ARRAY_SIZE(mas_pimem_links),
0511 .links = mas_pimem_links,
0512 };
0513
0514 static const u16 mas_qdss_bam_links[] = {
0515 QCM2290_SLAVE_ANOC_SNOC,
0516 };
0517
0518 static struct qcom_icc_node mas_qdss_bam = {
0519 .id = QCM2290_MASTER_QDSS_BAM,
0520 .name = "mas_qdss_bam",
0521 .buswidth = 4,
0522 .qos.ap_owned = true,
0523 .qos.qos_port = 2,
0524 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0525 .qos.areq_prio = 2,
0526 .mas_rpm_id = 19,
0527 .slv_rpm_id = -1,
0528 .num_links = ARRAY_SIZE(mas_qdss_bam_links),
0529 .links = mas_qdss_bam_links,
0530 };
0531
0532 static const u16 mas_qup_0_links[] = {
0533 QCM2290_SLAVE_ANOC_SNOC,
0534 };
0535
0536 static struct qcom_icc_node mas_qup_0 = {
0537 .id = QCM2290_MASTER_QUP_0,
0538 .name = "mas_qup_0",
0539 .buswidth = 4,
0540 .qos.ap_owned = true,
0541 .qos.qos_port = 0,
0542 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0543 .qos.areq_prio = 2,
0544 .mas_rpm_id = 166,
0545 .slv_rpm_id = -1,
0546 .num_links = ARRAY_SIZE(mas_qup_0_links),
0547 .links = mas_qup_0_links,
0548 };
0549
0550 static const u16 mas_ipa_links[] = {
0551 QCM2290_SLAVE_ANOC_SNOC,
0552 };
0553
0554 static struct qcom_icc_node mas_ipa = {
0555 .id = QCM2290_MASTER_IPA,
0556 .name = "mas_ipa",
0557 .buswidth = 8,
0558 .qos.ap_owned = true,
0559 .qos.qos_port = 3,
0560 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0561 .qos.areq_prio = 2,
0562 .mas_rpm_id = 59,
0563 .slv_rpm_id = -1,
0564 .num_links = ARRAY_SIZE(mas_ipa_links),
0565 .links = mas_ipa_links,
0566 };
0567
0568 static const u16 mas_qdss_etr_links[] = {
0569 QCM2290_SLAVE_ANOC_SNOC,
0570 };
0571
0572 static struct qcom_icc_node mas_qdss_etr = {
0573 .id = QCM2290_MASTER_QDSS_ETR,
0574 .name = "mas_qdss_etr",
0575 .buswidth = 8,
0576 .qos.ap_owned = true,
0577 .qos.qos_port = 12,
0578 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0579 .qos.areq_prio = 2,
0580 .mas_rpm_id = 31,
0581 .slv_rpm_id = -1,
0582 .num_links = ARRAY_SIZE(mas_qdss_etr_links),
0583 .links = mas_qdss_etr_links,
0584 };
0585
0586 static const u16 mas_sdcc_1_links[] = {
0587 QCM2290_SLAVE_ANOC_SNOC,
0588 };
0589
0590 static struct qcom_icc_node mas_sdcc_1 = {
0591 .id = QCM2290_MASTER_SDCC_1,
0592 .name = "mas_sdcc_1",
0593 .buswidth = 8,
0594 .qos.ap_owned = true,
0595 .qos.qos_port = 17,
0596 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0597 .qos.areq_prio = 2,
0598 .mas_rpm_id = 33,
0599 .slv_rpm_id = -1,
0600 .num_links = ARRAY_SIZE(mas_sdcc_1_links),
0601 .links = mas_sdcc_1_links,
0602 };
0603
0604 static const u16 mas_sdcc_2_links[] = {
0605 QCM2290_SLAVE_ANOC_SNOC,
0606 };
0607
0608 static struct qcom_icc_node mas_sdcc_2 = {
0609 .id = QCM2290_MASTER_SDCC_2,
0610 .name = "mas_sdcc_2",
0611 .buswidth = 8,
0612 .qos.ap_owned = true,
0613 .qos.qos_port = 23,
0614 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0615 .qos.areq_prio = 2,
0616 .mas_rpm_id = 35,
0617 .slv_rpm_id = -1,
0618 .num_links = ARRAY_SIZE(mas_sdcc_2_links),
0619 .links = mas_sdcc_2_links,
0620 };
0621
0622 static const u16 mas_qpic_links[] = {
0623 QCM2290_SLAVE_ANOC_SNOC,
0624 };
0625
0626 static struct qcom_icc_node mas_qpic = {
0627 .id = QCM2290_MASTER_QPIC,
0628 .name = "mas_qpic",
0629 .buswidth = 4,
0630 .qos.ap_owned = true,
0631 .qos.qos_port = 1,
0632 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0633 .qos.areq_prio = 2,
0634 .mas_rpm_id = 58,
0635 .slv_rpm_id = -1,
0636 .num_links = ARRAY_SIZE(mas_qpic_links),
0637 .links = mas_qpic_links,
0638 };
0639
0640 static const u16 mas_usb3_0_links[] = {
0641 QCM2290_SLAVE_ANOC_SNOC,
0642 };
0643
0644 static struct qcom_icc_node mas_usb3_0 = {
0645 .id = QCM2290_MASTER_USB3_0,
0646 .name = "mas_usb3_0",
0647 .buswidth = 8,
0648 .qos.ap_owned = true,
0649 .qos.qos_port = 24,
0650 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0651 .qos.areq_prio = 2,
0652 .mas_rpm_id = 32,
0653 .slv_rpm_id = -1,
0654 .num_links = ARRAY_SIZE(mas_usb3_0_links),
0655 .links = mas_usb3_0_links,
0656 };
0657
0658 static const u16 mas_gfx3d_links[] = {
0659 QCM2290_SLAVE_EBI1,
0660 };
0661
0662 static struct qcom_icc_node mas_gfx3d = {
0663 .id = QCM2290_MASTER_GFX3D,
0664 .name = "mas_gfx3d",
0665 .buswidth = 32,
0666 .qos.ap_owned = true,
0667 .qos.qos_port = 1,
0668 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0669 .qos.prio_level = 0,
0670 .qos.areq_prio = 0,
0671 .mas_rpm_id = 6,
0672 .slv_rpm_id = -1,
0673 .num_links = ARRAY_SIZE(mas_gfx3d_links),
0674 .links = mas_gfx3d_links,
0675 };
0676
0677
0678 static struct qcom_icc_node slv_ebi1 = {
0679 .name = "slv_ebi1",
0680 .id = QCM2290_SLAVE_EBI1,
0681 .buswidth = 8,
0682 .mas_rpm_id = -1,
0683 .slv_rpm_id = 0,
0684 };
0685
0686 static const u16 slv_bimc_snoc_links[] = {
0687 QCM2290_MASTER_BIMC_SNOC,
0688 };
0689
0690 static struct qcom_icc_node slv_bimc_snoc = {
0691 .name = "slv_bimc_snoc",
0692 .id = QCM2290_SLAVE_BIMC_SNOC,
0693 .buswidth = 8,
0694 .mas_rpm_id = -1,
0695 .slv_rpm_id = 2,
0696 .num_links = ARRAY_SIZE(slv_bimc_snoc_links),
0697 .links = slv_bimc_snoc_links,
0698 };
0699
0700 static struct qcom_icc_node slv_bimc_cfg = {
0701 .name = "slv_bimc_cfg",
0702 .id = QCM2290_SLAVE_BIMC_CFG,
0703 .buswidth = 4,
0704 .qos.ap_owned = true,
0705 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0706 .mas_rpm_id = -1,
0707 .slv_rpm_id = 56,
0708 };
0709
0710 static struct qcom_icc_node slv_camera_nrt_throttle_cfg = {
0711 .name = "slv_camera_nrt_throttle_cfg",
0712 .id = QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG,
0713 .buswidth = 4,
0714 .qos.ap_owned = true,
0715 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0716 .mas_rpm_id = -1,
0717 .slv_rpm_id = 271,
0718 };
0719
0720 static struct qcom_icc_node slv_camera_rt_throttle_cfg = {
0721 .name = "slv_camera_rt_throttle_cfg",
0722 .id = QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG,
0723 .buswidth = 4,
0724 .qos.ap_owned = true,
0725 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0726 .mas_rpm_id = -1,
0727 .slv_rpm_id = 279,
0728 };
0729
0730 static struct qcom_icc_node slv_camera_cfg = {
0731 .name = "slv_camera_cfg",
0732 .id = QCM2290_SLAVE_CAMERA_CFG,
0733 .buswidth = 4,
0734 .qos.ap_owned = true,
0735 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0736 .mas_rpm_id = -1,
0737 .slv_rpm_id = 3,
0738 };
0739
0740 static struct qcom_icc_node slv_clk_ctl = {
0741 .name = "slv_clk_ctl",
0742 .id = QCM2290_SLAVE_CLK_CTL,
0743 .buswidth = 4,
0744 .qos.ap_owned = true,
0745 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0746 .mas_rpm_id = -1,
0747 .slv_rpm_id = 47,
0748 };
0749
0750 static struct qcom_icc_node slv_crypto_0_cfg = {
0751 .name = "slv_crypto_0_cfg",
0752 .id = QCM2290_SLAVE_CRYPTO_0_CFG,
0753 .buswidth = 4,
0754 .qos.ap_owned = true,
0755 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0756 .mas_rpm_id = -1,
0757 .slv_rpm_id = 52,
0758 };
0759
0760 static struct qcom_icc_node slv_display_cfg = {
0761 .name = "slv_display_cfg",
0762 .id = QCM2290_SLAVE_DISPLAY_CFG,
0763 .buswidth = 4,
0764 .qos.ap_owned = true,
0765 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0766 .mas_rpm_id = -1,
0767 .slv_rpm_id = 4,
0768 };
0769
0770 static struct qcom_icc_node slv_display_throttle_cfg = {
0771 .name = "slv_display_throttle_cfg",
0772 .id = QCM2290_SLAVE_DISPLAY_THROTTLE_CFG,
0773 .buswidth = 4,
0774 .qos.ap_owned = true,
0775 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0776 .mas_rpm_id = -1,
0777 .slv_rpm_id = 156,
0778 };
0779
0780 static struct qcom_icc_node slv_gpu_cfg = {
0781 .name = "slv_gpu_cfg",
0782 .id = QCM2290_SLAVE_GPU_CFG,
0783 .buswidth = 8,
0784 .qos.ap_owned = true,
0785 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0786 .mas_rpm_id = -1,
0787 .slv_rpm_id = 275,
0788 };
0789
0790 static struct qcom_icc_node slv_hwkm = {
0791 .name = "slv_hwkm",
0792 .id = QCM2290_SLAVE_HWKM,
0793 .buswidth = 4,
0794 .qos.ap_owned = true,
0795 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0796 .mas_rpm_id = -1,
0797 .slv_rpm_id = 280,
0798 };
0799
0800 static struct qcom_icc_node slv_imem_cfg = {
0801 .name = "slv_imem_cfg",
0802 .id = QCM2290_SLAVE_IMEM_CFG,
0803 .buswidth = 4,
0804 .qos.ap_owned = true,
0805 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0806 .mas_rpm_id = -1,
0807 .slv_rpm_id = 54,
0808 };
0809
0810 static struct qcom_icc_node slv_ipa_cfg = {
0811 .name = "slv_ipa_cfg",
0812 .id = QCM2290_SLAVE_IPA_CFG,
0813 .buswidth = 4,
0814 .qos.ap_owned = true,
0815 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0816 .mas_rpm_id = -1,
0817 .slv_rpm_id = 183,
0818 };
0819
0820 static struct qcom_icc_node slv_lpass = {
0821 .name = "slv_lpass",
0822 .id = QCM2290_SLAVE_LPASS,
0823 .buswidth = 4,
0824 .qos.ap_owned = true,
0825 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0826 .mas_rpm_id = -1,
0827 .slv_rpm_id = 21,
0828 };
0829
0830 static struct qcom_icc_node slv_message_ram = {
0831 .name = "slv_message_ram",
0832 .id = QCM2290_SLAVE_MESSAGE_RAM,
0833 .buswidth = 4,
0834 .qos.ap_owned = true,
0835 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0836 .mas_rpm_id = -1,
0837 .slv_rpm_id = 55,
0838 };
0839
0840 static struct qcom_icc_node slv_pdm = {
0841 .name = "slv_pdm",
0842 .id = QCM2290_SLAVE_PDM,
0843 .buswidth = 4,
0844 .qos.ap_owned = true,
0845 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0846 .mas_rpm_id = -1,
0847 .slv_rpm_id = 41,
0848 };
0849
0850 static struct qcom_icc_node slv_pimem_cfg = {
0851 .name = "slv_pimem_cfg",
0852 .id = QCM2290_SLAVE_PIMEM_CFG,
0853 .buswidth = 4,
0854 .qos.ap_owned = true,
0855 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0856 .mas_rpm_id = -1,
0857 .slv_rpm_id = 167,
0858 };
0859
0860 static struct qcom_icc_node slv_pka_wrapper = {
0861 .name = "slv_pka_wrapper",
0862 .id = QCM2290_SLAVE_PKA_WRAPPER,
0863 .buswidth = 4,
0864 .qos.ap_owned = true,
0865 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0866 .mas_rpm_id = -1,
0867 .slv_rpm_id = 281,
0868 };
0869
0870 static struct qcom_icc_node slv_pmic_arb = {
0871 .name = "slv_pmic_arb",
0872 .id = QCM2290_SLAVE_PMIC_ARB,
0873 .buswidth = 4,
0874 .qos.ap_owned = true,
0875 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0876 .mas_rpm_id = -1,
0877 .slv_rpm_id = 59,
0878 };
0879
0880 static struct qcom_icc_node slv_prng = {
0881 .name = "slv_prng",
0882 .id = QCM2290_SLAVE_PRNG,
0883 .buswidth = 4,
0884 .qos.ap_owned = true,
0885 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0886 .mas_rpm_id = -1,
0887 .slv_rpm_id = 44,
0888 };
0889
0890 static struct qcom_icc_node slv_qdss_cfg = {
0891 .name = "slv_qdss_cfg",
0892 .id = QCM2290_SLAVE_QDSS_CFG,
0893 .buswidth = 4,
0894 .qos.ap_owned = true,
0895 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0896 .mas_rpm_id = -1,
0897 .slv_rpm_id = 63,
0898 };
0899
0900 static struct qcom_icc_node slv_qm_cfg = {
0901 .name = "slv_qm_cfg",
0902 .id = QCM2290_SLAVE_QM_CFG,
0903 .buswidth = 4,
0904 .qos.ap_owned = true,
0905 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0906 .mas_rpm_id = -1,
0907 .slv_rpm_id = 212,
0908 };
0909
0910 static struct qcom_icc_node slv_qm_mpu_cfg = {
0911 .name = "slv_qm_mpu_cfg",
0912 .id = QCM2290_SLAVE_QM_MPU_CFG,
0913 .buswidth = 4,
0914 .qos.ap_owned = true,
0915 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0916 .mas_rpm_id = -1,
0917 .slv_rpm_id = 231,
0918 };
0919
0920 static struct qcom_icc_node slv_qpic = {
0921 .name = "slv_qpic",
0922 .id = QCM2290_SLAVE_QPIC,
0923 .buswidth = 4,
0924 .qos.ap_owned = true,
0925 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0926 .mas_rpm_id = -1,
0927 .slv_rpm_id = 80,
0928 };
0929
0930 static struct qcom_icc_node slv_qup_0 = {
0931 .name = "slv_qup_0",
0932 .id = QCM2290_SLAVE_QUP_0,
0933 .buswidth = 4,
0934 .qos.ap_owned = true,
0935 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0936 .mas_rpm_id = -1,
0937 .slv_rpm_id = 261,
0938 };
0939
0940 static struct qcom_icc_node slv_sdcc_1 = {
0941 .name = "slv_sdcc_1",
0942 .id = QCM2290_SLAVE_SDCC_1,
0943 .buswidth = 4,
0944 .qos.ap_owned = true,
0945 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0946 .mas_rpm_id = -1,
0947 .slv_rpm_id = 31,
0948 };
0949
0950 static struct qcom_icc_node slv_sdcc_2 = {
0951 .name = "slv_sdcc_2",
0952 .id = QCM2290_SLAVE_SDCC_2,
0953 .buswidth = 4,
0954 .qos.ap_owned = true,
0955 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0956 .mas_rpm_id = -1,
0957 .slv_rpm_id = 33,
0958 };
0959
0960 static const u16 slv_snoc_cfg_links[] = {
0961 QCM2290_MASTER_SNOC_CFG,
0962 };
0963
0964 static struct qcom_icc_node slv_snoc_cfg = {
0965 .name = "slv_snoc_cfg",
0966 .id = QCM2290_SLAVE_SNOC_CFG,
0967 .buswidth = 4,
0968 .qos.ap_owned = true,
0969 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0970 .mas_rpm_id = -1,
0971 .slv_rpm_id = 70,
0972 .num_links = ARRAY_SIZE(slv_snoc_cfg_links),
0973 .links = slv_snoc_cfg_links,
0974 };
0975
0976 static struct qcom_icc_node slv_tcsr = {
0977 .name = "slv_tcsr",
0978 .id = QCM2290_SLAVE_TCSR,
0979 .buswidth = 4,
0980 .qos.ap_owned = true,
0981 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0982 .mas_rpm_id = -1,
0983 .slv_rpm_id = 50,
0984 };
0985
0986 static struct qcom_icc_node slv_usb3 = {
0987 .name = "slv_usb3",
0988 .id = QCM2290_SLAVE_USB3,
0989 .buswidth = 4,
0990 .qos.ap_owned = true,
0991 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0992 .mas_rpm_id = -1,
0993 .slv_rpm_id = 22,
0994 };
0995
0996 static struct qcom_icc_node slv_venus_cfg = {
0997 .name = "slv_venus_cfg",
0998 .id = QCM2290_SLAVE_VENUS_CFG,
0999 .buswidth = 4,
1000 .qos.ap_owned = true,
1001 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1002 .mas_rpm_id = -1,
1003 .slv_rpm_id = 10,
1004 };
1005
1006 static struct qcom_icc_node slv_venus_throttle_cfg = {
1007 .name = "slv_venus_throttle_cfg",
1008 .id = QCM2290_SLAVE_VENUS_THROTTLE_CFG,
1009 .buswidth = 4,
1010 .qos.ap_owned = true,
1011 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1012 .mas_rpm_id = -1,
1013 .slv_rpm_id = 178,
1014 };
1015
1016 static struct qcom_icc_node slv_vsense_ctrl_cfg = {
1017 .name = "slv_vsense_ctrl_cfg",
1018 .id = QCM2290_SLAVE_VSENSE_CTRL_CFG,
1019 .buswidth = 4,
1020 .qos.ap_owned = true,
1021 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1022 .mas_rpm_id = -1,
1023 .slv_rpm_id = 263,
1024 };
1025
1026 static struct qcom_icc_node slv_service_cnoc = {
1027 .name = "slv_service_cnoc",
1028 .id = QCM2290_SLAVE_SERVICE_CNOC,
1029 .buswidth = 4,
1030 .qos.ap_owned = true,
1031 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1032 .mas_rpm_id = -1,
1033 .slv_rpm_id = 76,
1034 };
1035
1036 static struct qcom_icc_node slv_qup_core_0 = {
1037 .name = "slv_qup_core_0",
1038 .id = QCM2290_SLAVE_QUP_CORE_0,
1039 .buswidth = 4,
1040 .qos.ap_owned = true,
1041 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1042 .mas_rpm_id = -1,
1043 .slv_rpm_id = 264,
1044 };
1045
1046 static const u16 slv_snoc_bimc_nrt_links[] = {
1047 QCM2290_MASTER_SNOC_BIMC_NRT,
1048 };
1049
1050 static struct qcom_icc_node slv_snoc_bimc_nrt = {
1051 .name = "slv_snoc_bimc_nrt",
1052 .id = QCM2290_SLAVE_SNOC_BIMC_NRT,
1053 .buswidth = 16,
1054 .qos.ap_owned = true,
1055 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1056 .mas_rpm_id = -1,
1057 .slv_rpm_id = 259,
1058 .num_links = ARRAY_SIZE(slv_snoc_bimc_nrt_links),
1059 .links = slv_snoc_bimc_nrt_links,
1060 };
1061
1062 static const u16 slv_snoc_bimc_rt_links[] = {
1063 QCM2290_MASTER_SNOC_BIMC_RT,
1064 };
1065
1066 static struct qcom_icc_node slv_snoc_bimc_rt = {
1067 .name = "slv_snoc_bimc_rt",
1068 .id = QCM2290_SLAVE_SNOC_BIMC_RT,
1069 .buswidth = 16,
1070 .qos.ap_owned = true,
1071 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1072 .mas_rpm_id = -1,
1073 .slv_rpm_id = 260,
1074 .num_links = ARRAY_SIZE(slv_snoc_bimc_rt_links),
1075 .links = slv_snoc_bimc_rt_links,
1076 };
1077
1078 static struct qcom_icc_node slv_appss = {
1079 .name = "slv_appss",
1080 .id = QCM2290_SLAVE_APPSS,
1081 .buswidth = 8,
1082 .qos.ap_owned = true,
1083 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1084 .mas_rpm_id = -1,
1085 .slv_rpm_id = 20,
1086 };
1087
1088 static const u16 slv_snoc_cnoc_links[] = {
1089 QCM2290_MASTER_SNOC_CNOC,
1090 };
1091
1092 static struct qcom_icc_node slv_snoc_cnoc = {
1093 .name = "slv_snoc_cnoc",
1094 .id = QCM2290_SLAVE_SNOC_CNOC,
1095 .buswidth = 8,
1096 .mas_rpm_id = -1,
1097 .slv_rpm_id = 25,
1098 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links),
1099 .links = slv_snoc_cnoc_links,
1100 };
1101
1102 static struct qcom_icc_node slv_imem = {
1103 .name = "slv_imem",
1104 .id = QCM2290_SLAVE_IMEM,
1105 .buswidth = 8,
1106 .mas_rpm_id = -1,
1107 .slv_rpm_id = 26,
1108 };
1109
1110 static struct qcom_icc_node slv_pimem = {
1111 .name = "slv_pimem",
1112 .id = QCM2290_SLAVE_PIMEM,
1113 .buswidth = 8,
1114 .qos.ap_owned = true,
1115 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1116 .mas_rpm_id = -1,
1117 .slv_rpm_id = 166,
1118 };
1119
1120 static const u16 slv_snoc_bimc_links[] = {
1121 QCM2290_MASTER_SNOC_BIMC,
1122 };
1123
1124 static struct qcom_icc_node slv_snoc_bimc = {
1125 .name = "slv_snoc_bimc",
1126 .id = QCM2290_SLAVE_SNOC_BIMC,
1127 .buswidth = 16,
1128 .mas_rpm_id = -1,
1129 .slv_rpm_id = 24,
1130 .num_links = ARRAY_SIZE(slv_snoc_bimc_links),
1131 .links = slv_snoc_bimc_links,
1132 };
1133
1134 static struct qcom_icc_node slv_service_snoc = {
1135 .name = "slv_service_snoc",
1136 .id = QCM2290_SLAVE_SERVICE_SNOC,
1137 .buswidth = 4,
1138 .qos.ap_owned = true,
1139 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1140 .mas_rpm_id = -1,
1141 .slv_rpm_id = 29,
1142 };
1143
1144 static struct qcom_icc_node slv_qdss_stm = {
1145 .name = "slv_qdss_stm",
1146 .id = QCM2290_SLAVE_QDSS_STM,
1147 .buswidth = 4,
1148 .mas_rpm_id = -1,
1149 .slv_rpm_id = 30,
1150 };
1151
1152 static struct qcom_icc_node slv_tcu = {
1153 .name = "slv_tcu",
1154 .id = QCM2290_SLAVE_TCU,
1155 .buswidth = 8,
1156 .qos.ap_owned = true,
1157 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1158 .mas_rpm_id = -1,
1159 .slv_rpm_id = 133,
1160 };
1161
1162 static const u16 slv_anoc_snoc_links[] = {
1163 QCM2290_MASTER_ANOC_SNOC,
1164 };
1165
1166 static struct qcom_icc_node slv_anoc_snoc = {
1167 .name = "slv_anoc_snoc",
1168 .id = QCM2290_SLAVE_ANOC_SNOC,
1169 .buswidth = 16,
1170 .mas_rpm_id = -1,
1171 .slv_rpm_id = 141,
1172 .num_links = ARRAY_SIZE(slv_anoc_snoc_links),
1173 .links = slv_anoc_snoc_links,
1174 };
1175
1176
1177 static struct qcom_icc_node * const qcm2290_bimc_nodes[] = {
1178 [MASTER_APPSS_PROC] = &mas_appss_proc,
1179 [MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt,
1180 [MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt,
1181 [MASTER_SNOC_BIMC] = &mas_snoc_bimc,
1182 [MASTER_TCU_0] = &mas_tcu_0,
1183 [MASTER_GFX3D] = &mas_gfx3d,
1184 [SLAVE_EBI1] = &slv_ebi1,
1185 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
1186 };
1187
1188 static const struct regmap_config qcm2290_bimc_regmap_config = {
1189 .reg_bits = 32,
1190 .reg_stride = 4,
1191 .val_bits = 32,
1192 .max_register = 0x80000,
1193 .fast_io = true,
1194 };
1195
1196 static const struct qcom_icc_desc qcm2290_bimc = {
1197 .type = QCOM_ICC_BIMC,
1198 .nodes = qcm2290_bimc_nodes,
1199 .num_nodes = ARRAY_SIZE(qcm2290_bimc_nodes),
1200 .regmap_cfg = &qcm2290_bimc_regmap_config,
1201
1202 .qos_offset = 0x8000,
1203 };
1204
1205 static struct qcom_icc_node * const qcm2290_cnoc_nodes[] = {
1206 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
1207 [MASTER_QDSS_DAP] = &mas_qdss_dap,
1208 [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1209 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &slv_camera_nrt_throttle_cfg,
1210 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &slv_camera_rt_throttle_cfg,
1211 [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1212 [SLAVE_CLK_CTL] = &slv_clk_ctl,
1213 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1214 [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1215 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
1216 [SLAVE_GPU_CFG] = &slv_gpu_cfg,
1217 [SLAVE_HWKM] = &slv_hwkm,
1218 [SLAVE_IMEM_CFG] = &slv_imem_cfg,
1219 [SLAVE_IPA_CFG] = &slv_ipa_cfg,
1220 [SLAVE_LPASS] = &slv_lpass,
1221 [SLAVE_MESSAGE_RAM] = &slv_message_ram,
1222 [SLAVE_PDM] = &slv_pdm,
1223 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
1224 [SLAVE_PKA_WRAPPER] = &slv_pka_wrapper,
1225 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1226 [SLAVE_PRNG] = &slv_prng,
1227 [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1228 [SLAVE_QM_CFG] = &slv_qm_cfg,
1229 [SLAVE_QM_MPU_CFG] = &slv_qm_mpu_cfg,
1230 [SLAVE_QPIC] = &slv_qpic,
1231 [SLAVE_QUP_0] = &slv_qup_0,
1232 [SLAVE_SDCC_1] = &slv_sdcc_1,
1233 [SLAVE_SDCC_2] = &slv_sdcc_2,
1234 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1235 [SLAVE_TCSR] = &slv_tcsr,
1236 [SLAVE_USB3] = &slv_usb3,
1237 [SLAVE_VENUS_CFG] = &slv_venus_cfg,
1238 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
1239 [SLAVE_VSENSE_CTRL_CFG] = &slv_vsense_ctrl_cfg,
1240 [SLAVE_SERVICE_CNOC] = &slv_service_cnoc,
1241 };
1242
1243 static const struct regmap_config qcm2290_cnoc_regmap_config = {
1244 .reg_bits = 32,
1245 .reg_stride = 4,
1246 .val_bits = 32,
1247 .max_register = 0x8200,
1248 .fast_io = true,
1249 };
1250
1251 static const struct qcom_icc_desc qcm2290_cnoc = {
1252 .type = QCOM_ICC_NOC,
1253 .nodes = qcm2290_cnoc_nodes,
1254 .num_nodes = ARRAY_SIZE(qcm2290_cnoc_nodes),
1255 .regmap_cfg = &qcm2290_cnoc_regmap_config,
1256 };
1257
1258 static struct qcom_icc_node * const qcm2290_snoc_nodes[] = {
1259 [MASTER_CRYPTO_CORE0] = &mas_crypto_core0,
1260 [MASTER_SNOC_CFG] = &mas_snoc_cfg,
1261 [MASTER_TIC] = &mas_tic,
1262 [MASTER_ANOC_SNOC] = &mas_anoc_snoc,
1263 [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
1264 [MASTER_PIMEM] = &mas_pimem,
1265 [MASTER_QDSS_BAM] = &mas_qdss_bam,
1266 [MASTER_QUP_0] = &mas_qup_0,
1267 [MASTER_IPA] = &mas_ipa,
1268 [MASTER_QDSS_ETR] = &mas_qdss_etr,
1269 [MASTER_SDCC_1] = &mas_sdcc_1,
1270 [MASTER_SDCC_2] = &mas_sdcc_2,
1271 [MASTER_QPIC] = &mas_qpic,
1272 [MASTER_USB3_0] = &mas_usb3_0,
1273 [SLAVE_APPSS] = &slv_appss,
1274 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
1275 [SLAVE_IMEM] = &slv_imem,
1276 [SLAVE_PIMEM] = &slv_pimem,
1277 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
1278 [SLAVE_SERVICE_SNOC] = &slv_service_snoc,
1279 [SLAVE_QDSS_STM] = &slv_qdss_stm,
1280 [SLAVE_TCU] = &slv_tcu,
1281 [SLAVE_ANOC_SNOC] = &slv_anoc_snoc,
1282 };
1283
1284 static const struct regmap_config qcm2290_snoc_regmap_config = {
1285 .reg_bits = 32,
1286 .reg_stride = 4,
1287 .val_bits = 32,
1288 .max_register = 0x60200,
1289 .fast_io = true,
1290 };
1291
1292 static const struct qcom_icc_desc qcm2290_snoc = {
1293 .type = QCOM_ICC_QNOC,
1294 .nodes = qcm2290_snoc_nodes,
1295 .num_nodes = ARRAY_SIZE(qcm2290_snoc_nodes),
1296 .regmap_cfg = &qcm2290_snoc_regmap_config,
1297
1298 .qos_offset = 0x15000,
1299 };
1300
1301 static struct qcom_icc_node * const qcm2290_qup_virt_nodes[] = {
1302 [MASTER_QUP_CORE_0] = &mas_qup_core_0,
1303 [SLAVE_QUP_CORE_0] = &slv_qup_core_0
1304 };
1305
1306 static const struct qcom_icc_desc qcm2290_qup_virt = {
1307 .type = QCOM_ICC_QNOC,
1308 .nodes = qcm2290_qup_virt_nodes,
1309 .num_nodes = ARRAY_SIZE(qcm2290_qup_virt_nodes),
1310 };
1311
1312 static struct qcom_icc_node * const qcm2290_mmnrt_virt_nodes[] = {
1313 [MASTER_CAMNOC_SF] = &mas_camnoc_sf,
1314 [MASTER_VIDEO_P0] = &mas_video_p0,
1315 [MASTER_VIDEO_PROC] = &mas_video_proc,
1316 [SLAVE_SNOC_BIMC_NRT] = &slv_snoc_bimc_nrt,
1317 };
1318
1319 static const struct qcom_icc_desc qcm2290_mmnrt_virt = {
1320 .type = QCOM_ICC_QNOC,
1321 .nodes = qcm2290_mmnrt_virt_nodes,
1322 .num_nodes = ARRAY_SIZE(qcm2290_mmnrt_virt_nodes),
1323 .regmap_cfg = &qcm2290_snoc_regmap_config,
1324 .qos_offset = 0x15000,
1325 };
1326
1327 static struct qcom_icc_node * const qcm2290_mmrt_virt_nodes[] = {
1328 [MASTER_CAMNOC_HF] = &mas_camnoc_hf,
1329 [MASTER_MDP0] = &mas_mdp0,
1330 [SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt,
1331 };
1332
1333 static const struct qcom_icc_desc qcm2290_mmrt_virt = {
1334 .type = QCOM_ICC_QNOC,
1335 .nodes = qcm2290_mmrt_virt_nodes,
1336 .num_nodes = ARRAY_SIZE(qcm2290_mmrt_virt_nodes),
1337 .regmap_cfg = &qcm2290_snoc_regmap_config,
1338 .qos_offset = 0x15000,
1339 };
1340
1341 static const struct of_device_id qcm2290_noc_of_match[] = {
1342 { .compatible = "qcom,qcm2290-bimc", .data = &qcm2290_bimc },
1343 { .compatible = "qcom,qcm2290-cnoc", .data = &qcm2290_cnoc },
1344 { .compatible = "qcom,qcm2290-snoc", .data = &qcm2290_snoc },
1345 { .compatible = "qcom,qcm2290-qup-virt", .data = &qcm2290_qup_virt },
1346 { .compatible = "qcom,qcm2290-mmrt-virt", .data = &qcm2290_mmrt_virt },
1347 { .compatible = "qcom,qcm2290-mmnrt-virt", .data = &qcm2290_mmnrt_virt },
1348 { },
1349 };
1350 MODULE_DEVICE_TABLE(of, qcm2290_noc_of_match);
1351
1352 static struct platform_driver qcm2290_noc_driver = {
1353 .probe = qnoc_probe,
1354 .remove = qnoc_remove,
1355 .driver = {
1356 .name = "qnoc-qcm2290",
1357 .of_match_table = qcm2290_noc_of_match,
1358 },
1359 };
1360 module_platform_driver(qcm2290_noc_driver);
1361
1362 MODULE_DESCRIPTION("Qualcomm QCM2290 NoC driver");
1363 MODULE_LICENSE("GPL v2");
