interconnect/qcom/msm8996.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Qualcomm MSM8996 Network-on-Chip (NoC) QoS driver
0004  *
0005  * Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com>
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/device.h>
0010 #include <linux/interconnect-provider.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/of_device.h>
0014 #include <linux/of_platform.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/regmap.h>
0017
0018 #include <dt-bindings/interconnect/qcom,msm8996.h>
0019
0020 #include "icc-rpm.h"
0021 #include "smd-rpm.h"
0022 #include "msm8996.h"
0023
0024 static const char * const bus_mm_clocks[] = {
0025     "bus",
0026     "bus_a",
0027     "iface"
0028 };
0029
0030 static const char * const bus_a0noc_clocks[] = {
0031     "aggre0_snoc_axi",
0032     "aggre0_cnoc_ahb",
0033     "aggre0_noc_mpu_cfg"
0034 };
0035
0036 static const u16 mas_a0noc_common_links[] = {
0037     MSM8996_SLAVE_A0NOC_SNOC
0038 };
0039
0040 static struct qcom_icc_node mas_pcie_0 = {
0041     .name = "mas_pcie_0",
0042     .id = MSM8996_MASTER_PCIE_0,
0043     .buswidth = 8,
0044     .mas_rpm_id = 65,
0045     .slv_rpm_id = -1,
0046     .qos.ap_owned = true,
0047     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0048     .qos.areq_prio = 1,
0049     .qos.prio_level = 1,
0050     .qos.qos_port = 0,
0051     .num_links = ARRAY_SIZE(mas_a0noc_common_links),
0052     .links = mas_a0noc_common_links
0053 };
0054
0055 static struct qcom_icc_node mas_pcie_1 = {
0056     .name = "mas_pcie_1",
0057     .id = MSM8996_MASTER_PCIE_1,
0058     .buswidth = 8,
0059     .mas_rpm_id = 66,
0060     .slv_rpm_id = -1,
0061     .qos.ap_owned = true,
0062     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0063     .qos.areq_prio = 1,
0064     .qos.prio_level = 1,
0065     .qos.qos_port = 1,
0066     .num_links = ARRAY_SIZE(mas_a0noc_common_links),
0067     .links = mas_a0noc_common_links
0068 };
0069
0070 static struct qcom_icc_node mas_pcie_2 = {
0071     .name = "mas_pcie_2",
0072     .id = MSM8996_MASTER_PCIE_2,
0073     .buswidth = 8,
0074     .mas_rpm_id = 119,
0075     .slv_rpm_id = -1,
0076     .qos.ap_owned = true,
0077     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0078     .qos.areq_prio = 1,
0079     .qos.prio_level = 1,
0080     .qos.qos_port = 2,
0081     .num_links = ARRAY_SIZE(mas_a0noc_common_links),
0082     .links = mas_a0noc_common_links
0083 };
0084
0085 static const u16 mas_a1noc_common_links[] = {
0086     MSM8996_SLAVE_A1NOC_SNOC
0087 };
0088
0089 static struct qcom_icc_node mas_cnoc_a1noc = {
0090     .name = "mas_cnoc_a1noc",
0091     .id = MSM8996_MASTER_CNOC_A1NOC,
0092     .buswidth = 8,
0093     .mas_rpm_id = 116,
0094     .slv_rpm_id = -1,
0095     .qos.ap_owned = true,
0096     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0097     .num_links = ARRAY_SIZE(mas_a1noc_common_links),
0098     .links = mas_a1noc_common_links
0099 };
0100
0101 static struct qcom_icc_node mas_crypto_c0 = {
0102     .name = "mas_crypto_c0",
0103     .id = MSM8996_MASTER_CRYPTO_CORE0,
0104     .buswidth = 8,
0105     .mas_rpm_id = 23,
0106     .slv_rpm_id = -1,
0107     .qos.ap_owned = true,
0108     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0109     .qos.areq_prio = 1,
0110     .qos.prio_level = 1,
0111     .qos.qos_port = 0,
0112     .num_links = ARRAY_SIZE(mas_a1noc_common_links),
0113     .links = mas_a1noc_common_links
0114 };
0115
0116 static struct qcom_icc_node mas_pnoc_a1noc = {
0117     .name = "mas_pnoc_a1noc",
0118     .id = MSM8996_MASTER_PNOC_A1NOC,
0119     .buswidth = 8,
0120     .mas_rpm_id = 117,
0121     .slv_rpm_id = -1,
0122     .qos.ap_owned = false,
0123     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0124     .qos.areq_prio = 0,
0125     .qos.prio_level = 0,
0126     .qos.qos_port = 1,
0127     .num_links = ARRAY_SIZE(mas_a1noc_common_links),
0128     .links = mas_a1noc_common_links
0129 };
0130
0131 static const u16 mas_a2noc_common_links[] = {
0132     MSM8996_SLAVE_A2NOC_SNOC
0133 };
0134
0135 static struct qcom_icc_node mas_usb3 = {
0136     .name = "mas_usb3",
0137     .id = MSM8996_MASTER_USB3,
0138     .buswidth = 8,
0139     .mas_rpm_id = 32,
0140     .slv_rpm_id = -1,
0141     .qos.ap_owned = true,
0142     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0143     .qos.areq_prio = 1,
0144     .qos.prio_level = 1,
0145     .qos.qos_port = 3,
0146     .num_links = ARRAY_SIZE(mas_a2noc_common_links),
0147     .links = mas_a2noc_common_links
0148 };
0149
0150 static struct qcom_icc_node mas_ipa = {
0151     .name = "mas_ipa",
0152     .id = MSM8996_MASTER_IPA,
0153     .buswidth = 8,
0154     .mas_rpm_id = 59,
0155     .slv_rpm_id = -1,
0156     .qos.ap_owned = true,
0157     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0158     .qos.areq_prio = 0,
0159     .qos.prio_level = 0,
0160     .qos.qos_port = -1,
0161     .num_links = ARRAY_SIZE(mas_a2noc_common_links),
0162     .links = mas_a2noc_common_links
0163 };
0164
0165 static struct qcom_icc_node mas_ufs = {
0166     .name = "mas_ufs",
0167     .id = MSM8996_MASTER_UFS,
0168     .buswidth = 8,
0169     .mas_rpm_id = 68,
0170     .slv_rpm_id = -1,
0171     .qos.ap_owned = true,
0172     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0173     .qos.areq_prio = 1,
0174     .qos.prio_level = 1,
0175     .qos.qos_port = 2,
0176     .num_links = ARRAY_SIZE(mas_a2noc_common_links),
0177     .links = mas_a2noc_common_links
0178 };
0179
0180 static const u16 mas_apps_proc_links[] = {
0181     MSM8996_SLAVE_BIMC_SNOC_1,
0182     MSM8996_SLAVE_EBI_CH0,
0183     MSM8996_SLAVE_BIMC_SNOC_0
0184 };
0185
0186 static struct qcom_icc_node mas_apps_proc = {
0187     .name = "mas_apps_proc",
0188     .id = MSM8996_MASTER_AMPSS_M0,
0189     .buswidth = 8,
0190     .mas_rpm_id = 0,
0191     .slv_rpm_id = -1,
0192     .qos.ap_owned = true,
0193     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0194     .qos.areq_prio = 0,
0195     .qos.prio_level = 0,
0196     .qos.qos_port = 0,
0197     .num_links = ARRAY_SIZE(mas_apps_proc_links),
0198     .links = mas_apps_proc_links
0199 };
0200
0201 static const u16 mas_oxili_common_links[] = {
0202     MSM8996_SLAVE_BIMC_SNOC_1,
0203     MSM8996_SLAVE_HMSS_L3,
0204     MSM8996_SLAVE_EBI_CH0,
0205     MSM8996_SLAVE_BIMC_SNOC_0
0206 };
0207
0208 static struct qcom_icc_node mas_oxili = {
0209     .name = "mas_oxili",
0210     .id = MSM8996_MASTER_GRAPHICS_3D,
0211     .buswidth = 8,
0212     .mas_rpm_id = 6,
0213     .slv_rpm_id = -1,
0214     .qos.ap_owned = true,
0215     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0216     .qos.areq_prio = 0,
0217     .qos.prio_level = 0,
0218     .qos.qos_port = 1,
0219     .num_links = ARRAY_SIZE(mas_oxili_common_links),
0220     .links = mas_oxili_common_links
0221 };
0222
0223 static struct qcom_icc_node mas_mnoc_bimc = {
0224     .name = "mas_mnoc_bimc",
0225     .id = MSM8996_MASTER_MNOC_BIMC,
0226     .buswidth = 8,
0227     .mas_rpm_id = 2,
0228     .slv_rpm_id = -1,
0229     .qos.ap_owned = true,
0230     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0231     .qos.areq_prio = 0,
0232     .qos.prio_level = 0,
0233     .qos.qos_port = 2,
0234     .num_links = ARRAY_SIZE(mas_oxili_common_links),
0235     .links = mas_oxili_common_links
0236 };
0237
0238 static const u16 mas_snoc_bimc_links[] = {
0239     MSM8996_SLAVE_HMSS_L3,
0240     MSM8996_SLAVE_EBI_CH0
0241 };
0242
0243 static struct qcom_icc_node mas_snoc_bimc = {
0244     .name = "mas_snoc_bimc",
0245     .id = MSM8996_MASTER_SNOC_BIMC,
0246     .buswidth = 8,
0247     .mas_rpm_id = 3,
0248     .slv_rpm_id = -1,
0249     .qos.ap_owned = false,
0250     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0251     .qos.areq_prio = 0,
0252     .qos.prio_level = 0,
0253     .qos.qos_port = -1,
0254     .num_links = ARRAY_SIZE(mas_snoc_bimc_links),
0255     .links = mas_snoc_bimc_links
0256 };
0257
0258 static const u16 mas_snoc_cnoc_links[] = {
0259     MSM8996_SLAVE_CLK_CTL,
0260     MSM8996_SLAVE_RBCPR_CX,
0261     MSM8996_SLAVE_A2NOC_SMMU_CFG,
0262     MSM8996_SLAVE_A0NOC_MPU_CFG,
0263     MSM8996_SLAVE_MESSAGE_RAM,
0264     MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
0265     MSM8996_SLAVE_PCIE_0_CFG,
0266     MSM8996_SLAVE_TLMM,
0267     MSM8996_SLAVE_MPM,
0268     MSM8996_SLAVE_A0NOC_SMMU_CFG,
0269     MSM8996_SLAVE_EBI1_PHY_CFG,
0270     MSM8996_SLAVE_BIMC_CFG,
0271     MSM8996_SLAVE_PIMEM_CFG,
0272     MSM8996_SLAVE_RBCPR_MX,
0273     MSM8996_SLAVE_PRNG,
0274     MSM8996_SLAVE_PCIE20_AHB2PHY,
0275     MSM8996_SLAVE_A2NOC_MPU_CFG,
0276     MSM8996_SLAVE_QDSS_CFG,
0277     MSM8996_SLAVE_A2NOC_CFG,
0278     MSM8996_SLAVE_A0NOC_CFG,
0279     MSM8996_SLAVE_UFS_CFG,
0280     MSM8996_SLAVE_CRYPTO_0_CFG,
0281     MSM8996_SLAVE_PCIE_1_CFG,
0282     MSM8996_SLAVE_SNOC_CFG,
0283     MSM8996_SLAVE_SNOC_MPU_CFG,
0284     MSM8996_SLAVE_A1NOC_MPU_CFG,
0285     MSM8996_SLAVE_A1NOC_SMMU_CFG,
0286     MSM8996_SLAVE_PCIE_2_CFG,
0287     MSM8996_SLAVE_CNOC_MNOC_CFG,
0288     MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
0289     MSM8996_SLAVE_PMIC_ARB,
0290     MSM8996_SLAVE_IMEM_CFG,
0291     MSM8996_SLAVE_A1NOC_CFG,
0292     MSM8996_SLAVE_SSC_CFG,
0293     MSM8996_SLAVE_TCSR,
0294     MSM8996_SLAVE_LPASS_SMMU_CFG,
0295     MSM8996_SLAVE_DCC_CFG
0296 };
0297
0298 static struct qcom_icc_node mas_snoc_cnoc = {
0299     .name = "mas_snoc_cnoc",
0300     .id = MSM8996_MASTER_SNOC_CNOC,
0301     .buswidth = 8,
0302     .mas_rpm_id = 52,
0303     .slv_rpm_id = -1,
0304     .num_links = ARRAY_SIZE(mas_snoc_cnoc_links),
0305     .links = mas_snoc_cnoc_links
0306 };
0307
0308 static const u16 mas_qdss_dap_links[] = {
0309     MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
0310     MSM8996_SLAVE_RBCPR_CX,
0311     MSM8996_SLAVE_A2NOC_SMMU_CFG,
0312     MSM8996_SLAVE_A0NOC_MPU_CFG,
0313     MSM8996_SLAVE_MESSAGE_RAM,
0314     MSM8996_SLAVE_PCIE_0_CFG,
0315     MSM8996_SLAVE_TLMM,
0316     MSM8996_SLAVE_MPM,
0317     MSM8996_SLAVE_A0NOC_SMMU_CFG,
0318     MSM8996_SLAVE_EBI1_PHY_CFG,
0319     MSM8996_SLAVE_BIMC_CFG,
0320     MSM8996_SLAVE_PIMEM_CFG,
0321     MSM8996_SLAVE_RBCPR_MX,
0322     MSM8996_SLAVE_CLK_CTL,
0323     MSM8996_SLAVE_PRNG,
0324     MSM8996_SLAVE_PCIE20_AHB2PHY,
0325     MSM8996_SLAVE_A2NOC_MPU_CFG,
0326     MSM8996_SLAVE_QDSS_CFG,
0327     MSM8996_SLAVE_A2NOC_CFG,
0328     MSM8996_SLAVE_A0NOC_CFG,
0329     MSM8996_SLAVE_UFS_CFG,
0330     MSM8996_SLAVE_CRYPTO_0_CFG,
0331     MSM8996_SLAVE_CNOC_A1NOC,
0332     MSM8996_SLAVE_PCIE_1_CFG,
0333     MSM8996_SLAVE_SNOC_CFG,
0334     MSM8996_SLAVE_SNOC_MPU_CFG,
0335     MSM8996_SLAVE_A1NOC_MPU_CFG,
0336     MSM8996_SLAVE_A1NOC_SMMU_CFG,
0337     MSM8996_SLAVE_PCIE_2_CFG,
0338     MSM8996_SLAVE_CNOC_MNOC_CFG,
0339     MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
0340     MSM8996_SLAVE_PMIC_ARB,
0341     MSM8996_SLAVE_IMEM_CFG,
0342     MSM8996_SLAVE_A1NOC_CFG,
0343     MSM8996_SLAVE_SSC_CFG,
0344     MSM8996_SLAVE_TCSR,
0345     MSM8996_SLAVE_LPASS_SMMU_CFG,
0346     MSM8996_SLAVE_DCC_CFG
0347 };
0348
0349 static struct qcom_icc_node mas_qdss_dap = {
0350     .name = "mas_qdss_dap",
0351     .id = MSM8996_MASTER_QDSS_DAP,
0352     .buswidth = 8,
0353     .mas_rpm_id = 49,
0354     .slv_rpm_id = -1,
0355     .qos.ap_owned = true,
0356     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0357     .num_links = ARRAY_SIZE(mas_qdss_dap_links),
0358     .links = mas_qdss_dap_links
0359 };
0360
0361 static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = {
0362     MSM8996_SLAVE_MMAGIC_CFG,
0363     MSM8996_SLAVE_DSA_MPU_CFG,
0364     MSM8996_SLAVE_MMSS_CLK_CFG,
0365     MSM8996_SLAVE_CAMERA_THROTTLE_CFG,
0366     MSM8996_SLAVE_VENUS_CFG,
0367     MSM8996_SLAVE_SMMU_VFE_CFG,
0368     MSM8996_SLAVE_MISC_CFG,
0369     MSM8996_SLAVE_SMMU_CPP_CFG,
0370     MSM8996_SLAVE_GRAPHICS_3D_CFG,
0371     MSM8996_SLAVE_DISPLAY_THROTTLE_CFG,
0372     MSM8996_SLAVE_VENUS_THROTTLE_CFG,
0373     MSM8996_SLAVE_CAMERA_CFG,
0374     MSM8996_SLAVE_DISPLAY_CFG,
0375     MSM8996_SLAVE_CPR_CFG,
0376     MSM8996_SLAVE_SMMU_ROTATOR_CFG,
0377     MSM8996_SLAVE_DSA_CFG,
0378     MSM8996_SLAVE_SMMU_VENUS_CFG,
0379     MSM8996_SLAVE_VMEM_CFG,
0380     MSM8996_SLAVE_SMMU_JPEG_CFG,
0381     MSM8996_SLAVE_SMMU_MDP_CFG,
0382     MSM8996_SLAVE_MNOC_MPU_CFG
0383 };
0384
0385 static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = {
0386     .name = "mas_cnoc_mnoc_mmss_cfg",
0387     .id = MSM8996_MASTER_CNOC_MNOC_MMSS_CFG,
0388     .buswidth = 8,
0389     .mas_rpm_id = 4,
0390     .slv_rpm_id = -1,
0391     .qos.ap_owned = true,
0392     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0393     .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links),
0394     .links = mas_cnoc_mnoc_mmss_cfg_links
0395 };
0396
0397 static const u16 mas_cnoc_mnoc_cfg_links[] = {
0398     MSM8996_SLAVE_SERVICE_MNOC
0399 };
0400
0401 static struct qcom_icc_node mas_cnoc_mnoc_cfg = {
0402     .name = "mas_cnoc_mnoc_cfg",
0403     .id = MSM8996_MASTER_CNOC_MNOC_CFG,
0404     .buswidth = 8,
0405     .mas_rpm_id = 5,
0406     .slv_rpm_id = -1,
0407     .qos.ap_owned = true,
0408     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0409     .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links),
0410     .links = mas_cnoc_mnoc_cfg_links
0411 };
0412
0413 static const u16 mas_mnoc_bimc_common_links[] = {
0414     MSM8996_SLAVE_MNOC_BIMC
0415 };
0416
0417 static struct qcom_icc_node mas_cpp = {
0418     .name = "mas_cpp",
0419     .id = MSM8996_MASTER_CPP,
0420     .buswidth = 32,
0421     .mas_rpm_id = 115,
0422     .slv_rpm_id = -1,
0423     .qos.ap_owned = true,
0424     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0425     .qos.areq_prio = 0,
0426     .qos.prio_level = 0,
0427     .qos.qos_port = 5,
0428     .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
0429     .links = mas_mnoc_bimc_common_links
0430 };
0431
0432 static struct qcom_icc_node mas_jpeg = {
0433     .name = "mas_jpeg",
0434     .id = MSM8996_MASTER_JPEG,
0435     .buswidth = 32,
0436     .mas_rpm_id = 7,
0437     .slv_rpm_id = -1,
0438     .qos.ap_owned = true,
0439     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0440     .qos.areq_prio = 0,
0441     .qos.prio_level = 0,
0442     .qos.qos_port = 7,
0443     .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
0444     .links = mas_mnoc_bimc_common_links
0445 };
0446
0447 static struct qcom_icc_node mas_mdp_p0 = {
0448     .name = "mas_mdp_p0",
0449     .id = MSM8996_MASTER_MDP_PORT0,
0450     .buswidth = 32,
0451     .mas_rpm_id = 8,
0452     .slv_rpm_id = -1,
0453     .qos.ap_owned = true,
0454     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0455     .qos.areq_prio = 0,
0456     .qos.prio_level = 0,
0457     .qos.qos_port = 1,
0458     .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
0459     .links = mas_mnoc_bimc_common_links
0460 };
0461
0462 static struct qcom_icc_node mas_mdp_p1 = {
0463     .name = "mas_mdp_p1",
0464     .id = MSM8996_MASTER_MDP_PORT1,
0465     .buswidth = 32,
0466     .mas_rpm_id = 61,
0467     .slv_rpm_id = -1,
0468     .qos.ap_owned = true,
0469     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0470     .qos.areq_prio = 0,
0471     .qos.prio_level = 0,
0472     .qos.qos_port = 2,
0473     .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
0474     .links = mas_mnoc_bimc_common_links
0475 };
0476
0477 static struct qcom_icc_node mas_rotator = {
0478     .name = "mas_rotator",
0479     .id = MSM8996_MASTER_ROTATOR,
0480     .buswidth = 32,
0481     .mas_rpm_id = 120,
0482     .slv_rpm_id = -1,
0483     .qos.ap_owned = true,
0484     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0485     .qos.areq_prio = 0,
0486     .qos.prio_level = 0,
0487     .qos.qos_port = 0,
0488     .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
0489     .links = mas_mnoc_bimc_common_links
0490 };
0491
0492 static struct qcom_icc_node mas_venus = {
0493     .name = "mas_venus",
0494     .id = MSM8996_MASTER_VIDEO_P0,
0495     .buswidth = 32,
0496     .mas_rpm_id = 9,
0497     .slv_rpm_id = -1,
0498     .qos.ap_owned = true,
0499     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0500     .qos.areq_prio = 0,
0501     .qos.prio_level = 0,
0502     .qos.qos_port = 3,
0503     .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
0504     .links = mas_mnoc_bimc_common_links
0505 };
0506
0507 static struct qcom_icc_node mas_vfe = {
0508     .name = "mas_vfe",
0509     .id = MSM8996_MASTER_VFE,
0510     .buswidth = 32,
0511     .mas_rpm_id = 11,
0512     .slv_rpm_id = -1,
0513     .qos.ap_owned = true,
0514     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0515     .qos.areq_prio = 0,
0516     .qos.prio_level = 0,
0517     .qos.qos_port = 6,
0518     .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links),
0519     .links = mas_mnoc_bimc_common_links
0520 };
0521
0522 static const u16 mas_vmem_common_links[] = {
0523     MSM8996_SLAVE_VMEM
0524 };
0525
0526 static struct qcom_icc_node mas_snoc_vmem = {
0527     .name = "mas_snoc_vmem",
0528     .id = MSM8996_MASTER_SNOC_VMEM,
0529     .buswidth = 32,
0530     .mas_rpm_id = 114,
0531     .slv_rpm_id = -1,
0532     .qos.ap_owned = true,
0533     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0534     .num_links = ARRAY_SIZE(mas_vmem_common_links),
0535     .links = mas_vmem_common_links
0536 };
0537
0538 static struct qcom_icc_node mas_venus_vmem = {
0539     .name = "mas_venus_vmem",
0540     .id = MSM8996_MASTER_VIDEO_P0_OCMEM,
0541     .buswidth = 32,
0542     .mas_rpm_id = 121,
0543     .slv_rpm_id = -1,
0544     .qos.ap_owned = true,
0545     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0546     .num_links = ARRAY_SIZE(mas_vmem_common_links),
0547     .links = mas_vmem_common_links
0548 };
0549
0550 static const u16 mas_snoc_pnoc_links[] = {
0551     MSM8996_SLAVE_BLSP_1,
0552     MSM8996_SLAVE_BLSP_2,
0553     MSM8996_SLAVE_SDCC_1,
0554     MSM8996_SLAVE_SDCC_2,
0555     MSM8996_SLAVE_SDCC_4,
0556     MSM8996_SLAVE_TSIF,
0557     MSM8996_SLAVE_PDM,
0558     MSM8996_SLAVE_AHB2PHY
0559 };
0560
0561 static struct qcom_icc_node mas_snoc_pnoc = {
0562     .name = "mas_snoc_pnoc",
0563     .id = MSM8996_MASTER_SNOC_PNOC,
0564     .buswidth = 8,
0565     .mas_rpm_id = 44,
0566     .slv_rpm_id = -1,
0567     .num_links = ARRAY_SIZE(mas_snoc_pnoc_links),
0568     .links = mas_snoc_pnoc_links
0569 };
0570
0571 static const u16 mas_pnoc_a1noc_common_links[] = {
0572     MSM8996_SLAVE_PNOC_A1NOC
0573 };
0574
0575 static struct qcom_icc_node mas_sdcc_1 = {
0576     .name = "mas_sdcc_1",
0577     .id = MSM8996_MASTER_SDCC_1,
0578     .buswidth = 8,
0579     .mas_rpm_id = 33,
0580     .slv_rpm_id = -1,
0581     .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
0582     .links = mas_pnoc_a1noc_common_links
0583 };
0584
0585 static struct qcom_icc_node mas_sdcc_2 = {
0586     .name = "mas_sdcc_2",
0587     .id = MSM8996_MASTER_SDCC_2,
0588     .buswidth = 8,
0589     .mas_rpm_id = 35,
0590     .slv_rpm_id = -1,
0591     .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
0592     .links = mas_pnoc_a1noc_common_links
0593 };
0594
0595 static struct qcom_icc_node mas_sdcc_4 = {
0596     .name = "mas_sdcc_4",
0597     .id = MSM8996_MASTER_SDCC_4,
0598     .buswidth = 8,
0599     .mas_rpm_id = 36,
0600     .slv_rpm_id = -1,
0601     .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
0602     .links = mas_pnoc_a1noc_common_links
0603 };
0604
0605 static struct qcom_icc_node mas_usb_hs = {
0606     .name = "mas_usb_hs",
0607     .id = MSM8996_MASTER_USB_HS,
0608     .buswidth = 8,
0609     .mas_rpm_id = 42,
0610     .slv_rpm_id = -1,
0611     .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
0612     .links = mas_pnoc_a1noc_common_links
0613 };
0614
0615 static struct qcom_icc_node mas_blsp_1 = {
0616     .name = "mas_blsp_1",
0617     .id = MSM8996_MASTER_BLSP_1,
0618     .buswidth = 4,
0619     .mas_rpm_id = 41,
0620     .slv_rpm_id = -1,
0621     .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
0622     .links = mas_pnoc_a1noc_common_links
0623 };
0624
0625 static struct qcom_icc_node mas_blsp_2 = {
0626     .name = "mas_blsp_2",
0627     .id = MSM8996_MASTER_BLSP_2,
0628     .buswidth = 4,
0629     .mas_rpm_id = 39,
0630     .slv_rpm_id = -1,
0631     .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
0632     .links = mas_pnoc_a1noc_common_links
0633 };
0634
0635 static struct qcom_icc_node mas_tsif = {
0636     .name = "mas_tsif",
0637     .id = MSM8996_MASTER_TSIF,
0638     .buswidth = 4,
0639     .mas_rpm_id = 37,
0640     .slv_rpm_id = -1,
0641     .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links),
0642     .links = mas_pnoc_a1noc_common_links
0643 };
0644
0645 static const u16 mas_hmss_links[] = {
0646     MSM8996_SLAVE_PIMEM,
0647     MSM8996_SLAVE_OCIMEM,
0648     MSM8996_SLAVE_SNOC_BIMC
0649 };
0650
0651 static struct qcom_icc_node mas_hmss = {
0652     .name = "mas_hmss",
0653     .id = MSM8996_MASTER_HMSS,
0654     .buswidth = 8,
0655     .mas_rpm_id = 118,
0656     .slv_rpm_id = -1,
0657     .qos.ap_owned = true,
0658     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0659     .qos.areq_prio = 1,
0660     .qos.prio_level = 1,
0661     .qos.qos_port = 4,
0662     .num_links = ARRAY_SIZE(mas_hmss_links),
0663     .links = mas_hmss_links
0664 };
0665
0666 static const u16 mas_qdss_common_links[] = {
0667     MSM8996_SLAVE_PIMEM,
0668     MSM8996_SLAVE_USB3,
0669     MSM8996_SLAVE_OCIMEM,
0670     MSM8996_SLAVE_SNOC_BIMC,
0671     MSM8996_SLAVE_SNOC_PNOC
0672 };
0673
0674 static struct qcom_icc_node mas_qdss_bam = {
0675     .name = "mas_qdss_bam",
0676     .id = MSM8996_MASTER_QDSS_BAM,
0677     .buswidth = 16,
0678     .mas_rpm_id = 19,
0679     .slv_rpm_id = -1,
0680     .qos.ap_owned = true,
0681     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0682     .qos.areq_prio = 1,
0683     .qos.prio_level = 1,
0684     .qos.qos_port = 2,
0685     .num_links = ARRAY_SIZE(mas_qdss_common_links),
0686     .links = mas_qdss_common_links
0687 };
0688
0689 static const u16 mas_snoc_cfg_links[] = {
0690     MSM8996_SLAVE_SERVICE_SNOC
0691 };
0692
0693 static struct qcom_icc_node mas_snoc_cfg = {
0694     .name = "mas_snoc_cfg",
0695     .id = MSM8996_MASTER_SNOC_CFG,
0696     .buswidth = 16,
0697     .mas_rpm_id = 20,
0698     .slv_rpm_id = -1,
0699     .qos.ap_owned = true,
0700     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0701     .num_links = ARRAY_SIZE(mas_snoc_cfg_links),
0702     .links = mas_snoc_cfg_links
0703 };
0704
0705 static const u16 mas_bimc_snoc_0_links[] = {
0706     MSM8996_SLAVE_SNOC_VMEM,
0707     MSM8996_SLAVE_USB3,
0708     MSM8996_SLAVE_PIMEM,
0709     MSM8996_SLAVE_LPASS,
0710     MSM8996_SLAVE_APPSS,
0711     MSM8996_SLAVE_SNOC_CNOC,
0712     MSM8996_SLAVE_SNOC_PNOC,
0713     MSM8996_SLAVE_OCIMEM,
0714     MSM8996_SLAVE_QDSS_STM
0715 };
0716
0717 static struct qcom_icc_node mas_bimc_snoc_0 = {
0718     .name = "mas_bimc_snoc_0",
0719     .id = MSM8996_MASTER_BIMC_SNOC_0,
0720     .buswidth = 16,
0721     .mas_rpm_id = 21,
0722     .slv_rpm_id = -1,
0723     .qos.ap_owned = true,
0724     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0725     .num_links = ARRAY_SIZE(mas_bimc_snoc_0_links),
0726     .links = mas_bimc_snoc_0_links
0727 };
0728
0729 static const u16 mas_bimc_snoc_1_links[] = {
0730     MSM8996_SLAVE_PCIE_2,
0731     MSM8996_SLAVE_PCIE_1,
0732     MSM8996_SLAVE_PCIE_0
0733 };
0734
0735 static struct qcom_icc_node mas_bimc_snoc_1 = {
0736     .name = "mas_bimc_snoc_1",
0737     .id = MSM8996_MASTER_BIMC_SNOC_1,
0738     .buswidth = 16,
0739     .mas_rpm_id = 109,
0740     .slv_rpm_id = -1,
0741     .qos.ap_owned = true,
0742     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0743     .num_links = ARRAY_SIZE(mas_bimc_snoc_1_links),
0744     .links = mas_bimc_snoc_1_links
0745 };
0746
0747 static const u16 mas_a0noc_snoc_links[] = {
0748     MSM8996_SLAVE_SNOC_PNOC,
0749     MSM8996_SLAVE_OCIMEM,
0750     MSM8996_SLAVE_APPSS,
0751     MSM8996_SLAVE_SNOC_BIMC,
0752     MSM8996_SLAVE_PIMEM
0753 };
0754
0755 static struct qcom_icc_node mas_a0noc_snoc = {
0756     .name = "mas_a0noc_snoc",
0757     .id = MSM8996_MASTER_A0NOC_SNOC,
0758     .buswidth = 16,
0759     .mas_rpm_id = 110,
0760     .slv_rpm_id = -1,
0761     .qos.ap_owned = true,
0762     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0763     .num_links = ARRAY_SIZE(mas_a0noc_snoc_links),
0764     .links = mas_a0noc_snoc_links
0765 };
0766
0767 static const u16 mas_a1noc_snoc_links[] = {
0768     MSM8996_SLAVE_SNOC_VMEM,
0769     MSM8996_SLAVE_USB3,
0770     MSM8996_SLAVE_PCIE_0,
0771     MSM8996_SLAVE_PIMEM,
0772     MSM8996_SLAVE_PCIE_2,
0773     MSM8996_SLAVE_LPASS,
0774     MSM8996_SLAVE_PCIE_1,
0775     MSM8996_SLAVE_APPSS,
0776     MSM8996_SLAVE_SNOC_BIMC,
0777     MSM8996_SLAVE_SNOC_CNOC,
0778     MSM8996_SLAVE_SNOC_PNOC,
0779     MSM8996_SLAVE_OCIMEM,
0780     MSM8996_SLAVE_QDSS_STM
0781 };
0782
0783 static struct qcom_icc_node mas_a1noc_snoc = {
0784     .name = "mas_a1noc_snoc",
0785     .id = MSM8996_MASTER_A1NOC_SNOC,
0786     .buswidth = 16,
0787     .mas_rpm_id = 111,
0788     .slv_rpm_id = -1,
0789     .num_links = ARRAY_SIZE(mas_a1noc_snoc_links),
0790     .links = mas_a1noc_snoc_links
0791 };
0792
0793 static const u16 mas_a2noc_snoc_links[] = {
0794     MSM8996_SLAVE_SNOC_VMEM,
0795     MSM8996_SLAVE_USB3,
0796     MSM8996_SLAVE_PCIE_1,
0797     MSM8996_SLAVE_PIMEM,
0798     MSM8996_SLAVE_PCIE_2,
0799     MSM8996_SLAVE_QDSS_STM,
0800     MSM8996_SLAVE_LPASS,
0801     MSM8996_SLAVE_SNOC_BIMC,
0802     MSM8996_SLAVE_SNOC_CNOC,
0803     MSM8996_SLAVE_SNOC_PNOC,
0804     MSM8996_SLAVE_OCIMEM,
0805     MSM8996_SLAVE_PCIE_0
0806 };
0807
0808 static struct qcom_icc_node mas_a2noc_snoc = {
0809     .name = "mas_a2noc_snoc",
0810     .id = MSM8996_MASTER_A2NOC_SNOC,
0811     .buswidth = 16,
0812     .mas_rpm_id = 112,
0813     .slv_rpm_id = -1,
0814     .num_links = ARRAY_SIZE(mas_a2noc_snoc_links),
0815     .links = mas_a2noc_snoc_links
0816 };
0817
0818 static struct qcom_icc_node mas_qdss_etr = {
0819     .name = "mas_qdss_etr",
0820     .id = MSM8996_MASTER_QDSS_ETR,
0821     .buswidth = 16,
0822     .mas_rpm_id = 31,
0823     .slv_rpm_id = -1,
0824     .qos.ap_owned = true,
0825     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0826     .qos.areq_prio = 1,
0827     .qos.prio_level = 1,
0828     .qos.qos_port = 3,
0829     .num_links = ARRAY_SIZE(mas_qdss_common_links),
0830     .links = mas_qdss_common_links
0831 };
0832
0833 static const u16 slv_a0noc_snoc_links[] = {
0834     MSM8996_MASTER_A0NOC_SNOC
0835 };
0836
0837 static struct qcom_icc_node slv_a0noc_snoc = {
0838     .name = "slv_a0noc_snoc",
0839     .id = MSM8996_SLAVE_A0NOC_SNOC,
0840     .buswidth = 8,
0841     .mas_rpm_id = -1,
0842     .slv_rpm_id = 141,
0843     .qos.ap_owned = true,
0844     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0845     .num_links = ARRAY_SIZE(slv_a0noc_snoc_links),
0846     .links = slv_a0noc_snoc_links
0847 };
0848
0849 static const u16 slv_a1noc_snoc_links[] = {
0850     MSM8996_MASTER_A1NOC_SNOC
0851 };
0852
0853 static struct qcom_icc_node slv_a1noc_snoc = {
0854     .name = "slv_a1noc_snoc",
0855     .id = MSM8996_SLAVE_A1NOC_SNOC,
0856     .buswidth = 8,
0857     .mas_rpm_id = -1,
0858     .slv_rpm_id = 142,
0859     .num_links = ARRAY_SIZE(slv_a1noc_snoc_links),
0860     .links = slv_a1noc_snoc_links
0861 };
0862
0863 static const u16 slv_a2noc_snoc_links[] = {
0864     MSM8996_MASTER_A2NOC_SNOC
0865 };
0866
0867 static struct qcom_icc_node slv_a2noc_snoc = {
0868     .name = "slv_a2noc_snoc",
0869     .id = MSM8996_SLAVE_A2NOC_SNOC,
0870     .buswidth = 8,
0871     .mas_rpm_id = -1,
0872     .slv_rpm_id = 143,
0873     .num_links = ARRAY_SIZE(slv_a2noc_snoc_links),
0874     .links = slv_a2noc_snoc_links
0875 };
0876
0877 static struct qcom_icc_node slv_ebi = {
0878     .name = "slv_ebi",
0879     .id = MSM8996_SLAVE_EBI_CH0,
0880     .buswidth = 8,
0881     .mas_rpm_id = -1,
0882     .slv_rpm_id = 0
0883 };
0884
0885 static struct qcom_icc_node slv_hmss_l3 = {
0886     .name = "slv_hmss_l3",
0887     .id = MSM8996_SLAVE_HMSS_L3,
0888     .buswidth = 8,
0889     .mas_rpm_id = -1,
0890     .slv_rpm_id = 160
0891 };
0892
0893 static const u16 slv_bimc_snoc_0_links[] = {
0894     MSM8996_MASTER_BIMC_SNOC_0
0895 };
0896
0897 static struct qcom_icc_node slv_bimc_snoc_0 = {
0898     .name = "slv_bimc_snoc_0",
0899     .id = MSM8996_SLAVE_BIMC_SNOC_0,
0900     .buswidth = 8,
0901     .mas_rpm_id = -1,
0902     .slv_rpm_id = 2,
0903     .qos.ap_owned = true,
0904     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0905     .num_links = ARRAY_SIZE(slv_bimc_snoc_0_links),
0906     .links = slv_bimc_snoc_0_links
0907 };
0908
0909 static const u16 slv_bimc_snoc_1_links[] = {
0910     MSM8996_MASTER_BIMC_SNOC_1
0911 };
0912
0913 static struct qcom_icc_node slv_bimc_snoc_1 = {
0914     .name = "slv_bimc_snoc_1",
0915     .id = MSM8996_SLAVE_BIMC_SNOC_1,
0916     .buswidth = 8,
0917     .mas_rpm_id = -1,
0918     .slv_rpm_id = 138,
0919     .qos.ap_owned = true,
0920     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0921     .num_links = ARRAY_SIZE(slv_bimc_snoc_1_links),
0922     .links = slv_bimc_snoc_1_links
0923 };
0924
0925 static const u16 slv_cnoc_a1noc_links[] = {
0926     MSM8996_MASTER_CNOC_A1NOC
0927 };
0928
0929 static struct qcom_icc_node slv_cnoc_a1noc = {
0930     .name = "slv_cnoc_a1noc",
0931     .id = MSM8996_SLAVE_CNOC_A1NOC,
0932     .buswidth = 4,
0933     .mas_rpm_id = -1,
0934     .slv_rpm_id = 75,
0935     .qos.ap_owned = true,
0936     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0937     .num_links = ARRAY_SIZE(slv_cnoc_a1noc_links),
0938     .links = slv_cnoc_a1noc_links
0939 };
0940
0941 static struct qcom_icc_node slv_clk_ctl = {
0942     .name = "slv_clk_ctl",
0943     .id = MSM8996_SLAVE_CLK_CTL,
0944     .buswidth = 4,
0945     .mas_rpm_id = -1,
0946     .slv_rpm_id = 47
0947 };
0948
0949 static struct qcom_icc_node slv_tcsr = {
0950     .name = "slv_tcsr",
0951     .id = MSM8996_SLAVE_TCSR,
0952     .buswidth = 4,
0953     .mas_rpm_id = -1,
0954     .slv_rpm_id = 50
0955 };
0956
0957 static struct qcom_icc_node slv_tlmm = {
0958     .name = "slv_tlmm",
0959     .id = MSM8996_SLAVE_TLMM,
0960     .buswidth = 4,
0961     .mas_rpm_id = -1,
0962     .slv_rpm_id = 51
0963 };
0964
0965 static struct qcom_icc_node slv_crypto0_cfg = {
0966     .name = "slv_crypto0_cfg",
0967     .id = MSM8996_SLAVE_CRYPTO_0_CFG,
0968     .buswidth = 4,
0969     .mas_rpm_id = -1,
0970     .slv_rpm_id = 52,
0971     .qos.ap_owned = true,
0972     .qos.qos_mode = NOC_QOS_MODE_INVALID
0973 };
0974
0975 static struct qcom_icc_node slv_mpm = {
0976     .name = "slv_mpm",
0977     .id = MSM8996_SLAVE_MPM,
0978     .buswidth = 4,
0979     .mas_rpm_id = -1,
0980     .slv_rpm_id = 62,
0981     .qos.ap_owned = true,
0982     .qos.qos_mode = NOC_QOS_MODE_INVALID
0983 };
0984
0985 static struct qcom_icc_node slv_pimem_cfg = {
0986     .name = "slv_pimem_cfg",
0987     .id = MSM8996_SLAVE_PIMEM_CFG,
0988     .buswidth = 4,
0989     .mas_rpm_id = -1,
0990     .slv_rpm_id = 167,
0991     .qos.ap_owned = true,
0992     .qos.qos_mode = NOC_QOS_MODE_INVALID
0993 };
0994
0995 static struct qcom_icc_node slv_imem_cfg = {
0996     .name = "slv_imem_cfg",
0997     .id = MSM8996_SLAVE_IMEM_CFG,
0998     .buswidth = 4,
0999     .mas_rpm_id = -1,
1000     .slv_rpm_id = 54,
1001     .qos.ap_owned = true,
1002     .qos.qos_mode = NOC_QOS_MODE_INVALID
1003 };
1004
1005 static struct qcom_icc_node slv_message_ram = {
1006     .name = "slv_message_ram",
1007     .id = MSM8996_SLAVE_MESSAGE_RAM,
1008     .buswidth = 4,
1009     .mas_rpm_id = -1,
1010     .slv_rpm_id = 55
1011 };
1012
1013 static struct qcom_icc_node slv_bimc_cfg = {
1014     .name = "slv_bimc_cfg",
1015     .id = MSM8996_SLAVE_BIMC_CFG,
1016     .buswidth = 4,
1017     .mas_rpm_id = -1,
1018     .slv_rpm_id = 56,
1019     .qos.ap_owned = true,
1020     .qos.qos_mode = NOC_QOS_MODE_INVALID
1021 };
1022
1023 static struct qcom_icc_node slv_pmic_arb = {
1024     .name = "slv_pmic_arb",
1025     .id = MSM8996_SLAVE_PMIC_ARB,
1026     .buswidth = 4,
1027     .mas_rpm_id = -1,
1028     .slv_rpm_id = 59
1029 };
1030
1031 static struct qcom_icc_node slv_prng = {
1032     .name = "slv_prng",
1033     .id = MSM8996_SLAVE_PRNG,
1034     .buswidth = 4,
1035     .mas_rpm_id = -1,
1036     .slv_rpm_id = 127,
1037     .qos.ap_owned = true,
1038     .qos.qos_mode = NOC_QOS_MODE_INVALID
1039 };
1040
1041 static struct qcom_icc_node slv_dcc_cfg = {
1042     .name = "slv_dcc_cfg",
1043     .id = MSM8996_SLAVE_DCC_CFG,
1044     .buswidth = 4,
1045     .mas_rpm_id = -1,
1046     .slv_rpm_id = 155,
1047     .qos.ap_owned = true,
1048     .qos.qos_mode = NOC_QOS_MODE_INVALID
1049 };
1050
1051 static struct qcom_icc_node slv_rbcpr_mx = {
1052     .name = "slv_rbcpr_mx",
1053     .id = MSM8996_SLAVE_RBCPR_MX,
1054     .buswidth = 4,
1055     .mas_rpm_id = -1,
1056     .slv_rpm_id = 170,
1057     .qos.ap_owned = true,
1058     .qos.qos_mode = NOC_QOS_MODE_INVALID
1059 };
1060
1061 static struct qcom_icc_node slv_qdss_cfg = {
1062     .name = "slv_qdss_cfg",
1063     .id = MSM8996_SLAVE_QDSS_CFG,
1064     .buswidth = 4,
1065     .mas_rpm_id = -1,
1066     .slv_rpm_id = 63,
1067     .qos.ap_owned = true,
1068     .qos.qos_mode = NOC_QOS_MODE_INVALID
1069 };
1070
1071 static struct qcom_icc_node slv_rbcpr_cx = {
1072     .name = "slv_rbcpr_cx",
1073     .id = MSM8996_SLAVE_RBCPR_CX,
1074     .buswidth = 4,
1075     .mas_rpm_id = -1,
1076     .slv_rpm_id = 169,
1077     .qos.ap_owned = true,
1078     .qos.qos_mode = NOC_QOS_MODE_INVALID
1079 };
1080
1081 static struct qcom_icc_node slv_cpu_apu_cfg = {
1082     .name = "slv_cpu_apu_cfg",
1083     .id = MSM8996_SLAVE_QDSS_RBCPR_APU_CFG,
1084     .buswidth = 4,
1085     .mas_rpm_id = -1,
1086     .slv_rpm_id = 168,
1087     .qos.ap_owned = true,
1088     .qos.qos_mode = NOC_QOS_MODE_INVALID
1089 };
1090
1091 static const u16 slv_cnoc_mnoc_cfg_links[] = {
1092     MSM8996_MASTER_CNOC_MNOC_CFG
1093 };
1094
1095 static struct qcom_icc_node slv_cnoc_mnoc_cfg = {
1096     .name = "slv_cnoc_mnoc_cfg",
1097     .id = MSM8996_SLAVE_CNOC_MNOC_CFG,
1098     .buswidth = 4,
1099     .mas_rpm_id = -1,
1100     .slv_rpm_id = 66,
1101     .qos.ap_owned = true,
1102     .qos.qos_mode = NOC_QOS_MODE_INVALID,
1103     .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links),
1104     .links = slv_cnoc_mnoc_cfg_links
1105 };
1106
1107 static struct qcom_icc_node slv_snoc_cfg = {
1108     .name = "slv_snoc_cfg",
1109     .id = MSM8996_SLAVE_SNOC_CFG,
1110     .buswidth = 4,
1111     .mas_rpm_id = -1,
1112     .slv_rpm_id = 70,
1113     .qos.ap_owned = true,
1114     .qos.qos_mode = NOC_QOS_MODE_INVALID
1115 };
1116
1117 static struct qcom_icc_node slv_snoc_mpu_cfg = {
1118     .name = "slv_snoc_mpu_cfg",
1119     .id = MSM8996_SLAVE_SNOC_MPU_CFG,
1120     .buswidth = 4,
1121     .mas_rpm_id = -1,
1122     .slv_rpm_id = 67,
1123     .qos.ap_owned = true,
1124     .qos.qos_mode = NOC_QOS_MODE_INVALID
1125 };
1126
1127 static struct qcom_icc_node slv_ebi1_phy_cfg = {
1128     .name = "slv_ebi1_phy_cfg",
1129     .id = MSM8996_SLAVE_EBI1_PHY_CFG,
1130     .buswidth = 4,
1131     .mas_rpm_id = -1,
1132     .slv_rpm_id = 73,
1133     .qos.ap_owned = true,
1134     .qos.qos_mode = NOC_QOS_MODE_INVALID
1135 };
1136
1137 static struct qcom_icc_node slv_a0noc_cfg = {
1138     .name = "slv_a0noc_cfg",
1139     .id = MSM8996_SLAVE_A0NOC_CFG,
1140     .buswidth = 4,
1141     .mas_rpm_id = -1,
1142     .slv_rpm_id = 144,
1143     .qos.ap_owned = true,
1144     .qos.qos_mode = NOC_QOS_MODE_INVALID
1145 };
1146
1147 static struct qcom_icc_node slv_pcie_1_cfg = {
1148     .name = "slv_pcie_1_cfg",
1149     .id = MSM8996_SLAVE_PCIE_1_CFG,
1150     .buswidth = 4,
1151     .mas_rpm_id = -1,
1152     .slv_rpm_id = 89,
1153     .qos.ap_owned = true,
1154     .qos.qos_mode = NOC_QOS_MODE_INVALID
1155 };
1156
1157 static struct qcom_icc_node slv_pcie_2_cfg = {
1158     .name = "slv_pcie_2_cfg",
1159     .id = MSM8996_SLAVE_PCIE_2_CFG,
1160     .buswidth = 4,
1161     .mas_rpm_id = -1,
1162     .slv_rpm_id = 165,
1163     .qos.ap_owned = true,
1164     .qos.qos_mode = NOC_QOS_MODE_INVALID
1165 };
1166
1167 static struct qcom_icc_node slv_pcie_0_cfg = {
1168     .name = "slv_pcie_0_cfg",
1169     .id = MSM8996_SLAVE_PCIE_0_CFG,
1170     .buswidth = 4,
1171     .mas_rpm_id = -1,
1172     .slv_rpm_id = 88,
1173     .qos.ap_owned = true,
1174     .qos.qos_mode = NOC_QOS_MODE_INVALID
1175 };
1176
1177 static struct qcom_icc_node slv_pcie20_ahb2phy = {
1178     .name = "slv_pcie20_ahb2phy",
1179     .id = MSM8996_SLAVE_PCIE20_AHB2PHY,
1180     .buswidth = 4,
1181     .mas_rpm_id = -1,
1182     .slv_rpm_id = 163,
1183     .qos.ap_owned = true,
1184     .qos.qos_mode = NOC_QOS_MODE_INVALID
1185 };
1186
1187 static struct qcom_icc_node slv_a0noc_mpu_cfg = {
1188     .name = "slv_a0noc_mpu_cfg",
1189     .id = MSM8996_SLAVE_A0NOC_MPU_CFG,
1190     .buswidth = 4,
1191     .mas_rpm_id = -1,
1192     .slv_rpm_id = 145,
1193     .qos.ap_owned = true,
1194     .qos.qos_mode = NOC_QOS_MODE_INVALID
1195 };
1196
1197 static struct qcom_icc_node slv_ufs_cfg = {
1198     .name = "slv_ufs_cfg",
1199     .id = MSM8996_SLAVE_UFS_CFG,
1200     .buswidth = 4,
1201     .mas_rpm_id = -1,
1202     .slv_rpm_id = 92,
1203     .qos.ap_owned = true,
1204     .qos.qos_mode = NOC_QOS_MODE_INVALID
1205 };
1206
1207 static struct qcom_icc_node slv_a1noc_cfg = {
1208     .name = "slv_a1noc_cfg",
1209     .id = MSM8996_SLAVE_A1NOC_CFG,
1210     .buswidth = 4,
1211     .mas_rpm_id = -1,
1212     .slv_rpm_id = 147,
1213     .qos.ap_owned = true,
1214     .qos.qos_mode = NOC_QOS_MODE_INVALID
1215 };
1216
1217 static struct qcom_icc_node slv_a1noc_mpu_cfg = {
1218     .name = "slv_a1noc_mpu_cfg",
1219     .id = MSM8996_SLAVE_A1NOC_MPU_CFG,
1220     .buswidth = 4,
1221     .mas_rpm_id = -1,
1222     .slv_rpm_id = 148,
1223     .qos.ap_owned = true,
1224     .qos.qos_mode = NOC_QOS_MODE_INVALID
1225 };
1226
1227 static struct qcom_icc_node slv_a2noc_cfg = {
1228     .name = "slv_a2noc_cfg",
1229     .id = MSM8996_SLAVE_A2NOC_CFG,
1230     .buswidth = 4,
1231     .mas_rpm_id = -1,
1232     .slv_rpm_id = 150,
1233     .qos.ap_owned = true,
1234     .qos.qos_mode = NOC_QOS_MODE_INVALID
1235 };
1236
1237 static struct qcom_icc_node slv_a2noc_mpu_cfg = {
1238     .name = "slv_a2noc_mpu_cfg",
1239     .id = MSM8996_SLAVE_A2NOC_MPU_CFG,
1240     .buswidth = 4,
1241     .mas_rpm_id = -1,
1242     .slv_rpm_id = 151,
1243     .qos.ap_owned = true,
1244     .qos.qos_mode = NOC_QOS_MODE_INVALID
1245 };
1246
1247 static struct qcom_icc_node slv_ssc_cfg = {
1248     .name = "slv_ssc_cfg",
1249     .id = MSM8996_SLAVE_SSC_CFG,
1250     .buswidth = 4,
1251     .mas_rpm_id = -1,
1252     .slv_rpm_id = 177,
1253     .qos.ap_owned = true,
1254     .qos.qos_mode = NOC_QOS_MODE_INVALID
1255 };
1256
1257 static struct qcom_icc_node slv_a0noc_smmu_cfg = {
1258     .name = "slv_a0noc_smmu_cfg",
1259     .id = MSM8996_SLAVE_A0NOC_SMMU_CFG,
1260     .buswidth = 8,
1261     .mas_rpm_id = -1,
1262     .slv_rpm_id = 146,
1263     .qos.ap_owned = true,
1264     .qos.qos_mode = NOC_QOS_MODE_INVALID
1265 };
1266
1267 static struct qcom_icc_node slv_a1noc_smmu_cfg = {
1268     .name = "slv_a1noc_smmu_cfg",
1269     .id = MSM8996_SLAVE_A1NOC_SMMU_CFG,
1270     .buswidth = 8,
1271     .mas_rpm_id = -1,
1272     .slv_rpm_id = 149,
1273     .qos.ap_owned = true,
1274     .qos.qos_mode = NOC_QOS_MODE_INVALID
1275 };
1276
1277 static struct qcom_icc_node slv_a2noc_smmu_cfg = {
1278     .name = "slv_a2noc_smmu_cfg",
1279     .id = MSM8996_SLAVE_A2NOC_SMMU_CFG,
1280     .buswidth = 8,
1281     .mas_rpm_id = -1,
1282     .slv_rpm_id = 152,
1283     .qos.ap_owned = true,
1284     .qos.qos_mode = NOC_QOS_MODE_INVALID
1285 };
1286
1287 static struct qcom_icc_node slv_lpass_smmu_cfg = {
1288     .name = "slv_lpass_smmu_cfg",
1289     .id = MSM8996_SLAVE_LPASS_SMMU_CFG,
1290     .buswidth = 8,
1291     .mas_rpm_id = -1,
1292     .slv_rpm_id = 161,
1293     .qos.ap_owned = true,
1294     .qos.qos_mode = NOC_QOS_MODE_INVALID
1295 };
1296
1297 static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = {
1298     MSM8996_MASTER_CNOC_MNOC_MMSS_CFG
1299 };
1300
1301 static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = {
1302     .name = "slv_cnoc_mnoc_mmss_cfg",
1303     .id = MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG,
1304     .buswidth = 8,
1305     .mas_rpm_id = -1,
1306     .slv_rpm_id = 58,
1307     .qos.ap_owned = true,
1308     .qos.qos_mode = NOC_QOS_MODE_INVALID,
1309     .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links),
1310     .links = slv_cnoc_mnoc_mmss_cfg_links
1311 };
1312
1313 static struct qcom_icc_node slv_mmagic_cfg = {
1314     .name = "slv_mmagic_cfg",
1315     .id = MSM8996_SLAVE_MMAGIC_CFG,
1316     .buswidth = 8,
1317     .mas_rpm_id = -1,
1318     .slv_rpm_id = 162,
1319     .qos.ap_owned = true,
1320     .qos.qos_mode = NOC_QOS_MODE_INVALID
1321 };
1322
1323 static struct qcom_icc_node slv_cpr_cfg = {
1324     .name = "slv_cpr_cfg",
1325     .id = MSM8996_SLAVE_CPR_CFG,
1326     .buswidth = 8,
1327     .mas_rpm_id = -1,
1328     .slv_rpm_id = 6,
1329     .qos.ap_owned = true,
1330     .qos.qos_mode = NOC_QOS_MODE_INVALID
1331 };
1332
1333 static struct qcom_icc_node slv_misc_cfg = {
1334     .name = "slv_misc_cfg",
1335     .id = MSM8996_SLAVE_MISC_CFG,
1336     .buswidth = 8,
1337     .mas_rpm_id = -1,
1338     .slv_rpm_id = 8,
1339     .qos.ap_owned = true,
1340     .qos.qos_mode = NOC_QOS_MODE_INVALID
1341 };
1342
1343 static struct qcom_icc_node slv_venus_throttle_cfg = {
1344     .name = "slv_venus_throttle_cfg",
1345     .id = MSM8996_SLAVE_VENUS_THROTTLE_CFG,
1346     .buswidth = 8,
1347     .mas_rpm_id = -1,
1348     .slv_rpm_id = 178,
1349     .qos.ap_owned = true,
1350     .qos.qos_mode = NOC_QOS_MODE_INVALID
1351 };
1352
1353 static struct qcom_icc_node slv_venus_cfg = {
1354     .name = "slv_venus_cfg",
1355     .id = MSM8996_SLAVE_VENUS_CFG,
1356     .buswidth = 8,
1357     .mas_rpm_id = -1,
1358     .slv_rpm_id = 10,
1359     .qos.ap_owned = true,
1360     .qos.qos_mode = NOC_QOS_MODE_INVALID
1361 };
1362
1363 static struct qcom_icc_node slv_vmem_cfg = {
1364     .name = "slv_vmem_cfg",
1365     .id = MSM8996_SLAVE_VMEM_CFG,
1366     .buswidth = 8,
1367     .mas_rpm_id = -1,
1368     .slv_rpm_id = 180,
1369     .qos.ap_owned = true,
1370     .qos.qos_mode = NOC_QOS_MODE_INVALID
1371 };
1372
1373 static struct qcom_icc_node slv_dsa_cfg = {
1374     .name = "slv_dsa_cfg",
1375     .id = MSM8996_SLAVE_DSA_CFG,
1376     .buswidth = 8,
1377     .mas_rpm_id = -1,
1378     .slv_rpm_id = 157,
1379     .qos.ap_owned = true,
1380     .qos.qos_mode = NOC_QOS_MODE_INVALID
1381 };
1382
1383 static struct qcom_icc_node slv_mnoc_clocks_cfg = {
1384     .name = "slv_mnoc_clocks_cfg",
1385     .id = MSM8996_SLAVE_MMSS_CLK_CFG,
1386     .buswidth = 8,
1387     .mas_rpm_id = -1,
1388     .slv_rpm_id = 12,
1389     .qos.ap_owned = true,
1390     .qos.qos_mode = NOC_QOS_MODE_INVALID
1391 };
1392
1393 static struct qcom_icc_node slv_dsa_mpu_cfg = {
1394     .name = "slv_dsa_mpu_cfg",
1395     .id = MSM8996_SLAVE_DSA_MPU_CFG,
1396     .buswidth = 8,
1397     .mas_rpm_id = -1,
1398     .slv_rpm_id = 158,
1399     .qos.ap_owned = true,
1400     .qos.qos_mode = NOC_QOS_MODE_INVALID
1401 };
1402
1403 static struct qcom_icc_node slv_mnoc_mpu_cfg = {
1404     .name = "slv_mnoc_mpu_cfg",
1405     .id = MSM8996_SLAVE_MNOC_MPU_CFG,
1406     .buswidth = 8,
1407     .mas_rpm_id = -1,
1408     .slv_rpm_id = 14,
1409     .qos.ap_owned = true,
1410     .qos.qos_mode = NOC_QOS_MODE_INVALID
1411 };
1412
1413 static struct qcom_icc_node slv_display_cfg = {
1414     .name = "slv_display_cfg",
1415     .id = MSM8996_SLAVE_DISPLAY_CFG,
1416     .buswidth = 8,
1417     .mas_rpm_id = -1,
1418     .slv_rpm_id = 4,
1419     .qos.ap_owned = true,
1420     .qos.qos_mode = NOC_QOS_MODE_INVALID
1421 };
1422
1423 static struct qcom_icc_node slv_display_throttle_cfg = {
1424     .name = "slv_display_throttle_cfg",
1425     .id = MSM8996_SLAVE_DISPLAY_THROTTLE_CFG,
1426     .buswidth = 8,
1427     .mas_rpm_id = -1,
1428     .slv_rpm_id = 156,
1429     .qos.ap_owned = true,
1430     .qos.qos_mode = NOC_QOS_MODE_INVALID
1431 };
1432
1433 static struct qcom_icc_node slv_camera_cfg = {
1434     .name = "slv_camera_cfg",
1435     .id = MSM8996_SLAVE_CAMERA_CFG,
1436     .buswidth = 8,
1437     .mas_rpm_id = -1,
1438     .slv_rpm_id = 3,
1439     .qos.ap_owned = true,
1440     .qos.qos_mode = NOC_QOS_MODE_INVALID
1441 };
1442
1443 static struct qcom_icc_node slv_camera_throttle_cfg = {
1444     .name = "slv_camera_throttle_cfg",
1445     .id = MSM8996_SLAVE_CAMERA_THROTTLE_CFG,
1446     .buswidth = 8,
1447     .mas_rpm_id = -1,
1448     .slv_rpm_id = 154,
1449     .qos.ap_owned = true,
1450     .qos.qos_mode = NOC_QOS_MODE_INVALID
1451 };
1452
1453 static struct qcom_icc_node slv_oxili_cfg = {
1454     .name = "slv_oxili_cfg",
1455     .id = MSM8996_SLAVE_GRAPHICS_3D_CFG,
1456     .buswidth = 8,
1457     .mas_rpm_id = -1,
1458     .slv_rpm_id = 11,
1459     .qos.ap_owned = true,
1460     .qos.qos_mode = NOC_QOS_MODE_INVALID
1461 };
1462
1463 static struct qcom_icc_node slv_smmu_mdp_cfg = {
1464     .name = "slv_smmu_mdp_cfg",
1465     .id = MSM8996_SLAVE_SMMU_MDP_CFG,
1466     .buswidth = 8,
1467     .mas_rpm_id = -1,
1468     .slv_rpm_id = 173,
1469     .qos.ap_owned = true,
1470     .qos.qos_mode = NOC_QOS_MODE_INVALID
1471 };
1472
1473 static struct qcom_icc_node slv_smmu_rot_cfg = {
1474     .name = "slv_smmu_rot_cfg",
1475     .id = MSM8996_SLAVE_SMMU_ROTATOR_CFG,
1476     .buswidth = 8,
1477     .mas_rpm_id = -1,
1478     .slv_rpm_id = 174,
1479     .qos.ap_owned = true,
1480     .qos.qos_mode = NOC_QOS_MODE_INVALID
1481 };
1482
1483 static struct qcom_icc_node slv_smmu_venus_cfg = {
1484     .name = "slv_smmu_venus_cfg",
1485     .id = MSM8996_SLAVE_SMMU_VENUS_CFG,
1486     .buswidth = 8,
1487     .mas_rpm_id = -1,
1488     .slv_rpm_id = 175,
1489     .qos.ap_owned = true,
1490     .qos.qos_mode = NOC_QOS_MODE_INVALID
1491 };
1492
1493 static struct qcom_icc_node slv_smmu_cpp_cfg = {
1494     .name = "slv_smmu_cpp_cfg",
1495     .id = MSM8996_SLAVE_SMMU_CPP_CFG,
1496     .buswidth = 8,
1497     .mas_rpm_id = -1,
1498     .slv_rpm_id = 171,
1499     .qos.ap_owned = true,
1500     .qos.qos_mode = NOC_QOS_MODE_INVALID
1501 };
1502
1503 static struct qcom_icc_node slv_smmu_jpeg_cfg = {
1504     .name = "slv_smmu_jpeg_cfg",
1505     .id = MSM8996_SLAVE_SMMU_JPEG_CFG,
1506     .buswidth = 8,
1507     .mas_rpm_id = -1,
1508     .slv_rpm_id = 172,
1509     .qos.ap_owned = true,
1510     .qos.qos_mode = NOC_QOS_MODE_INVALID
1511 };
1512
1513 static struct qcom_icc_node slv_smmu_vfe_cfg = {
1514     .name = "slv_smmu_vfe_cfg",
1515     .id = MSM8996_SLAVE_SMMU_VFE_CFG,
1516     .buswidth = 8,
1517     .mas_rpm_id = -1,
1518     .slv_rpm_id = 176,
1519     .qos.ap_owned = true,
1520     .qos.qos_mode = NOC_QOS_MODE_INVALID
1521 };
1522
1523 static const u16 slv_mnoc_bimc_links[] = {
1524     MSM8996_MASTER_MNOC_BIMC
1525 };
1526
1527 static struct qcom_icc_node slv_mnoc_bimc = {
1528     .name = "slv_mnoc_bimc",
1529     .id = MSM8996_SLAVE_MNOC_BIMC,
1530     .buswidth = 32,
1531     .mas_rpm_id = -1,
1532     .slv_rpm_id = 16,
1533     .qos.ap_owned = true,
1534     .qos.qos_mode = NOC_QOS_MODE_INVALID,
1535     .num_links = ARRAY_SIZE(slv_mnoc_bimc_links),
1536     .links = slv_mnoc_bimc_links
1537 };
1538
1539 static struct qcom_icc_node slv_vmem = {
1540     .name = "slv_vmem",
1541     .id = MSM8996_SLAVE_VMEM,
1542     .buswidth = 32,
1543     .mas_rpm_id = -1,
1544     .slv_rpm_id = 179,
1545     .qos.ap_owned = true,
1546     .qos.qos_mode = NOC_QOS_MODE_INVALID
1547 };
1548
1549 static struct qcom_icc_node slv_srvc_mnoc = {
1550     .name = "slv_srvc_mnoc",
1551     .id = MSM8996_SLAVE_SERVICE_MNOC,
1552     .buswidth = 8,
1553     .mas_rpm_id = -1,
1554     .slv_rpm_id = 17,
1555     .qos.ap_owned = true,
1556     .qos.qos_mode = NOC_QOS_MODE_INVALID
1557 };
1558
1559 static const u16 slv_pnoc_a1noc_links[] = {
1560     MSM8996_MASTER_PNOC_A1NOC
1561 };
1562
1563 static struct qcom_icc_node slv_pnoc_a1noc = {
1564     .name = "slv_pnoc_a1noc",
1565     .id = MSM8996_SLAVE_PNOC_A1NOC,
1566     .buswidth = 8,
1567     .mas_rpm_id = -1,
1568     .slv_rpm_id = 139,
1569     .num_links = ARRAY_SIZE(slv_pnoc_a1noc_links),
1570     .links = slv_pnoc_a1noc_links
1571 };
1572
1573 static struct qcom_icc_node slv_usb_hs = {
1574     .name = "slv_usb_hs",
1575     .id = MSM8996_SLAVE_USB_HS,
1576     .buswidth = 4,
1577     .mas_rpm_id = -1,
1578     .slv_rpm_id = 40
1579 };
1580
1581 static struct qcom_icc_node slv_sdcc_2 = {
1582     .name = "slv_sdcc_2",
1583     .id = MSM8996_SLAVE_SDCC_2,
1584     .buswidth = 4,
1585     .mas_rpm_id = -1,
1586     .slv_rpm_id = 33
1587 };
1588
1589 static struct qcom_icc_node slv_sdcc_4 = {
1590     .name = "slv_sdcc_4",
1591     .id = MSM8996_SLAVE_SDCC_4,
1592     .buswidth = 4,
1593     .mas_rpm_id = -1,
1594     .slv_rpm_id = 34
1595 };
1596
1597 static struct qcom_icc_node slv_tsif = {
1598     .name = "slv_tsif",
1599     .id = MSM8996_SLAVE_TSIF,
1600     .buswidth = 4,
1601     .mas_rpm_id = -1,
1602     .slv_rpm_id = 35
1603 };
1604
1605 static struct qcom_icc_node slv_blsp_2 = {
1606     .name = "slv_blsp_2",
1607     .id = MSM8996_SLAVE_BLSP_2,
1608     .buswidth = 4,
1609     .mas_rpm_id = -1,
1610     .slv_rpm_id = 37
1611 };
1612
1613 static struct qcom_icc_node slv_sdcc_1 = {
1614     .name = "slv_sdcc_1",
1615     .id = MSM8996_SLAVE_SDCC_1,
1616     .buswidth = 4,
1617     .mas_rpm_id = -1,
1618     .slv_rpm_id = 31
1619 };
1620
1621 static struct qcom_icc_node slv_blsp_1 = {
1622     .name = "slv_blsp_1",
1623     .id = MSM8996_SLAVE_BLSP_1,
1624     .buswidth = 4,
1625     .mas_rpm_id = -1,
1626     .slv_rpm_id = 39
1627 };
1628
1629 static struct qcom_icc_node slv_pdm = {
1630     .name = "slv_pdm",
1631     .id = MSM8996_SLAVE_PDM,
1632     .buswidth = 4,
1633     .mas_rpm_id = -1,
1634     .slv_rpm_id = 41
1635 };
1636
1637 static struct qcom_icc_node slv_ahb2phy = {
1638     .name = "slv_ahb2phy",
1639     .id = MSM8996_SLAVE_AHB2PHY,
1640     .buswidth = 4,
1641     .mas_rpm_id = -1,
1642     .slv_rpm_id = 153,
1643     .qos.ap_owned = true,
1644     .qos.qos_mode = NOC_QOS_MODE_INVALID
1645 };
1646
1647 static struct qcom_icc_node slv_hmss = {
1648     .name = "slv_hmss",
1649     .id = MSM8996_SLAVE_APPSS,
1650     .buswidth = 16,
1651     .mas_rpm_id = -1,
1652     .slv_rpm_id = 20,
1653     .qos.ap_owned = true,
1654     .qos.qos_mode = NOC_QOS_MODE_INVALID
1655 };
1656
1657 static struct qcom_icc_node slv_lpass = {
1658     .name = "slv_lpass",
1659     .id = MSM8996_SLAVE_LPASS,
1660     .buswidth = 16,
1661     .mas_rpm_id = -1,
1662     .slv_rpm_id = 21,
1663     .qos.ap_owned = true,
1664     .qos.qos_mode = NOC_QOS_MODE_INVALID
1665 };
1666
1667 static struct qcom_icc_node slv_usb3 = {
1668     .name = "slv_usb3",
1669     .id = MSM8996_SLAVE_USB3,
1670     .buswidth = 16,
1671     .mas_rpm_id = -1,
1672     .slv_rpm_id = 22,
1673     .qos.ap_owned = true,
1674     .qos.qos_mode = NOC_QOS_MODE_INVALID
1675 };
1676
1677 static const u16 slv_snoc_bimc_links[] = {
1678     MSM8996_MASTER_SNOC_BIMC
1679 };
1680
1681 static struct qcom_icc_node slv_snoc_bimc = {
1682     .name = "slv_snoc_bimc",
1683     .id = MSM8996_SLAVE_SNOC_BIMC,
1684     .buswidth = 32,
1685     .mas_rpm_id = -1,
1686     .slv_rpm_id = 24,
1687     .num_links = ARRAY_SIZE(slv_snoc_bimc_links),
1688     .links = slv_snoc_bimc_links
1689 };
1690
1691 static const u16 slv_snoc_cnoc_links[] = {
1692     MSM8996_MASTER_SNOC_CNOC
1693 };
1694
1695 static struct qcom_icc_node slv_snoc_cnoc = {
1696     .name = "slv_snoc_cnoc",
1697     .id = MSM8996_SLAVE_SNOC_CNOC,
1698     .buswidth = 16,
1699     .mas_rpm_id = -1,
1700     .slv_rpm_id = 25,
1701     .num_links = ARRAY_SIZE(slv_snoc_cnoc_links),
1702     .links = slv_snoc_cnoc_links
1703 };
1704
1705 static struct qcom_icc_node slv_imem = {
1706     .name = "slv_imem",
1707     .id = MSM8996_SLAVE_OCIMEM,
1708     .buswidth = 16,
1709     .mas_rpm_id = -1,
1710     .slv_rpm_id = 26
1711 };
1712
1713 static struct qcom_icc_node slv_pimem = {
1714     .name = "slv_pimem",
1715     .id = MSM8996_SLAVE_PIMEM,
1716     .buswidth = 16,
1717     .mas_rpm_id = -1,
1718     .slv_rpm_id = 166
1719 };
1720
1721 static const u16 slv_snoc_vmem_links[] = {
1722     MSM8996_MASTER_SNOC_VMEM
1723 };
1724
1725 static struct qcom_icc_node slv_snoc_vmem = {
1726     .name = "slv_snoc_vmem",
1727     .id = MSM8996_SLAVE_SNOC_VMEM,
1728     .buswidth = 16,
1729     .mas_rpm_id = -1,
1730     .slv_rpm_id = 140,
1731     .qos.ap_owned = true,
1732     .qos.qos_mode = NOC_QOS_MODE_INVALID,
1733     .num_links = ARRAY_SIZE(slv_snoc_vmem_links),
1734     .links = slv_snoc_vmem_links
1735 };
1736
1737 static const u16 slv_snoc_pnoc_links[] = {
1738     MSM8996_MASTER_SNOC_PNOC
1739 };
1740
1741 static struct qcom_icc_node slv_snoc_pnoc = {
1742     .name = "slv_snoc_pnoc",
1743     .id = MSM8996_SLAVE_SNOC_PNOC,
1744     .buswidth = 16,
1745     .mas_rpm_id = -1,
1746     .slv_rpm_id = 28,
1747     .num_links = ARRAY_SIZE(slv_snoc_pnoc_links),
1748     .links = slv_snoc_pnoc_links
1749 };
1750
1751 static struct qcom_icc_node slv_qdss_stm = {
1752     .name = "slv_qdss_stm",
1753     .id = MSM8996_SLAVE_QDSS_STM,
1754     .buswidth = 16,
1755     .mas_rpm_id = -1,
1756     .slv_rpm_id = 30
1757 };
1758
1759 static struct qcom_icc_node slv_pcie_0 = {
1760     .name = "slv_pcie_0",
1761     .id = MSM8996_SLAVE_PCIE_0,
1762     .buswidth = 16,
1763     .mas_rpm_id = -1,
1764     .slv_rpm_id = 84,
1765     .qos.ap_owned = true,
1766     .qos.qos_mode = NOC_QOS_MODE_INVALID
1767 };
1768
1769 static struct qcom_icc_node slv_pcie_1 = {
1770     .name = "slv_pcie_1",
1771     .id = MSM8996_SLAVE_PCIE_1,
1772     .buswidth = 16,
1773     .mas_rpm_id = -1,
1774     .slv_rpm_id = 85,
1775     .qos.ap_owned = true,
1776     .qos.qos_mode = NOC_QOS_MODE_INVALID
1777 };
1778
1779 static struct qcom_icc_node slv_pcie_2 = {
1780     .name = "slv_pcie_2",
1781     .id = MSM8996_SLAVE_PCIE_2,
1782     .buswidth = 16,
1783     .mas_rpm_id = -1,
1784     .slv_rpm_id = 164,
1785     .qos.ap_owned = true,
1786     .qos.qos_mode = NOC_QOS_MODE_INVALID
1787 };
1788
1789 static struct qcom_icc_node slv_srvc_snoc = {
1790     .name = "slv_srvc_snoc",
1791     .id = MSM8996_SLAVE_SERVICE_SNOC,
1792     .buswidth = 16,
1793     .mas_rpm_id = -1,
1794     .slv_rpm_id = 29,
1795     .qos.ap_owned = true,
1796     .qos.qos_mode = NOC_QOS_MODE_INVALID
1797 };
1798
1799 static struct qcom_icc_node * const a0noc_nodes[] = {
1800     [MASTER_PCIE_0] = &mas_pcie_0,
1801     [MASTER_PCIE_1] = &mas_pcie_1,
1802     [MASTER_PCIE_2] = &mas_pcie_2
1803 };
1804
1805 static const struct regmap_config msm8996_a0noc_regmap_config = {
1806     .reg_bits   = 32,
1807     .reg_stride = 4,
1808     .val_bits   = 32,
1809     .max_register   = 0x9000,
1810     .fast_io    = true
1811 };
1812
1813 static const struct qcom_icc_desc msm8996_a0noc = {
1814     .type = QCOM_ICC_NOC,
1815     .nodes = a0noc_nodes,
1816     .num_nodes = ARRAY_SIZE(a0noc_nodes),
1817     .clocks = bus_a0noc_clocks,
1818     .num_clocks = ARRAY_SIZE(bus_a0noc_clocks),
1819     .has_bus_pd = true,
1820     .regmap_cfg = &msm8996_a0noc_regmap_config
1821 };
1822
1823 static struct qcom_icc_node * const a1noc_nodes[] = {
1824     [MASTER_CNOC_A1NOC] = &mas_cnoc_a1noc,
1825     [MASTER_CRYPTO_CORE0] = &mas_crypto_c0,
1826     [MASTER_PNOC_A1NOC] = &mas_pnoc_a1noc
1827 };
1828
1829 static const struct regmap_config msm8996_a1noc_regmap_config = {
1830     .reg_bits   = 32,
1831     .reg_stride = 4,
1832     .val_bits   = 32,
1833     .max_register   = 0x7000,
1834     .fast_io    = true
1835 };
1836
1837 static const struct qcom_icc_desc msm8996_a1noc = {
1838     .type = QCOM_ICC_NOC,
1839     .nodes = a1noc_nodes,
1840     .num_nodes = ARRAY_SIZE(a1noc_nodes),
1841     .regmap_cfg = &msm8996_a1noc_regmap_config
1842 };
1843
1844 static struct qcom_icc_node * const a2noc_nodes[] = {
1845     [MASTER_USB3] = &mas_usb3,
1846     [MASTER_IPA] = &mas_ipa,
1847     [MASTER_UFS] = &mas_ufs
1848 };
1849
1850 static const struct regmap_config msm8996_a2noc_regmap_config = {
1851     .reg_bits   = 32,
1852     .reg_stride = 4,
1853     .val_bits   = 32,
1854     .max_register   = 0xa000,
1855     .fast_io    = true
1856 };
1857
1858 static const struct qcom_icc_desc msm8996_a2noc = {
1859     .type = QCOM_ICC_NOC,
1860     .nodes = a2noc_nodes,
1861     .num_nodes = ARRAY_SIZE(a2noc_nodes),
1862     .regmap_cfg = &msm8996_a2noc_regmap_config
1863 };
1864
1865 static struct qcom_icc_node * const bimc_nodes[] = {
1866     [MASTER_AMPSS_M0] = &mas_apps_proc,
1867     [MASTER_GRAPHICS_3D] = &mas_oxili,
1868     [MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
1869     [MASTER_SNOC_BIMC] = &mas_snoc_bimc,
1870     [SLAVE_EBI_CH0] = &slv_ebi,
1871     [SLAVE_HMSS_L3] = &slv_hmss_l3,
1872     [SLAVE_BIMC_SNOC_0] = &slv_bimc_snoc_0,
1873     [SLAVE_BIMC_SNOC_1] = &slv_bimc_snoc_1
1874 };
1875
1876 static const struct regmap_config msm8996_bimc_regmap_config = {
1877     .reg_bits   = 32,
1878     .reg_stride = 4,
1879     .val_bits   = 32,
1880     .max_register   = 0x62000,
1881     .fast_io    = true
1882 };
1883
1884 static const struct qcom_icc_desc msm8996_bimc = {
1885     .type = QCOM_ICC_BIMC,
1886     .nodes = bimc_nodes,
1887     .num_nodes = ARRAY_SIZE(bimc_nodes),
1888     .regmap_cfg = &msm8996_bimc_regmap_config
1889 };
1890
1891 static struct qcom_icc_node * const cnoc_nodes[] = {
1892     [MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
1893     [MASTER_QDSS_DAP] = &mas_qdss_dap,
1894     [SLAVE_CNOC_A1NOC] = &slv_cnoc_a1noc,
1895     [SLAVE_CLK_CTL] = &slv_clk_ctl,
1896     [SLAVE_TCSR] = &slv_tcsr,
1897     [SLAVE_TLMM] = &slv_tlmm,
1898     [SLAVE_CRYPTO_0_CFG] = &slv_crypto0_cfg,
1899     [SLAVE_MPM] = &slv_mpm,
1900     [SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
1901     [SLAVE_IMEM_CFG] = &slv_imem_cfg,
1902     [SLAVE_MESSAGE_RAM] = &slv_message_ram,
1903     [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1904     [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1905     [SLAVE_PRNG] = &slv_prng,
1906     [SLAVE_DCC_CFG] = &slv_dcc_cfg,
1907     [SLAVE_RBCPR_MX] = &slv_rbcpr_mx,
1908     [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1909     [SLAVE_RBCPR_CX] = &slv_rbcpr_cx,
1910     [SLAVE_QDSS_RBCPR_APU] = &slv_cpu_apu_cfg,
1911     [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
1912     [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1913     [SLAVE_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg,
1914     [SLAVE_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg,
1915     [SLAVE_A0NOC_CFG] = &slv_a0noc_cfg,
1916     [SLAVE_PCIE_1_CFG] = &slv_pcie_1_cfg,
1917     [SLAVE_PCIE_2_CFG] = &slv_pcie_2_cfg,
1918     [SLAVE_PCIE_0_CFG] = &slv_pcie_0_cfg,
1919     [SLAVE_PCIE20_AHB2PHY] = &slv_pcie20_ahb2phy,
1920     [SLAVE_A0NOC_MPU_CFG] = &slv_a0noc_mpu_cfg,
1921     [SLAVE_UFS_CFG] = &slv_ufs_cfg,
1922     [SLAVE_A1NOC_CFG] = &slv_a1noc_cfg,
1923     [SLAVE_A1NOC_MPU_CFG] = &slv_a1noc_mpu_cfg,
1924     [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
1925     [SLAVE_A2NOC_MPU_CFG] = &slv_a2noc_mpu_cfg,
1926     [SLAVE_SSC_CFG] = &slv_ssc_cfg,
1927     [SLAVE_A0NOC_SMMU_CFG] = &slv_a0noc_smmu_cfg,
1928     [SLAVE_A1NOC_SMMU_CFG] = &slv_a1noc_smmu_cfg,
1929     [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
1930     [SLAVE_LPASS_SMMU_CFG] = &slv_lpass_smmu_cfg,
1931     [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg
1932 };
1933
1934 static const struct regmap_config msm8996_cnoc_regmap_config = {
1935     .reg_bits   = 32,
1936     .reg_stride = 4,
1937     .val_bits   = 32,
1938     .max_register   = 0x1000,
1939     .fast_io    = true
1940 };
1941
1942 static const struct qcom_icc_desc msm8996_cnoc = {
1943     .type = QCOM_ICC_NOC,
1944     .nodes = cnoc_nodes,
1945     .num_nodes = ARRAY_SIZE(cnoc_nodes),
1946     .regmap_cfg = &msm8996_cnoc_regmap_config
1947 };
1948
1949 static struct qcom_icc_node * const mnoc_nodes[] = {
1950     [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
1951     [MASTER_CPP] = &mas_cpp,
1952     [MASTER_JPEG] = &mas_jpeg,
1953     [MASTER_MDP_PORT0] = &mas_mdp_p0,
1954     [MASTER_MDP_PORT1] = &mas_mdp_p1,
1955     [MASTER_ROTATOR] = &mas_rotator,
1956     [MASTER_VIDEO_P0] = &mas_venus,
1957     [MASTER_VFE] = &mas_vfe,
1958     [MASTER_SNOC_VMEM] = &mas_snoc_vmem,
1959     [MASTER_VIDEO_P0_OCMEM] = &mas_venus_vmem,
1960     [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
1961     [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
1962     [SLAVE_VMEM] = &slv_vmem,
1963     [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc,
1964     [SLAVE_MMAGIC_CFG] = &slv_mmagic_cfg,
1965     [SLAVE_CPR_CFG] = &slv_cpr_cfg,
1966     [SLAVE_MISC_CFG] = &slv_misc_cfg,
1967     [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
1968     [SLAVE_VENUS_CFG] = &slv_venus_cfg,
1969     [SLAVE_VMEM_CFG] = &slv_vmem_cfg,
1970     [SLAVE_DSA_CFG] = &slv_dsa_cfg,
1971     [SLAVE_MMSS_CLK_CFG] = &slv_mnoc_clocks_cfg,
1972     [SLAVE_DSA_MPU_CFG] = &slv_dsa_mpu_cfg,
1973     [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
1974     [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1975     [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
1976     [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1977     [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
1978     [SLAVE_GRAPHICS_3D_CFG] = &slv_oxili_cfg,
1979     [SLAVE_SMMU_MDP_CFG] = &slv_smmu_mdp_cfg,
1980     [SLAVE_SMMU_ROT_CFG] = &slv_smmu_rot_cfg,
1981     [SLAVE_SMMU_VENUS_CFG] = &slv_smmu_venus_cfg,
1982     [SLAVE_SMMU_CPP_CFG] = &slv_smmu_cpp_cfg,
1983     [SLAVE_SMMU_JPEG_CFG] = &slv_smmu_jpeg_cfg,
1984     [SLAVE_SMMU_VFE_CFG] = &slv_smmu_vfe_cfg
1985 };
1986
1987 static const struct regmap_config msm8996_mnoc_regmap_config = {
1988     .reg_bits   = 32,
1989     .reg_stride = 4,
1990     .val_bits   = 32,
1991     .max_register   = 0x20000,
1992     .fast_io    = true
1993 };
1994
1995 static const struct qcom_icc_desc msm8996_mnoc = {
1996     .type = QCOM_ICC_NOC,
1997     .nodes = mnoc_nodes,
1998     .num_nodes = ARRAY_SIZE(mnoc_nodes),
1999     .clocks = bus_mm_clocks,
2000     .num_clocks = ARRAY_SIZE(bus_mm_clocks),
2001     .regmap_cfg = &msm8996_mnoc_regmap_config
2002 };
2003
2004 static struct qcom_icc_node * const pnoc_nodes[] = {
2005     [MASTER_SNOC_PNOC] = &mas_snoc_pnoc,
2006     [MASTER_SDCC_1] = &mas_sdcc_1,
2007     [MASTER_SDCC_2] = &mas_sdcc_2,
2008     [MASTER_SDCC_4] = &mas_sdcc_4,
2009     [MASTER_USB_HS] = &mas_usb_hs,
2010     [MASTER_BLSP_1] = &mas_blsp_1,
2011     [MASTER_BLSP_2] = &mas_blsp_2,
2012     [MASTER_TSIF] = &mas_tsif,
2013     [SLAVE_PNOC_A1NOC] = &slv_pnoc_a1noc,
2014     [SLAVE_USB_HS] = &slv_usb_hs,
2015     [SLAVE_SDCC_2] = &slv_sdcc_2,
2016     [SLAVE_SDCC_4] = &slv_sdcc_4,
2017     [SLAVE_TSIF] = &slv_tsif,
2018     [SLAVE_BLSP_2] = &slv_blsp_2,
2019     [SLAVE_SDCC_1] = &slv_sdcc_1,
2020     [SLAVE_BLSP_1] = &slv_blsp_1,
2021     [SLAVE_PDM] = &slv_pdm,
2022     [SLAVE_AHB2PHY] = &slv_ahb2phy
2023 };
2024
2025 static const struct regmap_config msm8996_pnoc_regmap_config = {
2026     .reg_bits   = 32,
2027     .reg_stride = 4,
2028     .val_bits   = 32,
2029     .max_register   = 0x3000,
2030     .fast_io    = true
2031 };
2032
2033 static const struct qcom_icc_desc msm8996_pnoc = {
2034     .type = QCOM_ICC_NOC,
2035     .nodes = pnoc_nodes,
2036     .num_nodes = ARRAY_SIZE(pnoc_nodes),
2037     .regmap_cfg = &msm8996_pnoc_regmap_config
2038 };
2039
2040 static struct qcom_icc_node * const snoc_nodes[] = {
2041     [MASTER_HMSS] = &mas_hmss,
2042     [MASTER_QDSS_BAM] = &mas_qdss_bam,
2043     [MASTER_SNOC_CFG] = &mas_snoc_cfg,
2044     [MASTER_BIMC_SNOC_0] = &mas_bimc_snoc_0,
2045     [MASTER_BIMC_SNOC_1] = &mas_bimc_snoc_1,
2046     [MASTER_A0NOC_SNOC] = &mas_a0noc_snoc,
2047     [MASTER_A1NOC_SNOC] = &mas_a1noc_snoc,
2048     [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
2049     [MASTER_QDSS_ETR] = &mas_qdss_etr,
2050     [SLAVE_A0NOC_SNOC] = &slv_a0noc_snoc,
2051     [SLAVE_A1NOC_SNOC] = &slv_a1noc_snoc,
2052     [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
2053     [SLAVE_HMSS] = &slv_hmss,
2054     [SLAVE_LPASS] = &slv_lpass,
2055     [SLAVE_USB3] = &slv_usb3,
2056     [SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
2057     [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
2058     [SLAVE_IMEM] = &slv_imem,
2059     [SLAVE_PIMEM] = &slv_pimem,
2060     [SLAVE_SNOC_VMEM] = &slv_snoc_vmem,
2061     [SLAVE_SNOC_PNOC] = &slv_snoc_pnoc,
2062     [SLAVE_QDSS_STM] = &slv_qdss_stm,
2063     [SLAVE_PCIE_0] = &slv_pcie_0,
2064     [SLAVE_PCIE_1] = &slv_pcie_1,
2065     [SLAVE_PCIE_2] = &slv_pcie_2,
2066     [SLAVE_SERVICE_SNOC] = &slv_srvc_snoc
2067 };
2068
2069 static const struct regmap_config msm8996_snoc_regmap_config = {
2070     .reg_bits   = 32,
2071     .reg_stride = 4,
2072     .val_bits   = 32,
2073     .max_register   = 0x20000,
2074     .fast_io    = true
2075 };
2076
2077 static const struct qcom_icc_desc msm8996_snoc = {
2078     .type = QCOM_ICC_NOC,
2079     .nodes = snoc_nodes,
2080     .num_nodes = ARRAY_SIZE(snoc_nodes),
2081     .regmap_cfg = &msm8996_snoc_regmap_config
2082 };
2083
2084 static const struct of_device_id qnoc_of_match[] = {
2085     { .compatible = "qcom,msm8996-a0noc", .data = &msm8996_a0noc},
2086     { .compatible = "qcom,msm8996-a1noc", .data = &msm8996_a1noc},
2087     { .compatible = "qcom,msm8996-a2noc", .data = &msm8996_a2noc},
2088     { .compatible = "qcom,msm8996-bimc", .data = &msm8996_bimc},
2089     { .compatible = "qcom,msm8996-cnoc", .data = &msm8996_cnoc},
2090     { .compatible = "qcom,msm8996-mnoc", .data = &msm8996_mnoc},
2091     { .compatible = "qcom,msm8996-pnoc", .data = &msm8996_pnoc},
2092     { .compatible = "qcom,msm8996-snoc", .data = &msm8996_snoc},
2093     { }
2094 };
2095 MODULE_DEVICE_TABLE(of, qnoc_of_match);
2096
2097 static struct platform_driver qnoc_driver = {
2098     .probe = qnoc_probe,
2099     .remove = qnoc_remove,
2100     .driver = {
2101         .name = "qnoc-msm8996",
2102         .of_match_table = qnoc_of_match,
2103         .sync_state = icc_sync_state,
2104     }
2105 };
2106 module_platform_driver(qnoc_driver);
2107
2108 MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
2109 MODULE_DESCRIPTION("Qualcomm MSM8996 NoC driver");
2110 MODULE_LICENSE("GPL v2");