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0030 #include <dt-bindings/interconnect/qcom,msm8974.h>
0031 #include <linux/clk.h>
0032 #include <linux/device.h>
0033 #include <linux/interconnect-provider.h>
0034 #include <linux/io.h>
0035 #include <linux/module.h>
0036 #include <linux/of_device.h>
0037 #include <linux/of_platform.h>
0038 #include <linux/platform_device.h>
0039 #include <linux/slab.h>
0040
0041 #include "smd-rpm.h"
0042
0043 enum {
0044 MSM8974_BIMC_MAS_AMPSS_M0 = 1,
0045 MSM8974_BIMC_MAS_AMPSS_M1,
0046 MSM8974_BIMC_MAS_MSS_PROC,
0047 MSM8974_BIMC_TO_MNOC,
0048 MSM8974_BIMC_TO_SNOC,
0049 MSM8974_BIMC_SLV_EBI_CH0,
0050 MSM8974_BIMC_SLV_AMPSS_L2,
0051 MSM8974_CNOC_MAS_RPM_INST,
0052 MSM8974_CNOC_MAS_RPM_DATA,
0053 MSM8974_CNOC_MAS_RPM_SYS,
0054 MSM8974_CNOC_MAS_DEHR,
0055 MSM8974_CNOC_MAS_QDSS_DAP,
0056 MSM8974_CNOC_MAS_SPDM,
0057 MSM8974_CNOC_MAS_TIC,
0058 MSM8974_CNOC_SLV_CLK_CTL,
0059 MSM8974_CNOC_SLV_CNOC_MSS,
0060 MSM8974_CNOC_SLV_SECURITY,
0061 MSM8974_CNOC_SLV_TCSR,
0062 MSM8974_CNOC_SLV_TLMM,
0063 MSM8974_CNOC_SLV_CRYPTO_0_CFG,
0064 MSM8974_CNOC_SLV_CRYPTO_1_CFG,
0065 MSM8974_CNOC_SLV_IMEM_CFG,
0066 MSM8974_CNOC_SLV_MESSAGE_RAM,
0067 MSM8974_CNOC_SLV_BIMC_CFG,
0068 MSM8974_CNOC_SLV_BOOT_ROM,
0069 MSM8974_CNOC_SLV_PMIC_ARB,
0070 MSM8974_CNOC_SLV_SPDM_WRAPPER,
0071 MSM8974_CNOC_SLV_DEHR_CFG,
0072 MSM8974_CNOC_SLV_MPM,
0073 MSM8974_CNOC_SLV_QDSS_CFG,
0074 MSM8974_CNOC_SLV_RBCPR_CFG,
0075 MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG,
0076 MSM8974_CNOC_TO_SNOC,
0077 MSM8974_CNOC_SLV_CNOC_ONOC_CFG,
0078 MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG,
0079 MSM8974_CNOC_SLV_CNOC_MNOC_CFG,
0080 MSM8974_CNOC_SLV_PNOC_CFG,
0081 MSM8974_CNOC_SLV_SNOC_MPU_CFG,
0082 MSM8974_CNOC_SLV_SNOC_CFG,
0083 MSM8974_CNOC_SLV_EBI1_DLL_CFG,
0084 MSM8974_CNOC_SLV_PHY_APU_CFG,
0085 MSM8974_CNOC_SLV_EBI1_PHY_CFG,
0086 MSM8974_CNOC_SLV_RPM,
0087 MSM8974_CNOC_SLV_SERVICE_CNOC,
0088 MSM8974_MNOC_MAS_GRAPHICS_3D,
0089 MSM8974_MNOC_MAS_JPEG,
0090 MSM8974_MNOC_MAS_MDP_PORT0,
0091 MSM8974_MNOC_MAS_VIDEO_P0,
0092 MSM8974_MNOC_MAS_VIDEO_P1,
0093 MSM8974_MNOC_MAS_VFE,
0094 MSM8974_MNOC_TO_CNOC,
0095 MSM8974_MNOC_TO_BIMC,
0096 MSM8974_MNOC_SLV_CAMERA_CFG,
0097 MSM8974_MNOC_SLV_DISPLAY_CFG,
0098 MSM8974_MNOC_SLV_OCMEM_CFG,
0099 MSM8974_MNOC_SLV_CPR_CFG,
0100 MSM8974_MNOC_SLV_CPR_XPU_CFG,
0101 MSM8974_MNOC_SLV_MISC_CFG,
0102 MSM8974_MNOC_SLV_MISC_XPU_CFG,
0103 MSM8974_MNOC_SLV_VENUS_CFG,
0104 MSM8974_MNOC_SLV_GRAPHICS_3D_CFG,
0105 MSM8974_MNOC_SLV_MMSS_CLK_CFG,
0106 MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG,
0107 MSM8974_MNOC_SLV_MNOC_MPU_CFG,
0108 MSM8974_MNOC_SLV_ONOC_MPU_CFG,
0109 MSM8974_MNOC_SLV_SERVICE_MNOC,
0110 MSM8974_OCMEM_NOC_TO_OCMEM_VNOC,
0111 MSM8974_OCMEM_MAS_JPEG_OCMEM,
0112 MSM8974_OCMEM_MAS_MDP_OCMEM,
0113 MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM,
0114 MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM,
0115 MSM8974_OCMEM_MAS_VFE_OCMEM,
0116 MSM8974_OCMEM_MAS_CNOC_ONOC_CFG,
0117 MSM8974_OCMEM_SLV_SERVICE_ONOC,
0118 MSM8974_OCMEM_VNOC_TO_SNOC,
0119 MSM8974_OCMEM_VNOC_TO_OCMEM_NOC,
0120 MSM8974_OCMEM_VNOC_MAS_GFX3D,
0121 MSM8974_OCMEM_SLV_OCMEM,
0122 MSM8974_PNOC_MAS_PNOC_CFG,
0123 MSM8974_PNOC_MAS_SDCC_1,
0124 MSM8974_PNOC_MAS_SDCC_3,
0125 MSM8974_PNOC_MAS_SDCC_4,
0126 MSM8974_PNOC_MAS_SDCC_2,
0127 MSM8974_PNOC_MAS_TSIF,
0128 MSM8974_PNOC_MAS_BAM_DMA,
0129 MSM8974_PNOC_MAS_BLSP_2,
0130 MSM8974_PNOC_MAS_USB_HSIC,
0131 MSM8974_PNOC_MAS_BLSP_1,
0132 MSM8974_PNOC_MAS_USB_HS,
0133 MSM8974_PNOC_TO_SNOC,
0134 MSM8974_PNOC_SLV_SDCC_1,
0135 MSM8974_PNOC_SLV_SDCC_3,
0136 MSM8974_PNOC_SLV_SDCC_2,
0137 MSM8974_PNOC_SLV_SDCC_4,
0138 MSM8974_PNOC_SLV_TSIF,
0139 MSM8974_PNOC_SLV_BAM_DMA,
0140 MSM8974_PNOC_SLV_BLSP_2,
0141 MSM8974_PNOC_SLV_USB_HSIC,
0142 MSM8974_PNOC_SLV_BLSP_1,
0143 MSM8974_PNOC_SLV_USB_HS,
0144 MSM8974_PNOC_SLV_PDM,
0145 MSM8974_PNOC_SLV_PERIPH_APU_CFG,
0146 MSM8974_PNOC_SLV_PNOC_MPU_CFG,
0147 MSM8974_PNOC_SLV_PRNG,
0148 MSM8974_PNOC_SLV_SERVICE_PNOC,
0149 MSM8974_SNOC_MAS_LPASS_AHB,
0150 MSM8974_SNOC_MAS_QDSS_BAM,
0151 MSM8974_SNOC_MAS_SNOC_CFG,
0152 MSM8974_SNOC_TO_BIMC,
0153 MSM8974_SNOC_TO_CNOC,
0154 MSM8974_SNOC_TO_PNOC,
0155 MSM8974_SNOC_TO_OCMEM_VNOC,
0156 MSM8974_SNOC_MAS_CRYPTO_CORE0,
0157 MSM8974_SNOC_MAS_CRYPTO_CORE1,
0158 MSM8974_SNOC_MAS_LPASS_PROC,
0159 MSM8974_SNOC_MAS_MSS,
0160 MSM8974_SNOC_MAS_MSS_NAV,
0161 MSM8974_SNOC_MAS_OCMEM_DMA,
0162 MSM8974_SNOC_MAS_WCSS,
0163 MSM8974_SNOC_MAS_QDSS_ETR,
0164 MSM8974_SNOC_MAS_USB3,
0165 MSM8974_SNOC_SLV_AMPSS,
0166 MSM8974_SNOC_SLV_LPASS,
0167 MSM8974_SNOC_SLV_USB3,
0168 MSM8974_SNOC_SLV_WCSS,
0169 MSM8974_SNOC_SLV_OCIMEM,
0170 MSM8974_SNOC_SLV_SNOC_OCMEM,
0171 MSM8974_SNOC_SLV_SERVICE_SNOC,
0172 MSM8974_SNOC_SLV_QDSS_STM,
0173 };
0174
0175 #define RPM_BUS_MASTER_REQ 0x73616d62
0176 #define RPM_BUS_SLAVE_REQ 0x766c7362
0177
0178 #define to_msm8974_icc_provider(_provider) \
0179 container_of(_provider, struct msm8974_icc_provider, provider)
0180
0181 static const struct clk_bulk_data msm8974_icc_bus_clocks[] = {
0182 { .id = "bus" },
0183 { .id = "bus_a" },
0184 };
0185
0186
0187
0188
0189
0190
0191
0192 struct msm8974_icc_provider {
0193 struct icc_provider provider;
0194 struct clk_bulk_data *bus_clks;
0195 int num_clks;
0196 };
0197
0198 #define MSM8974_ICC_MAX_LINKS 3
0199
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211 struct msm8974_icc_node {
0212 unsigned char *name;
0213 u16 id;
0214 u16 links[MSM8974_ICC_MAX_LINKS];
0215 u16 num_links;
0216 u16 buswidth;
0217 int mas_rpm_id;
0218 int slv_rpm_id;
0219 u64 rate;
0220 };
0221
0222 struct msm8974_icc_desc {
0223 struct msm8974_icc_node * const *nodes;
0224 size_t num_nodes;
0225 };
0226
0227 #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \
0228 ...) \
0229 static struct msm8974_icc_node _name = { \
0230 .name = #_name, \
0231 .id = _id, \
0232 .buswidth = _buswidth, \
0233 .mas_rpm_id = _mas_rpm_id, \
0234 .slv_rpm_id = _slv_rpm_id, \
0235 .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
0236 .links = { __VA_ARGS__ }, \
0237 }
0238
0239 DEFINE_QNODE(mas_ampss_m0, MSM8974_BIMC_MAS_AMPSS_M0, 8, 0, -1);
0240 DEFINE_QNODE(mas_ampss_m1, MSM8974_BIMC_MAS_AMPSS_M1, 8, 0, -1);
0241 DEFINE_QNODE(mas_mss_proc, MSM8974_BIMC_MAS_MSS_PROC, 8, 1, -1);
0242 DEFINE_QNODE(bimc_to_mnoc, MSM8974_BIMC_TO_MNOC, 8, 2, -1, MSM8974_BIMC_SLV_EBI_CH0);
0243 DEFINE_QNODE(bimc_to_snoc, MSM8974_BIMC_TO_SNOC, 8, 3, 2, MSM8974_SNOC_TO_BIMC, MSM8974_BIMC_SLV_EBI_CH0, MSM8974_BIMC_MAS_AMPSS_M0);
0244 DEFINE_QNODE(slv_ebi_ch0, MSM8974_BIMC_SLV_EBI_CH0, 8, -1, 0);
0245 DEFINE_QNODE(slv_ampss_l2, MSM8974_BIMC_SLV_AMPSS_L2, 8, -1, 1);
0246
0247 static struct msm8974_icc_node * const msm8974_bimc_nodes[] = {
0248 [BIMC_MAS_AMPSS_M0] = &mas_ampss_m0,
0249 [BIMC_MAS_AMPSS_M1] = &mas_ampss_m1,
0250 [BIMC_MAS_MSS_PROC] = &mas_mss_proc,
0251 [BIMC_TO_MNOC] = &bimc_to_mnoc,
0252 [BIMC_TO_SNOC] = &bimc_to_snoc,
0253 [BIMC_SLV_EBI_CH0] = &slv_ebi_ch0,
0254 [BIMC_SLV_AMPSS_L2] = &slv_ampss_l2,
0255 };
0256
0257 static const struct msm8974_icc_desc msm8974_bimc = {
0258 .nodes = msm8974_bimc_nodes,
0259 .num_nodes = ARRAY_SIZE(msm8974_bimc_nodes),
0260 };
0261
0262 DEFINE_QNODE(mas_rpm_inst, MSM8974_CNOC_MAS_RPM_INST, 8, 45, -1);
0263 DEFINE_QNODE(mas_rpm_data, MSM8974_CNOC_MAS_RPM_DATA, 8, 46, -1);
0264 DEFINE_QNODE(mas_rpm_sys, MSM8974_CNOC_MAS_RPM_SYS, 8, 47, -1);
0265 DEFINE_QNODE(mas_dehr, MSM8974_CNOC_MAS_DEHR, 8, 48, -1);
0266 DEFINE_QNODE(mas_qdss_dap, MSM8974_CNOC_MAS_QDSS_DAP, 8, 49, -1);
0267 DEFINE_QNODE(mas_spdm, MSM8974_CNOC_MAS_SPDM, 8, 50, -1);
0268 DEFINE_QNODE(mas_tic, MSM8974_CNOC_MAS_TIC, 8, 51, -1);
0269 DEFINE_QNODE(slv_clk_ctl, MSM8974_CNOC_SLV_CLK_CTL, 8, -1, 47);
0270 DEFINE_QNODE(slv_cnoc_mss, MSM8974_CNOC_SLV_CNOC_MSS, 8, -1, 48);
0271 DEFINE_QNODE(slv_security, MSM8974_CNOC_SLV_SECURITY, 8, -1, 49);
0272 DEFINE_QNODE(slv_tcsr, MSM8974_CNOC_SLV_TCSR, 8, -1, 50);
0273 DEFINE_QNODE(slv_tlmm, MSM8974_CNOC_SLV_TLMM, 8, -1, 51);
0274 DEFINE_QNODE(slv_crypto_0_cfg, MSM8974_CNOC_SLV_CRYPTO_0_CFG, 8, -1, 52);
0275 DEFINE_QNODE(slv_crypto_1_cfg, MSM8974_CNOC_SLV_CRYPTO_1_CFG, 8, -1, 53);
0276 DEFINE_QNODE(slv_imem_cfg, MSM8974_CNOC_SLV_IMEM_CFG, 8, -1, 54);
0277 DEFINE_QNODE(slv_message_ram, MSM8974_CNOC_SLV_MESSAGE_RAM, 8, -1, 55);
0278 DEFINE_QNODE(slv_bimc_cfg, MSM8974_CNOC_SLV_BIMC_CFG, 8, -1, 56);
0279 DEFINE_QNODE(slv_boot_rom, MSM8974_CNOC_SLV_BOOT_ROM, 8, -1, 57);
0280 DEFINE_QNODE(slv_pmic_arb, MSM8974_CNOC_SLV_PMIC_ARB, 8, -1, 59);
0281 DEFINE_QNODE(slv_spdm_wrapper, MSM8974_CNOC_SLV_SPDM_WRAPPER, 8, -1, 60);
0282 DEFINE_QNODE(slv_dehr_cfg, MSM8974_CNOC_SLV_DEHR_CFG, 8, -1, 61);
0283 DEFINE_QNODE(slv_mpm, MSM8974_CNOC_SLV_MPM, 8, -1, 62);
0284 DEFINE_QNODE(slv_qdss_cfg, MSM8974_CNOC_SLV_QDSS_CFG, 8, -1, 63);
0285 DEFINE_QNODE(slv_rbcpr_cfg, MSM8974_CNOC_SLV_RBCPR_CFG, 8, -1, 64);
0286 DEFINE_QNODE(slv_rbcpr_qdss_apu_cfg, MSM8974_CNOC_SLV_RBCPR_QDSS_APU_CFG, 8, -1, 65);
0287 DEFINE_QNODE(cnoc_to_snoc, MSM8974_CNOC_TO_SNOC, 8, 52, 75);
0288 DEFINE_QNODE(slv_cnoc_onoc_cfg, MSM8974_CNOC_SLV_CNOC_ONOC_CFG, 8, -1, 68);
0289 DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, MSM8974_CNOC_SLV_CNOC_MNOC_MMSS_CFG, 8, -1, 58);
0290 DEFINE_QNODE(slv_cnoc_mnoc_cfg, MSM8974_CNOC_SLV_CNOC_MNOC_CFG, 8, -1, 66);
0291 DEFINE_QNODE(slv_pnoc_cfg, MSM8974_CNOC_SLV_PNOC_CFG, 8, -1, 69);
0292 DEFINE_QNODE(slv_snoc_mpu_cfg, MSM8974_CNOC_SLV_SNOC_MPU_CFG, 8, -1, 67);
0293 DEFINE_QNODE(slv_snoc_cfg, MSM8974_CNOC_SLV_SNOC_CFG, 8, -1, 70);
0294 DEFINE_QNODE(slv_ebi1_dll_cfg, MSM8974_CNOC_SLV_EBI1_DLL_CFG, 8, -1, 71);
0295 DEFINE_QNODE(slv_phy_apu_cfg, MSM8974_CNOC_SLV_PHY_APU_CFG, 8, -1, 72);
0296 DEFINE_QNODE(slv_ebi1_phy_cfg, MSM8974_CNOC_SLV_EBI1_PHY_CFG, 8, -1, 73);
0297 DEFINE_QNODE(slv_rpm, MSM8974_CNOC_SLV_RPM, 8, -1, 74);
0298 DEFINE_QNODE(slv_service_cnoc, MSM8974_CNOC_SLV_SERVICE_CNOC, 8, -1, 76);
0299
0300 static struct msm8974_icc_node * const msm8974_cnoc_nodes[] = {
0301 [CNOC_MAS_RPM_INST] = &mas_rpm_inst,
0302 [CNOC_MAS_RPM_DATA] = &mas_rpm_data,
0303 [CNOC_MAS_RPM_SYS] = &mas_rpm_sys,
0304 [CNOC_MAS_DEHR] = &mas_dehr,
0305 [CNOC_MAS_QDSS_DAP] = &mas_qdss_dap,
0306 [CNOC_MAS_SPDM] = &mas_spdm,
0307 [CNOC_MAS_TIC] = &mas_tic,
0308 [CNOC_SLV_CLK_CTL] = &slv_clk_ctl,
0309 [CNOC_SLV_CNOC_MSS] = &slv_cnoc_mss,
0310 [CNOC_SLV_SECURITY] = &slv_security,
0311 [CNOC_SLV_TCSR] = &slv_tcsr,
0312 [CNOC_SLV_TLMM] = &slv_tlmm,
0313 [CNOC_SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
0314 [CNOC_SLV_CRYPTO_1_CFG] = &slv_crypto_1_cfg,
0315 [CNOC_SLV_IMEM_CFG] = &slv_imem_cfg,
0316 [CNOC_SLV_MESSAGE_RAM] = &slv_message_ram,
0317 [CNOC_SLV_BIMC_CFG] = &slv_bimc_cfg,
0318 [CNOC_SLV_BOOT_ROM] = &slv_boot_rom,
0319 [CNOC_SLV_PMIC_ARB] = &slv_pmic_arb,
0320 [CNOC_SLV_SPDM_WRAPPER] = &slv_spdm_wrapper,
0321 [CNOC_SLV_DEHR_CFG] = &slv_dehr_cfg,
0322 [CNOC_SLV_MPM] = &slv_mpm,
0323 [CNOC_SLV_QDSS_CFG] = &slv_qdss_cfg,
0324 [CNOC_SLV_RBCPR_CFG] = &slv_rbcpr_cfg,
0325 [CNOC_SLV_RBCPR_QDSS_APU_CFG] = &slv_rbcpr_qdss_apu_cfg,
0326 [CNOC_TO_SNOC] = &cnoc_to_snoc,
0327 [CNOC_SLV_CNOC_ONOC_CFG] = &slv_cnoc_onoc_cfg,
0328 [CNOC_SLV_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg,
0329 [CNOC_SLV_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
0330 [CNOC_SLV_PNOC_CFG] = &slv_pnoc_cfg,
0331 [CNOC_SLV_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg,
0332 [CNOC_SLV_SNOC_CFG] = &slv_snoc_cfg,
0333 [CNOC_SLV_EBI1_DLL_CFG] = &slv_ebi1_dll_cfg,
0334 [CNOC_SLV_PHY_APU_CFG] = &slv_phy_apu_cfg,
0335 [CNOC_SLV_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg,
0336 [CNOC_SLV_RPM] = &slv_rpm,
0337 [CNOC_SLV_SERVICE_CNOC] = &slv_service_cnoc,
0338 };
0339
0340 static const struct msm8974_icc_desc msm8974_cnoc = {
0341 .nodes = msm8974_cnoc_nodes,
0342 .num_nodes = ARRAY_SIZE(msm8974_cnoc_nodes),
0343 };
0344
0345 DEFINE_QNODE(mas_graphics_3d, MSM8974_MNOC_MAS_GRAPHICS_3D, 16, 6, -1, MSM8974_MNOC_TO_BIMC);
0346 DEFINE_QNODE(mas_jpeg, MSM8974_MNOC_MAS_JPEG, 16, 7, -1, MSM8974_MNOC_TO_BIMC);
0347 DEFINE_QNODE(mas_mdp_port0, MSM8974_MNOC_MAS_MDP_PORT0, 16, 8, -1, MSM8974_MNOC_TO_BIMC);
0348 DEFINE_QNODE(mas_video_p0, MSM8974_MNOC_MAS_VIDEO_P0, 16, 9, -1);
0349 DEFINE_QNODE(mas_video_p1, MSM8974_MNOC_MAS_VIDEO_P1, 16, 10, -1);
0350 DEFINE_QNODE(mas_vfe, MSM8974_MNOC_MAS_VFE, 16, 11, -1, MSM8974_MNOC_TO_BIMC);
0351 DEFINE_QNODE(mnoc_to_cnoc, MSM8974_MNOC_TO_CNOC, 16, 4, -1);
0352 DEFINE_QNODE(mnoc_to_bimc, MSM8974_MNOC_TO_BIMC, 16, -1, 16, MSM8974_BIMC_TO_MNOC);
0353 DEFINE_QNODE(slv_camera_cfg, MSM8974_MNOC_SLV_CAMERA_CFG, 16, -1, 3);
0354 DEFINE_QNODE(slv_display_cfg, MSM8974_MNOC_SLV_DISPLAY_CFG, 16, -1, 4);
0355 DEFINE_QNODE(slv_ocmem_cfg, MSM8974_MNOC_SLV_OCMEM_CFG, 16, -1, 5);
0356 DEFINE_QNODE(slv_cpr_cfg, MSM8974_MNOC_SLV_CPR_CFG, 16, -1, 6);
0357 DEFINE_QNODE(slv_cpr_xpu_cfg, MSM8974_MNOC_SLV_CPR_XPU_CFG, 16, -1, 7);
0358 DEFINE_QNODE(slv_misc_cfg, MSM8974_MNOC_SLV_MISC_CFG, 16, -1, 8);
0359 DEFINE_QNODE(slv_misc_xpu_cfg, MSM8974_MNOC_SLV_MISC_XPU_CFG, 16, -1, 9);
0360 DEFINE_QNODE(slv_venus_cfg, MSM8974_MNOC_SLV_VENUS_CFG, 16, -1, 10);
0361 DEFINE_QNODE(slv_graphics_3d_cfg, MSM8974_MNOC_SLV_GRAPHICS_3D_CFG, 16, -1, 11);
0362 DEFINE_QNODE(slv_mmss_clk_cfg, MSM8974_MNOC_SLV_MMSS_CLK_CFG, 16, -1, 12);
0363 DEFINE_QNODE(slv_mmss_clk_xpu_cfg, MSM8974_MNOC_SLV_MMSS_CLK_XPU_CFG, 16, -1, 13);
0364 DEFINE_QNODE(slv_mnoc_mpu_cfg, MSM8974_MNOC_SLV_MNOC_MPU_CFG, 16, -1, 14);
0365 DEFINE_QNODE(slv_onoc_mpu_cfg, MSM8974_MNOC_SLV_ONOC_MPU_CFG, 16, -1, 15);
0366 DEFINE_QNODE(slv_service_mnoc, MSM8974_MNOC_SLV_SERVICE_MNOC, 16, -1, 17);
0367
0368 static struct msm8974_icc_node * const msm8974_mnoc_nodes[] = {
0369 [MNOC_MAS_GRAPHICS_3D] = &mas_graphics_3d,
0370 [MNOC_MAS_JPEG] = &mas_jpeg,
0371 [MNOC_MAS_MDP_PORT0] = &mas_mdp_port0,
0372 [MNOC_MAS_VIDEO_P0] = &mas_video_p0,
0373 [MNOC_MAS_VIDEO_P1] = &mas_video_p1,
0374 [MNOC_MAS_VFE] = &mas_vfe,
0375 [MNOC_TO_CNOC] = &mnoc_to_cnoc,
0376 [MNOC_TO_BIMC] = &mnoc_to_bimc,
0377 [MNOC_SLV_CAMERA_CFG] = &slv_camera_cfg,
0378 [MNOC_SLV_DISPLAY_CFG] = &slv_display_cfg,
0379 [MNOC_SLV_OCMEM_CFG] = &slv_ocmem_cfg,
0380 [MNOC_SLV_CPR_CFG] = &slv_cpr_cfg,
0381 [MNOC_SLV_CPR_XPU_CFG] = &slv_cpr_xpu_cfg,
0382 [MNOC_SLV_MISC_CFG] = &slv_misc_cfg,
0383 [MNOC_SLV_MISC_XPU_CFG] = &slv_misc_xpu_cfg,
0384 [MNOC_SLV_VENUS_CFG] = &slv_venus_cfg,
0385 [MNOC_SLV_GRAPHICS_3D_CFG] = &slv_graphics_3d_cfg,
0386 [MNOC_SLV_MMSS_CLK_CFG] = &slv_mmss_clk_cfg,
0387 [MNOC_SLV_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg,
0388 [MNOC_SLV_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
0389 [MNOC_SLV_ONOC_MPU_CFG] = &slv_onoc_mpu_cfg,
0390 [MNOC_SLV_SERVICE_MNOC] = &slv_service_mnoc,
0391 };
0392
0393 static const struct msm8974_icc_desc msm8974_mnoc = {
0394 .nodes = msm8974_mnoc_nodes,
0395 .num_nodes = ARRAY_SIZE(msm8974_mnoc_nodes),
0396 };
0397
0398 DEFINE_QNODE(ocmem_noc_to_ocmem_vnoc, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC, 16, 54, 78, MSM8974_OCMEM_SLV_OCMEM);
0399 DEFINE_QNODE(mas_jpeg_ocmem, MSM8974_OCMEM_MAS_JPEG_OCMEM, 16, 13, -1);
0400 DEFINE_QNODE(mas_mdp_ocmem, MSM8974_OCMEM_MAS_MDP_OCMEM, 16, 14, -1);
0401 DEFINE_QNODE(mas_video_p0_ocmem, MSM8974_OCMEM_MAS_VIDEO_P0_OCMEM, 16, 15, -1);
0402 DEFINE_QNODE(mas_video_p1_ocmem, MSM8974_OCMEM_MAS_VIDEO_P1_OCMEM, 16, 16, -1);
0403 DEFINE_QNODE(mas_vfe_ocmem, MSM8974_OCMEM_MAS_VFE_OCMEM, 16, 17, -1);
0404 DEFINE_QNODE(mas_cnoc_onoc_cfg, MSM8974_OCMEM_MAS_CNOC_ONOC_CFG, 16, 12, -1);
0405 DEFINE_QNODE(slv_service_onoc, MSM8974_OCMEM_SLV_SERVICE_ONOC, 16, -1, 19);
0406 DEFINE_QNODE(slv_ocmem, MSM8974_OCMEM_SLV_OCMEM, 16, -1, 18);
0407
0408
0409 DEFINE_QNODE(ocmem_vnoc_to_onoc, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC, 16, 56, 79, MSM8974_OCMEM_NOC_TO_OCMEM_VNOC);
0410 DEFINE_QNODE(ocmem_vnoc_to_snoc, MSM8974_OCMEM_VNOC_TO_SNOC, 8, 57, 80);
0411 DEFINE_QNODE(mas_v_ocmem_gfx3d, MSM8974_OCMEM_VNOC_MAS_GFX3D, 8, 55, -1, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC);
0412
0413 static struct msm8974_icc_node * const msm8974_onoc_nodes[] = {
0414 [OCMEM_NOC_TO_OCMEM_VNOC] = &ocmem_noc_to_ocmem_vnoc,
0415 [OCMEM_MAS_JPEG_OCMEM] = &mas_jpeg_ocmem,
0416 [OCMEM_MAS_MDP_OCMEM] = &mas_mdp_ocmem,
0417 [OCMEM_MAS_VIDEO_P0_OCMEM] = &mas_video_p0_ocmem,
0418 [OCMEM_MAS_VIDEO_P1_OCMEM] = &mas_video_p1_ocmem,
0419 [OCMEM_MAS_VFE_OCMEM] = &mas_vfe_ocmem,
0420 [OCMEM_MAS_CNOC_ONOC_CFG] = &mas_cnoc_onoc_cfg,
0421 [OCMEM_SLV_SERVICE_ONOC] = &slv_service_onoc,
0422 [OCMEM_VNOC_TO_SNOC] = &ocmem_vnoc_to_snoc,
0423 [OCMEM_VNOC_TO_OCMEM_NOC] = &ocmem_vnoc_to_onoc,
0424 [OCMEM_VNOC_MAS_GFX3D] = &mas_v_ocmem_gfx3d,
0425 [OCMEM_SLV_OCMEM] = &slv_ocmem,
0426 };
0427
0428 static const struct msm8974_icc_desc msm8974_onoc = {
0429 .nodes = msm8974_onoc_nodes,
0430 .num_nodes = ARRAY_SIZE(msm8974_onoc_nodes),
0431 };
0432
0433 DEFINE_QNODE(mas_pnoc_cfg, MSM8974_PNOC_MAS_PNOC_CFG, 8, 43, -1);
0434 DEFINE_QNODE(mas_sdcc_1, MSM8974_PNOC_MAS_SDCC_1, 8, 33, -1, MSM8974_PNOC_TO_SNOC);
0435 DEFINE_QNODE(mas_sdcc_3, MSM8974_PNOC_MAS_SDCC_3, 8, 34, -1, MSM8974_PNOC_TO_SNOC);
0436 DEFINE_QNODE(mas_sdcc_4, MSM8974_PNOC_MAS_SDCC_4, 8, 36, -1, MSM8974_PNOC_TO_SNOC);
0437 DEFINE_QNODE(mas_sdcc_2, MSM8974_PNOC_MAS_SDCC_2, 8, 35, -1, MSM8974_PNOC_TO_SNOC);
0438 DEFINE_QNODE(mas_tsif, MSM8974_PNOC_MAS_TSIF, 8, 37, -1, MSM8974_PNOC_TO_SNOC);
0439 DEFINE_QNODE(mas_bam_dma, MSM8974_PNOC_MAS_BAM_DMA, 8, 38, -1);
0440 DEFINE_QNODE(mas_blsp_2, MSM8974_PNOC_MAS_BLSP_2, 8, 39, -1, MSM8974_PNOC_TO_SNOC);
0441 DEFINE_QNODE(mas_usb_hsic, MSM8974_PNOC_MAS_USB_HSIC, 8, 40, -1, MSM8974_PNOC_TO_SNOC);
0442 DEFINE_QNODE(mas_blsp_1, MSM8974_PNOC_MAS_BLSP_1, 8, 41, -1, MSM8974_PNOC_TO_SNOC);
0443 DEFINE_QNODE(mas_usb_hs, MSM8974_PNOC_MAS_USB_HS, 8, 42, -1, MSM8974_PNOC_TO_SNOC);
0444 DEFINE_QNODE(pnoc_to_snoc, MSM8974_PNOC_TO_SNOC, 8, 44, 45, MSM8974_SNOC_TO_PNOC, MSM8974_PNOC_SLV_PRNG);
0445 DEFINE_QNODE(slv_sdcc_1, MSM8974_PNOC_SLV_SDCC_1, 8, -1, 31);
0446 DEFINE_QNODE(slv_sdcc_3, MSM8974_PNOC_SLV_SDCC_3, 8, -1, 32);
0447 DEFINE_QNODE(slv_sdcc_2, MSM8974_PNOC_SLV_SDCC_2, 8, -1, 33);
0448 DEFINE_QNODE(slv_sdcc_4, MSM8974_PNOC_SLV_SDCC_4, 8, -1, 34);
0449 DEFINE_QNODE(slv_tsif, MSM8974_PNOC_SLV_TSIF, 8, -1, 35);
0450 DEFINE_QNODE(slv_bam_dma, MSM8974_PNOC_SLV_BAM_DMA, 8, -1, 36);
0451 DEFINE_QNODE(slv_blsp_2, MSM8974_PNOC_SLV_BLSP_2, 8, -1, 37);
0452 DEFINE_QNODE(slv_usb_hsic, MSM8974_PNOC_SLV_USB_HSIC, 8, -1, 38);
0453 DEFINE_QNODE(slv_blsp_1, MSM8974_PNOC_SLV_BLSP_1, 8, -1, 39);
0454 DEFINE_QNODE(slv_usb_hs, MSM8974_PNOC_SLV_USB_HS, 8, -1, 40);
0455 DEFINE_QNODE(slv_pdm, MSM8974_PNOC_SLV_PDM, 8, -1, 41);
0456 DEFINE_QNODE(slv_periph_apu_cfg, MSM8974_PNOC_SLV_PERIPH_APU_CFG, 8, -1, 42);
0457 DEFINE_QNODE(slv_pnoc_mpu_cfg, MSM8974_PNOC_SLV_PNOC_MPU_CFG, 8, -1, 43);
0458 DEFINE_QNODE(slv_prng, MSM8974_PNOC_SLV_PRNG, 8, -1, 44, MSM8974_PNOC_TO_SNOC);
0459 DEFINE_QNODE(slv_service_pnoc, MSM8974_PNOC_SLV_SERVICE_PNOC, 8, -1, 46);
0460
0461 static struct msm8974_icc_node * const msm8974_pnoc_nodes[] = {
0462 [PNOC_MAS_PNOC_CFG] = &mas_pnoc_cfg,
0463 [PNOC_MAS_SDCC_1] = &mas_sdcc_1,
0464 [PNOC_MAS_SDCC_3] = &mas_sdcc_3,
0465 [PNOC_MAS_SDCC_4] = &mas_sdcc_4,
0466 [PNOC_MAS_SDCC_2] = &mas_sdcc_2,
0467 [PNOC_MAS_TSIF] = &mas_tsif,
0468 [PNOC_MAS_BAM_DMA] = &mas_bam_dma,
0469 [PNOC_MAS_BLSP_2] = &mas_blsp_2,
0470 [PNOC_MAS_USB_HSIC] = &mas_usb_hsic,
0471 [PNOC_MAS_BLSP_1] = &mas_blsp_1,
0472 [PNOC_MAS_USB_HS] = &mas_usb_hs,
0473 [PNOC_TO_SNOC] = &pnoc_to_snoc,
0474 [PNOC_SLV_SDCC_1] = &slv_sdcc_1,
0475 [PNOC_SLV_SDCC_3] = &slv_sdcc_3,
0476 [PNOC_SLV_SDCC_2] = &slv_sdcc_2,
0477 [PNOC_SLV_SDCC_4] = &slv_sdcc_4,
0478 [PNOC_SLV_TSIF] = &slv_tsif,
0479 [PNOC_SLV_BAM_DMA] = &slv_bam_dma,
0480 [PNOC_SLV_BLSP_2] = &slv_blsp_2,
0481 [PNOC_SLV_USB_HSIC] = &slv_usb_hsic,
0482 [PNOC_SLV_BLSP_1] = &slv_blsp_1,
0483 [PNOC_SLV_USB_HS] = &slv_usb_hs,
0484 [PNOC_SLV_PDM] = &slv_pdm,
0485 [PNOC_SLV_PERIPH_APU_CFG] = &slv_periph_apu_cfg,
0486 [PNOC_SLV_PNOC_MPU_CFG] = &slv_pnoc_mpu_cfg,
0487 [PNOC_SLV_PRNG] = &slv_prng,
0488 [PNOC_SLV_SERVICE_PNOC] = &slv_service_pnoc,
0489 };
0490
0491 static const struct msm8974_icc_desc msm8974_pnoc = {
0492 .nodes = msm8974_pnoc_nodes,
0493 .num_nodes = ARRAY_SIZE(msm8974_pnoc_nodes),
0494 };
0495
0496 DEFINE_QNODE(mas_lpass_ahb, MSM8974_SNOC_MAS_LPASS_AHB, 8, 18, -1);
0497 DEFINE_QNODE(mas_qdss_bam, MSM8974_SNOC_MAS_QDSS_BAM, 8, 19, -1);
0498 DEFINE_QNODE(mas_snoc_cfg, MSM8974_SNOC_MAS_SNOC_CFG, 8, 20, -1);
0499 DEFINE_QNODE(snoc_to_bimc, MSM8974_SNOC_TO_BIMC, 8, 21, 24, MSM8974_BIMC_TO_SNOC);
0500 DEFINE_QNODE(snoc_to_cnoc, MSM8974_SNOC_TO_CNOC, 8, 22, 25);
0501 DEFINE_QNODE(snoc_to_pnoc, MSM8974_SNOC_TO_PNOC, 8, 29, 28, MSM8974_PNOC_TO_SNOC);
0502 DEFINE_QNODE(snoc_to_ocmem_vnoc, MSM8974_SNOC_TO_OCMEM_VNOC, 8, 53, 77, MSM8974_OCMEM_VNOC_TO_OCMEM_NOC);
0503 DEFINE_QNODE(mas_crypto_core0, MSM8974_SNOC_MAS_CRYPTO_CORE0, 8, 23, -1, MSM8974_SNOC_TO_BIMC);
0504 DEFINE_QNODE(mas_crypto_core1, MSM8974_SNOC_MAS_CRYPTO_CORE1, 8, 24, -1);
0505 DEFINE_QNODE(mas_lpass_proc, MSM8974_SNOC_MAS_LPASS_PROC, 8, 25, -1, MSM8974_SNOC_TO_OCMEM_VNOC);
0506 DEFINE_QNODE(mas_mss, MSM8974_SNOC_MAS_MSS, 8, 26, -1);
0507 DEFINE_QNODE(mas_mss_nav, MSM8974_SNOC_MAS_MSS_NAV, 8, 27, -1);
0508 DEFINE_QNODE(mas_ocmem_dma, MSM8974_SNOC_MAS_OCMEM_DMA, 8, 28, -1);
0509 DEFINE_QNODE(mas_wcss, MSM8974_SNOC_MAS_WCSS, 8, 30, -1);
0510 DEFINE_QNODE(mas_qdss_etr, MSM8974_SNOC_MAS_QDSS_ETR, 8, 31, -1);
0511 DEFINE_QNODE(mas_usb3, MSM8974_SNOC_MAS_USB3, 8, 32, -1, MSM8974_SNOC_TO_BIMC);
0512 DEFINE_QNODE(slv_ampss, MSM8974_SNOC_SLV_AMPSS, 8, -1, 20);
0513 DEFINE_QNODE(slv_lpass, MSM8974_SNOC_SLV_LPASS, 8, -1, 21);
0514 DEFINE_QNODE(slv_usb3, MSM8974_SNOC_SLV_USB3, 8, -1, 22);
0515 DEFINE_QNODE(slv_wcss, MSM8974_SNOC_SLV_WCSS, 8, -1, 23);
0516 DEFINE_QNODE(slv_ocimem, MSM8974_SNOC_SLV_OCIMEM, 8, -1, 26);
0517 DEFINE_QNODE(slv_snoc_ocmem, MSM8974_SNOC_SLV_SNOC_OCMEM, 8, -1, 27);
0518 DEFINE_QNODE(slv_service_snoc, MSM8974_SNOC_SLV_SERVICE_SNOC, 8, -1, 29);
0519 DEFINE_QNODE(slv_qdss_stm, MSM8974_SNOC_SLV_QDSS_STM, 8, -1, 30);
0520
0521 static struct msm8974_icc_node * const msm8974_snoc_nodes[] = {
0522 [SNOC_MAS_LPASS_AHB] = &mas_lpass_ahb,
0523 [SNOC_MAS_QDSS_BAM] = &mas_qdss_bam,
0524 [SNOC_MAS_SNOC_CFG] = &mas_snoc_cfg,
0525 [SNOC_TO_BIMC] = &snoc_to_bimc,
0526 [SNOC_TO_CNOC] = &snoc_to_cnoc,
0527 [SNOC_TO_PNOC] = &snoc_to_pnoc,
0528 [SNOC_TO_OCMEM_VNOC] = &snoc_to_ocmem_vnoc,
0529 [SNOC_MAS_CRYPTO_CORE0] = &mas_crypto_core0,
0530 [SNOC_MAS_CRYPTO_CORE1] = &mas_crypto_core1,
0531 [SNOC_MAS_LPASS_PROC] = &mas_lpass_proc,
0532 [SNOC_MAS_MSS] = &mas_mss,
0533 [SNOC_MAS_MSS_NAV] = &mas_mss_nav,
0534 [SNOC_MAS_OCMEM_DMA] = &mas_ocmem_dma,
0535 [SNOC_MAS_WCSS] = &mas_wcss,
0536 [SNOC_MAS_QDSS_ETR] = &mas_qdss_etr,
0537 [SNOC_MAS_USB3] = &mas_usb3,
0538 [SNOC_SLV_AMPSS] = &slv_ampss,
0539 [SNOC_SLV_LPASS] = &slv_lpass,
0540 [SNOC_SLV_USB3] = &slv_usb3,
0541 [SNOC_SLV_WCSS] = &slv_wcss,
0542 [SNOC_SLV_OCIMEM] = &slv_ocimem,
0543 [SNOC_SLV_SNOC_OCMEM] = &slv_snoc_ocmem,
0544 [SNOC_SLV_SERVICE_SNOC] = &slv_service_snoc,
0545 [SNOC_SLV_QDSS_STM] = &slv_qdss_stm,
0546 };
0547
0548 static const struct msm8974_icc_desc msm8974_snoc = {
0549 .nodes = msm8974_snoc_nodes,
0550 .num_nodes = ARRAY_SIZE(msm8974_snoc_nodes),
0551 };
0552
0553 static void msm8974_icc_rpm_smd_send(struct device *dev, int rsc_type,
0554 char *name, int id, u64 val)
0555 {
0556 int ret;
0557
0558 if (id == -1)
0559 return;
0560
0561
0562
0563
0564
0565
0566
0567
0568
0569
0570
0571
0572
0573
0574 ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, rsc_type, id,
0575 val);
0576 if (ret)
0577 dev_dbg(dev, "Cannot set bandwidth for node %s (%d): %d\n",
0578 name, id, ret);
0579 }
0580
0581 static int msm8974_icc_set(struct icc_node *src, struct icc_node *dst)
0582 {
0583 struct msm8974_icc_node *src_qn, *dst_qn;
0584 struct msm8974_icc_provider *qp;
0585 u64 sum_bw, max_peak_bw, rate;
0586 u32 agg_avg = 0, agg_peak = 0;
0587 struct icc_provider *provider;
0588 struct icc_node *n;
0589 int ret, i;
0590
0591 src_qn = src->data;
0592 dst_qn = dst->data;
0593 provider = src->provider;
0594 qp = to_msm8974_icc_provider(provider);
0595
0596 list_for_each_entry(n, &provider->nodes, node_list)
0597 provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
0598 &agg_avg, &agg_peak);
0599
0600 sum_bw = icc_units_to_bps(agg_avg);
0601 max_peak_bw = icc_units_to_bps(agg_peak);
0602
0603
0604 msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_MASTER_REQ,
0605 src_qn->name, src_qn->mas_rpm_id, sum_bw);
0606
0607 msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_SLAVE_REQ,
0608 src_qn->name, src_qn->slv_rpm_id, sum_bw);
0609
0610
0611 msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_MASTER_REQ,
0612 dst_qn->name, dst_qn->mas_rpm_id, sum_bw);
0613
0614 msm8974_icc_rpm_smd_send(provider->dev, RPM_BUS_SLAVE_REQ,
0615 dst_qn->name, dst_qn->slv_rpm_id, sum_bw);
0616
0617 rate = max(sum_bw, max_peak_bw);
0618
0619 do_div(rate, src_qn->buswidth);
0620
0621 rate = min_t(u32, rate, INT_MAX);
0622
0623 if (src_qn->rate == rate)
0624 return 0;
0625
0626 for (i = 0; i < qp->num_clks; i++) {
0627 ret = clk_set_rate(qp->bus_clks[i].clk, rate);
0628 if (ret) {
0629 dev_err(provider->dev, "%s clk_set_rate error: %d\n",
0630 qp->bus_clks[i].id, ret);
0631 ret = 0;
0632 }
0633 }
0634
0635 src_qn->rate = rate;
0636
0637 return 0;
0638 }
0639
0640 static int msm8974_get_bw(struct icc_node *node, u32 *avg, u32 *peak)
0641 {
0642 *avg = 0;
0643 *peak = 0;
0644
0645 return 0;
0646 }
0647
0648 static int msm8974_icc_probe(struct platform_device *pdev)
0649 {
0650 const struct msm8974_icc_desc *desc;
0651 struct msm8974_icc_node * const *qnodes;
0652 struct msm8974_icc_provider *qp;
0653 struct device *dev = &pdev->dev;
0654 struct icc_onecell_data *data;
0655 struct icc_provider *provider;
0656 struct icc_node *node;
0657 size_t num_nodes, i;
0658 int ret;
0659
0660
0661 if (!qcom_icc_rpm_smd_available())
0662 return -EPROBE_DEFER;
0663
0664 desc = of_device_get_match_data(dev);
0665 if (!desc)
0666 return -EINVAL;
0667
0668 qnodes = desc->nodes;
0669 num_nodes = desc->num_nodes;
0670
0671 qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL);
0672 if (!qp)
0673 return -ENOMEM;
0674
0675 data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes),
0676 GFP_KERNEL);
0677 if (!data)
0678 return -ENOMEM;
0679
0680 qp->bus_clks = devm_kmemdup(dev, msm8974_icc_bus_clocks,
0681 sizeof(msm8974_icc_bus_clocks), GFP_KERNEL);
0682 if (!qp->bus_clks)
0683 return -ENOMEM;
0684
0685 qp->num_clks = ARRAY_SIZE(msm8974_icc_bus_clocks);
0686 ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
0687 if (ret)
0688 return ret;
0689
0690 ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks);
0691 if (ret)
0692 return ret;
0693
0694 provider = &qp->provider;
0695 INIT_LIST_HEAD(&provider->nodes);
0696 provider->dev = dev;
0697 provider->set = msm8974_icc_set;
0698 provider->aggregate = icc_std_aggregate;
0699 provider->xlate = of_icc_xlate_onecell;
0700 provider->data = data;
0701 provider->get_bw = msm8974_get_bw;
0702
0703 ret = icc_provider_add(provider);
0704 if (ret) {
0705 dev_err(dev, "error adding interconnect provider: %d\n", ret);
0706 goto err_disable_clks;
0707 }
0708
0709 for (i = 0; i < num_nodes; i++) {
0710 size_t j;
0711
0712 node = icc_node_create(qnodes[i]->id);
0713 if (IS_ERR(node)) {
0714 ret = PTR_ERR(node);
0715 goto err_del_icc;
0716 }
0717
0718 node->name = qnodes[i]->name;
0719 node->data = qnodes[i];
0720 icc_node_add(node, provider);
0721
0722 dev_dbg(dev, "registered node %s\n", node->name);
0723
0724
0725 for (j = 0; j < qnodes[i]->num_links; j++)
0726 icc_link_create(node, qnodes[i]->links[j]);
0727
0728 data->nodes[i] = node;
0729 }
0730 data->num_nodes = num_nodes;
0731
0732 platform_set_drvdata(pdev, qp);
0733
0734 return 0;
0735
0736 err_del_icc:
0737 icc_nodes_remove(provider);
0738 icc_provider_del(provider);
0739
0740 err_disable_clks:
0741 clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
0742
0743 return ret;
0744 }
0745
0746 static int msm8974_icc_remove(struct platform_device *pdev)
0747 {
0748 struct msm8974_icc_provider *qp = platform_get_drvdata(pdev);
0749
0750 icc_nodes_remove(&qp->provider);
0751 clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
0752 return icc_provider_del(&qp->provider);
0753 }
0754
0755 static const struct of_device_id msm8974_noc_of_match[] = {
0756 { .compatible = "qcom,msm8974-bimc", .data = &msm8974_bimc},
0757 { .compatible = "qcom,msm8974-cnoc", .data = &msm8974_cnoc},
0758 { .compatible = "qcom,msm8974-mmssnoc", .data = &msm8974_mnoc},
0759 { .compatible = "qcom,msm8974-ocmemnoc", .data = &msm8974_onoc},
0760 { .compatible = "qcom,msm8974-pnoc", .data = &msm8974_pnoc},
0761 { .compatible = "qcom,msm8974-snoc", .data = &msm8974_snoc},
0762 { },
0763 };
0764 MODULE_DEVICE_TABLE(of, msm8974_noc_of_match);
0765
0766 static struct platform_driver msm8974_noc_driver = {
0767 .probe = msm8974_icc_probe,
0768 .remove = msm8974_icc_remove,
0769 .driver = {
0770 .name = "qnoc-msm8974",
0771 .of_match_table = msm8974_noc_of_match,
0772 .sync_state = icc_sync_state,
0773 },
0774 };
0775 module_platform_driver(msm8974_noc_driver);
0776 MODULE_DESCRIPTION("Qualcomm MSM8974 NoC driver");
0777 MODULE_AUTHOR("Brian Masney <masneyb@onstation.org>");
0778 MODULE_LICENSE("GPL v2");
