interconnect/qcom/msm8939.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2020 Linaro Ltd
0004  * Author: Jun Nie <jun.nie@linaro.org>
0005  * With reference of msm8916 interconnect driver of Georgi Djakov.
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/device.h>
0010 #include <linux/interconnect-provider.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/regmap.h>
0015 #include <linux/of_device.h>
0016
0017 #include <dt-bindings/interconnect/qcom,msm8939.h>
0018
0019 #include "smd-rpm.h"
0020 #include "icc-rpm.h"
0021
0022 enum {
0023     MSM8939_BIMC_SNOC_MAS = 1,
0024     MSM8939_BIMC_SNOC_SLV,
0025     MSM8939_MASTER_AMPSS_M0,
0026     MSM8939_MASTER_LPASS,
0027     MSM8939_MASTER_BLSP_1,
0028     MSM8939_MASTER_DEHR,
0029     MSM8939_MASTER_GRAPHICS_3D,
0030     MSM8939_MASTER_JPEG,
0031     MSM8939_MASTER_MDP_PORT0,
0032     MSM8939_MASTER_MDP_PORT1,
0033     MSM8939_MASTER_CPP,
0034     MSM8939_MASTER_CRYPTO_CORE0,
0035     MSM8939_MASTER_SDCC_1,
0036     MSM8939_MASTER_SDCC_2,
0037     MSM8939_MASTER_QDSS_BAM,
0038     MSM8939_MASTER_QDSS_ETR,
0039     MSM8939_MASTER_SNOC_CFG,
0040     MSM8939_MASTER_SPDM,
0041     MSM8939_MASTER_TCU0,
0042     MSM8939_MASTER_USB_HS1,
0043     MSM8939_MASTER_USB_HS2,
0044     MSM8939_MASTER_VFE,
0045     MSM8939_MASTER_VIDEO_P0,
0046     MSM8939_SNOC_MM_INT_0,
0047     MSM8939_SNOC_MM_INT_1,
0048     MSM8939_SNOC_MM_INT_2,
0049     MSM8939_PNOC_INT_0,
0050     MSM8939_PNOC_INT_1,
0051     MSM8939_PNOC_MAS_0,
0052     MSM8939_PNOC_MAS_1,
0053     MSM8939_PNOC_SLV_0,
0054     MSM8939_PNOC_SLV_1,
0055     MSM8939_PNOC_SLV_2,
0056     MSM8939_PNOC_SLV_3,
0057     MSM8939_PNOC_SLV_4,
0058     MSM8939_PNOC_SLV_8,
0059     MSM8939_PNOC_SLV_9,
0060     MSM8939_PNOC_SNOC_MAS,
0061     MSM8939_PNOC_SNOC_SLV,
0062     MSM8939_SNOC_QDSS_INT,
0063     MSM8939_SLAVE_AMPSS_L2,
0064     MSM8939_SLAVE_APSS,
0065     MSM8939_SLAVE_LPASS,
0066     MSM8939_SLAVE_BIMC_CFG,
0067     MSM8939_SLAVE_BLSP_1,
0068     MSM8939_SLAVE_BOOT_ROM,
0069     MSM8939_SLAVE_CAMERA_CFG,
0070     MSM8939_SLAVE_CATS_128,
0071     MSM8939_SLAVE_OCMEM_64,
0072     MSM8939_SLAVE_CLK_CTL,
0073     MSM8939_SLAVE_CRYPTO_0_CFG,
0074     MSM8939_SLAVE_DEHR_CFG,
0075     MSM8939_SLAVE_DISPLAY_CFG,
0076     MSM8939_SLAVE_EBI_CH0,
0077     MSM8939_SLAVE_GRAPHICS_3D_CFG,
0078     MSM8939_SLAVE_IMEM_CFG,
0079     MSM8939_SLAVE_IMEM,
0080     MSM8939_SLAVE_MPM,
0081     MSM8939_SLAVE_MSG_RAM,
0082     MSM8939_SLAVE_MSS,
0083     MSM8939_SLAVE_PDM,
0084     MSM8939_SLAVE_PMIC_ARB,
0085     MSM8939_SLAVE_PNOC_CFG,
0086     MSM8939_SLAVE_PRNG,
0087     MSM8939_SLAVE_QDSS_CFG,
0088     MSM8939_SLAVE_QDSS_STM,
0089     MSM8939_SLAVE_RBCPR_CFG,
0090     MSM8939_SLAVE_SDCC_1,
0091     MSM8939_SLAVE_SDCC_2,
0092     MSM8939_SLAVE_SECURITY,
0093     MSM8939_SLAVE_SNOC_CFG,
0094     MSM8939_SLAVE_SPDM,
0095     MSM8939_SLAVE_SRVC_SNOC,
0096     MSM8939_SLAVE_TCSR,
0097     MSM8939_SLAVE_TLMM,
0098     MSM8939_SLAVE_USB_HS1,
0099     MSM8939_SLAVE_USB_HS2,
0100     MSM8939_SLAVE_VENUS_CFG,
0101     MSM8939_SNOC_BIMC_0_MAS,
0102     MSM8939_SNOC_BIMC_0_SLV,
0103     MSM8939_SNOC_BIMC_1_MAS,
0104     MSM8939_SNOC_BIMC_1_SLV,
0105     MSM8939_SNOC_BIMC_2_MAS,
0106     MSM8939_SNOC_BIMC_2_SLV,
0107     MSM8939_SNOC_INT_0,
0108     MSM8939_SNOC_INT_1,
0109     MSM8939_SNOC_INT_BIMC,
0110     MSM8939_SNOC_PNOC_MAS,
0111     MSM8939_SNOC_PNOC_SLV,
0112 };
0113
0114 static const u16 bimc_snoc_mas_links[] = {
0115     MSM8939_BIMC_SNOC_SLV
0116 };
0117
0118 static struct qcom_icc_node bimc_snoc_mas = {
0119     .name = "bimc_snoc_mas",
0120     .id = MSM8939_BIMC_SNOC_MAS,
0121     .buswidth = 8,
0122     .mas_rpm_id = -1,
0123     .slv_rpm_id = -1,
0124     .qos.ap_owned = true,
0125     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0126     .num_links = ARRAY_SIZE(bimc_snoc_mas_links),
0127     .links = bimc_snoc_mas_links,
0128 };
0129
0130 static const u16 bimc_snoc_slv_links[] = {
0131     MSM8939_SNOC_INT_0,
0132     MSM8939_SNOC_INT_1
0133 };
0134
0135 static struct qcom_icc_node bimc_snoc_slv = {
0136     .name = "bimc_snoc_slv",
0137     .id = MSM8939_BIMC_SNOC_SLV,
0138     .buswidth = 16,
0139     .mas_rpm_id = -1,
0140     .slv_rpm_id = 2,
0141     .num_links = ARRAY_SIZE(bimc_snoc_slv_links),
0142     .links = bimc_snoc_slv_links,
0143 };
0144
0145 static const u16 mas_apss_links[] = {
0146     MSM8939_SLAVE_EBI_CH0,
0147     MSM8939_BIMC_SNOC_MAS,
0148     MSM8939_SLAVE_AMPSS_L2
0149 };
0150
0151 static struct qcom_icc_node mas_apss = {
0152     .name = "mas_apss",
0153     .id = MSM8939_MASTER_AMPSS_M0,
0154     .buswidth = 16,
0155     .mas_rpm_id = -1,
0156     .slv_rpm_id = -1,
0157     .qos.ap_owned = true,
0158     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0159     .qos.areq_prio = 0,
0160     .qos.prio_level = 0,
0161     .qos.qos_port = 0,
0162     .num_links = ARRAY_SIZE(mas_apss_links),
0163     .links = mas_apss_links,
0164 };
0165
0166 static const u16 mas_audio_links[] = {
0167     MSM8939_PNOC_MAS_0
0168 };
0169
0170 static struct qcom_icc_node mas_audio = {
0171     .name = "mas_audio",
0172     .id = MSM8939_MASTER_LPASS,
0173     .buswidth = 4,
0174     .mas_rpm_id = -1,
0175     .slv_rpm_id = -1,
0176     .num_links = ARRAY_SIZE(mas_audio_links),
0177     .links = mas_audio_links,
0178 };
0179
0180 static const u16 mas_blsp_1_links[] = {
0181     MSM8939_PNOC_MAS_1
0182 };
0183
0184 static struct qcom_icc_node mas_blsp_1 = {
0185     .name = "mas_blsp_1",
0186     .id = MSM8939_MASTER_BLSP_1,
0187     .buswidth = 4,
0188     .mas_rpm_id = -1,
0189     .slv_rpm_id = -1,
0190     .num_links = ARRAY_SIZE(mas_blsp_1_links),
0191     .links = mas_blsp_1_links,
0192 };
0193
0194 static const u16 mas_dehr_links[] = {
0195     MSM8939_PNOC_MAS_0
0196 };
0197
0198 static struct qcom_icc_node mas_dehr = {
0199     .name = "mas_dehr",
0200     .id = MSM8939_MASTER_DEHR,
0201     .buswidth = 4,
0202     .mas_rpm_id = -1,
0203     .slv_rpm_id = -1,
0204     .num_links = ARRAY_SIZE(mas_dehr_links),
0205     .links = mas_dehr_links,
0206 };
0207
0208 static const u16 mas_gfx_links[] = {
0209     MSM8939_SLAVE_EBI_CH0,
0210     MSM8939_BIMC_SNOC_MAS,
0211     MSM8939_SLAVE_AMPSS_L2
0212 };
0213
0214 static struct qcom_icc_node mas_gfx = {
0215     .name = "mas_gfx",
0216     .id = MSM8939_MASTER_GRAPHICS_3D,
0217     .buswidth = 16,
0218     .mas_rpm_id = -1,
0219     .slv_rpm_id = -1,
0220     .qos.ap_owned = true,
0221     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0222     .qos.areq_prio = 0,
0223     .qos.prio_level = 0,
0224     .qos.qos_port = 2,
0225     .num_links = ARRAY_SIZE(mas_gfx_links),
0226     .links = mas_gfx_links,
0227 };
0228
0229 static const u16 mas_jpeg_links[] = {
0230     MSM8939_SNOC_MM_INT_0,
0231     MSM8939_SNOC_MM_INT_2
0232 };
0233
0234 static struct qcom_icc_node mas_jpeg = {
0235     .name = "mas_jpeg",
0236     .id = MSM8939_MASTER_JPEG,
0237     .buswidth = 16,
0238     .mas_rpm_id = -1,
0239     .slv_rpm_id = -1,
0240     .qos.ap_owned = true,
0241     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0242     .qos.areq_prio = 0,
0243     .qos.prio_level = 0,
0244     .qos.qos_port = 6,
0245     .num_links = ARRAY_SIZE(mas_jpeg_links),
0246     .links = mas_jpeg_links,
0247 };
0248
0249 static const u16 mas_mdp0_links[] = {
0250     MSM8939_SNOC_MM_INT_1,
0251     MSM8939_SNOC_MM_INT_2
0252 };
0253
0254 static struct qcom_icc_node mas_mdp0 = {
0255     .name = "mas_mdp0",
0256     .id = MSM8939_MASTER_MDP_PORT0,
0257     .buswidth = 16,
0258     .mas_rpm_id = -1,
0259     .slv_rpm_id = -1,
0260     .qos.ap_owned = true,
0261     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0262     .qos.areq_prio = 0,
0263     .qos.prio_level = 0,
0264     .qos.qos_port = 7,
0265     .num_links = ARRAY_SIZE(mas_mdp0_links),
0266     .links = mas_mdp0_links,
0267 };
0268
0269 static const u16 mas_mdp1_links[] = {
0270     MSM8939_SNOC_MM_INT_0,
0271     MSM8939_SNOC_MM_INT_2
0272 };
0273
0274 static struct qcom_icc_node mas_mdp1 = {
0275     .name = "mas_mdp1",
0276     .id = MSM8939_MASTER_MDP_PORT1,
0277     .buswidth = 16,
0278     .mas_rpm_id = -1,
0279     .slv_rpm_id = -1,
0280     .qos.ap_owned = true,
0281     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0282     .qos.areq_prio = 0,
0283     .qos.prio_level = 0,
0284     .qos.qos_port = 13,
0285     .num_links = ARRAY_SIZE(mas_mdp1_links),
0286     .links = mas_mdp1_links,
0287 };
0288
0289 static const u16 mas_cpp_links[] = {
0290     MSM8939_SNOC_MM_INT_0,
0291     MSM8939_SNOC_MM_INT_2
0292 };
0293
0294 static struct qcom_icc_node mas_cpp = {
0295     .name = "mas_cpp",
0296     .id = MSM8939_MASTER_CPP,
0297     .buswidth = 16,
0298     .mas_rpm_id = -1,
0299     .slv_rpm_id = -1,
0300     .qos.ap_owned = true,
0301     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0302     .qos.areq_prio = 0,
0303     .qos.prio_level = 0,
0304     .qos.qos_port = 12,
0305     .num_links = ARRAY_SIZE(mas_cpp_links),
0306     .links = mas_cpp_links,
0307 };
0308
0309 static const u16 mas_pcnoc_crypto_0_links[] = {
0310     MSM8939_PNOC_INT_1
0311 };
0312
0313 static struct qcom_icc_node mas_pcnoc_crypto_0 = {
0314     .name = "mas_pcnoc_crypto_0",
0315     .id = MSM8939_MASTER_CRYPTO_CORE0,
0316     .buswidth = 8,
0317     .mas_rpm_id = -1,
0318     .slv_rpm_id = -1,
0319     .num_links = ARRAY_SIZE(mas_pcnoc_crypto_0_links),
0320     .links = mas_pcnoc_crypto_0_links,
0321 };
0322
0323 static const u16 mas_pcnoc_sdcc_1_links[] = {
0324     MSM8939_PNOC_INT_1
0325 };
0326
0327 static struct qcom_icc_node mas_pcnoc_sdcc_1 = {
0328     .name = "mas_pcnoc_sdcc_1",
0329     .id = MSM8939_MASTER_SDCC_1,
0330     .buswidth = 8,
0331     .mas_rpm_id = -1,
0332     .slv_rpm_id = -1,
0333     .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_1_links),
0334     .links = mas_pcnoc_sdcc_1_links,
0335 };
0336
0337 static const u16 mas_pcnoc_sdcc_2_links[] = {
0338     MSM8939_PNOC_INT_1
0339 };
0340
0341 static struct qcom_icc_node mas_pcnoc_sdcc_2 = {
0342     .name = "mas_pcnoc_sdcc_2",
0343     .id = MSM8939_MASTER_SDCC_2,
0344     .buswidth = 8,
0345     .mas_rpm_id = -1,
0346     .slv_rpm_id = -1,
0347     .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_2_links),
0348     .links = mas_pcnoc_sdcc_2_links,
0349 };
0350
0351 static const u16 mas_qdss_bam_links[] = {
0352     MSM8939_SNOC_QDSS_INT
0353 };
0354
0355 static struct qcom_icc_node mas_qdss_bam = {
0356     .name = "mas_qdss_bam",
0357     .id = MSM8939_MASTER_QDSS_BAM,
0358     .buswidth = 8,
0359     .mas_rpm_id = -1,
0360     .slv_rpm_id = -1,
0361     .qos.ap_owned = true,
0362     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0363     .qos.areq_prio = 1,
0364     .qos.prio_level = 1,
0365     .qos.qos_port = 11,
0366     .num_links = ARRAY_SIZE(mas_qdss_bam_links),
0367     .links = mas_qdss_bam_links,
0368 };
0369
0370 static const u16 mas_qdss_etr_links[] = {
0371     MSM8939_SNOC_QDSS_INT
0372 };
0373
0374 static struct qcom_icc_node mas_qdss_etr = {
0375     .name = "mas_qdss_etr",
0376     .id = MSM8939_MASTER_QDSS_ETR,
0377     .buswidth = 8,
0378     .mas_rpm_id = -1,
0379     .slv_rpm_id = -1,
0380     .qos.ap_owned = true,
0381     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0382     .qos.areq_prio = 1,
0383     .qos.prio_level = 1,
0384     .qos.qos_port = 10,
0385     .num_links = ARRAY_SIZE(mas_qdss_etr_links),
0386     .links = mas_qdss_etr_links,
0387 };
0388
0389 static const u16 mas_snoc_cfg_links[] = {
0390     MSM8939_SLAVE_SRVC_SNOC
0391 };
0392
0393 static struct qcom_icc_node mas_snoc_cfg = {
0394     .name = "mas_snoc_cfg",
0395     .id = MSM8939_MASTER_SNOC_CFG,
0396     .buswidth = 4,
0397     .mas_rpm_id = -1,
0398     .slv_rpm_id = -1,
0399     .num_links = ARRAY_SIZE(mas_snoc_cfg_links),
0400     .links = mas_snoc_cfg_links,
0401 };
0402
0403 static const u16 mas_spdm_links[] = {
0404     MSM8939_PNOC_MAS_0
0405 };
0406
0407 static struct qcom_icc_node mas_spdm = {
0408     .name = "mas_spdm",
0409     .id = MSM8939_MASTER_SPDM,
0410     .buswidth = 4,
0411     .mas_rpm_id = -1,
0412     .slv_rpm_id = -1,
0413     .num_links = ARRAY_SIZE(mas_spdm_links),
0414     .links = mas_spdm_links,
0415 };
0416
0417 static const u16 mas_tcu0_links[] = {
0418     MSM8939_SLAVE_EBI_CH0,
0419     MSM8939_BIMC_SNOC_MAS,
0420     MSM8939_SLAVE_AMPSS_L2
0421 };
0422
0423 static struct qcom_icc_node mas_tcu0 = {
0424     .name = "mas_tcu0",
0425     .id = MSM8939_MASTER_TCU0,
0426     .buswidth = 16,
0427     .mas_rpm_id = -1,
0428     .slv_rpm_id = -1,
0429     .qos.ap_owned = true,
0430     .qos.qos_mode = NOC_QOS_MODE_FIXED,
0431     .qos.areq_prio = 2,
0432     .qos.prio_level = 2,
0433     .qos.qos_port = 6,
0434     .num_links = ARRAY_SIZE(mas_tcu0_links),
0435     .links = mas_tcu0_links,
0436 };
0437
0438 static const u16 mas_usb_hs1_links[] = {
0439     MSM8939_PNOC_MAS_1
0440 };
0441
0442 static struct qcom_icc_node mas_usb_hs1 = {
0443     .name = "mas_usb_hs1",
0444     .id = MSM8939_MASTER_USB_HS1,
0445     .buswidth = 4,
0446     .mas_rpm_id = -1,
0447     .slv_rpm_id = -1,
0448     .num_links = ARRAY_SIZE(mas_usb_hs1_links),
0449     .links = mas_usb_hs1_links,
0450 };
0451
0452 static const u16 mas_usb_hs2_links[] = {
0453     MSM8939_PNOC_MAS_1
0454 };
0455
0456 static struct qcom_icc_node mas_usb_hs2 = {
0457     .name = "mas_usb_hs2",
0458     .id = MSM8939_MASTER_USB_HS2,
0459     .buswidth = 4,
0460     .mas_rpm_id = -1,
0461     .slv_rpm_id = -1,
0462     .num_links = ARRAY_SIZE(mas_usb_hs2_links),
0463     .links = mas_usb_hs2_links,
0464 };
0465
0466 static const u16 mas_vfe_links[] = {
0467     MSM8939_SNOC_MM_INT_1,
0468     MSM8939_SNOC_MM_INT_2
0469 };
0470
0471 static struct qcom_icc_node mas_vfe = {
0472     .name = "mas_vfe",
0473     .id = MSM8939_MASTER_VFE,
0474     .buswidth = 16,
0475     .mas_rpm_id = -1,
0476     .slv_rpm_id = -1,
0477     .qos.ap_owned = true,
0478     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0479     .qos.areq_prio = 0,
0480     .qos.prio_level = 0,
0481     .qos.qos_port = 9,
0482     .num_links = ARRAY_SIZE(mas_vfe_links),
0483     .links = mas_vfe_links,
0484 };
0485
0486 static const u16 mas_video_links[] = {
0487     MSM8939_SNOC_MM_INT_0,
0488     MSM8939_SNOC_MM_INT_2
0489 };
0490
0491 static struct qcom_icc_node mas_video = {
0492     .name = "mas_video",
0493     .id = MSM8939_MASTER_VIDEO_P0,
0494     .buswidth = 16,
0495     .mas_rpm_id = -1,
0496     .slv_rpm_id = -1,
0497     .qos.ap_owned = true,
0498     .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0499     .qos.areq_prio = 0,
0500     .qos.prio_level = 0,
0501     .qos.qos_port = 8,
0502     .num_links = ARRAY_SIZE(mas_video_links),
0503     .links = mas_video_links,
0504 };
0505
0506 static const u16 mm_int_0_links[] = {
0507     MSM8939_SNOC_BIMC_2_MAS
0508 };
0509
0510 static struct qcom_icc_node mm_int_0 = {
0511     .name = "mm_int_0",
0512     .id = MSM8939_SNOC_MM_INT_0,
0513     .buswidth = 16,
0514     .mas_rpm_id = -1,
0515     .slv_rpm_id = -1,
0516     .qos.ap_owned = true,
0517     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0518     .num_links = ARRAY_SIZE(mm_int_0_links),
0519     .links = mm_int_0_links,
0520 };
0521
0522 static const u16 mm_int_1_links[] = {
0523     MSM8939_SNOC_BIMC_1_MAS
0524 };
0525
0526 static struct qcom_icc_node mm_int_1 = {
0527     .name = "mm_int_1",
0528     .id = MSM8939_SNOC_MM_INT_1,
0529     .buswidth = 16,
0530     .mas_rpm_id = -1,
0531     .slv_rpm_id = -1,
0532     .qos.ap_owned = true,
0533     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0534     .num_links = ARRAY_SIZE(mm_int_1_links),
0535     .links = mm_int_1_links,
0536 };
0537
0538 static const u16 mm_int_2_links[] = {
0539     MSM8939_SNOC_INT_0
0540 };
0541
0542 static struct qcom_icc_node mm_int_2 = {
0543     .name = "mm_int_2",
0544     .id = MSM8939_SNOC_MM_INT_2,
0545     .buswidth = 16,
0546     .mas_rpm_id = -1,
0547     .slv_rpm_id = -1,
0548     .qos.ap_owned = true,
0549     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0550     .num_links = ARRAY_SIZE(mm_int_2_links),
0551     .links = mm_int_2_links,
0552 };
0553
0554 static const u16 pcnoc_int_0_links[] = {
0555     MSM8939_PNOC_SNOC_MAS,
0556     MSM8939_PNOC_SLV_0,
0557     MSM8939_PNOC_SLV_1,
0558     MSM8939_PNOC_SLV_2,
0559     MSM8939_PNOC_SLV_3,
0560     MSM8939_PNOC_SLV_4,
0561     MSM8939_PNOC_SLV_8,
0562     MSM8939_PNOC_SLV_9
0563 };
0564
0565 static struct qcom_icc_node pcnoc_int_0 = {
0566     .name = "pcnoc_int_0",
0567     .id = MSM8939_PNOC_INT_0,
0568     .buswidth = 8,
0569     .mas_rpm_id = -1,
0570     .slv_rpm_id = -1,
0571     .num_links = ARRAY_SIZE(pcnoc_int_0_links),
0572     .links = pcnoc_int_0_links,
0573 };
0574
0575 static const u16 pcnoc_int_1_links[] = {
0576     MSM8939_PNOC_SNOC_MAS
0577 };
0578
0579 static struct qcom_icc_node pcnoc_int_1 = {
0580     .name = "pcnoc_int_1",
0581     .id = MSM8939_PNOC_INT_1,
0582     .buswidth = 8,
0583     .mas_rpm_id = -1,
0584     .slv_rpm_id = -1,
0585     .num_links = ARRAY_SIZE(pcnoc_int_1_links),
0586     .links = pcnoc_int_1_links,
0587 };
0588
0589 static const u16 pcnoc_m_0_links[] = {
0590     MSM8939_PNOC_INT_0
0591 };
0592
0593 static struct qcom_icc_node pcnoc_m_0 = {
0594     .name = "pcnoc_m_0",
0595     .id = MSM8939_PNOC_MAS_0,
0596     .buswidth = 8,
0597     .mas_rpm_id = -1,
0598     .slv_rpm_id = -1,
0599     .num_links = ARRAY_SIZE(pcnoc_m_0_links),
0600     .links = pcnoc_m_0_links,
0601 };
0602
0603 static const u16 pcnoc_m_1_links[] = {
0604     MSM8939_PNOC_SNOC_MAS
0605 };
0606
0607 static struct qcom_icc_node pcnoc_m_1 = {
0608     .name = "pcnoc_m_1",
0609     .id = MSM8939_PNOC_MAS_1,
0610     .buswidth = 8,
0611     .mas_rpm_id = -1,
0612     .slv_rpm_id = -1,
0613     .num_links = ARRAY_SIZE(pcnoc_m_1_links),
0614     .links = pcnoc_m_1_links,
0615 };
0616
0617 static const u16 pcnoc_s_0_links[] = {
0618     MSM8939_SLAVE_CLK_CTL,
0619     MSM8939_SLAVE_TLMM,
0620     MSM8939_SLAVE_TCSR,
0621     MSM8939_SLAVE_SECURITY,
0622     MSM8939_SLAVE_MSS
0623 };
0624
0625 static struct qcom_icc_node pcnoc_s_0 = {
0626     .name = "pcnoc_s_0",
0627     .id = MSM8939_PNOC_SLV_0,
0628     .buswidth = 4,
0629     .mas_rpm_id = -1,
0630     .slv_rpm_id = -1,
0631     .num_links = ARRAY_SIZE(pcnoc_s_0_links),
0632     .links = pcnoc_s_0_links,
0633 };
0634
0635 static const u16 pcnoc_s_1_links[] = {
0636     MSM8939_SLAVE_IMEM_CFG,
0637     MSM8939_SLAVE_CRYPTO_0_CFG,
0638     MSM8939_SLAVE_MSG_RAM,
0639     MSM8939_SLAVE_PDM,
0640     MSM8939_SLAVE_PRNG
0641 };
0642
0643 static struct qcom_icc_node pcnoc_s_1 = {
0644     .name = "pcnoc_s_1",
0645     .id = MSM8939_PNOC_SLV_1,
0646     .buswidth = 4,
0647     .mas_rpm_id = -1,
0648     .slv_rpm_id = -1,
0649     .num_links = ARRAY_SIZE(pcnoc_s_1_links),
0650     .links = pcnoc_s_1_links,
0651 };
0652
0653 static const u16 pcnoc_s_2_links[] = {
0654     MSM8939_SLAVE_SPDM,
0655     MSM8939_SLAVE_BOOT_ROM,
0656     MSM8939_SLAVE_BIMC_CFG,
0657     MSM8939_SLAVE_PNOC_CFG,
0658     MSM8939_SLAVE_PMIC_ARB
0659 };
0660
0661 static struct qcom_icc_node pcnoc_s_2 = {
0662     .name = "pcnoc_s_2",
0663     .id = MSM8939_PNOC_SLV_2,
0664     .buswidth = 4,
0665     .mas_rpm_id = -1,
0666     .slv_rpm_id = -1,
0667     .num_links = ARRAY_SIZE(pcnoc_s_2_links),
0668     .links = pcnoc_s_2_links,
0669 };
0670
0671 static const u16 pcnoc_s_3_links[] = {
0672     MSM8939_SLAVE_MPM,
0673     MSM8939_SLAVE_SNOC_CFG,
0674     MSM8939_SLAVE_RBCPR_CFG,
0675     MSM8939_SLAVE_QDSS_CFG,
0676     MSM8939_SLAVE_DEHR_CFG
0677 };
0678
0679 static struct qcom_icc_node pcnoc_s_3 = {
0680     .name = "pcnoc_s_3",
0681     .id = MSM8939_PNOC_SLV_3,
0682     .buswidth = 4,
0683     .mas_rpm_id = -1,
0684     .slv_rpm_id = -1,
0685     .num_links = ARRAY_SIZE(pcnoc_s_3_links),
0686     .links = pcnoc_s_3_links,
0687 };
0688
0689 static const u16 pcnoc_s_4_links[] = {
0690     MSM8939_SLAVE_VENUS_CFG,
0691     MSM8939_SLAVE_CAMERA_CFG,
0692     MSM8939_SLAVE_DISPLAY_CFG
0693 };
0694
0695 static struct qcom_icc_node pcnoc_s_4 = {
0696     .name = "pcnoc_s_4",
0697     .id = MSM8939_PNOC_SLV_4,
0698     .buswidth = 4,
0699     .mas_rpm_id = -1,
0700     .slv_rpm_id = -1,
0701     .num_links = ARRAY_SIZE(pcnoc_s_4_links),
0702     .links = pcnoc_s_4_links,
0703 };
0704
0705 static const u16 pcnoc_s_8_links[] = {
0706     MSM8939_SLAVE_USB_HS1,
0707     MSM8939_SLAVE_SDCC_1,
0708     MSM8939_SLAVE_BLSP_1
0709 };
0710
0711 static struct qcom_icc_node pcnoc_s_8 = {
0712     .name = "pcnoc_s_8",
0713     .id = MSM8939_PNOC_SLV_8,
0714     .buswidth = 4,
0715     .mas_rpm_id = -1,
0716     .slv_rpm_id = -1,
0717     .num_links = ARRAY_SIZE(pcnoc_s_8_links),
0718     .links = pcnoc_s_8_links,
0719 };
0720
0721 static const u16 pcnoc_s_9_links[] = {
0722     MSM8939_SLAVE_SDCC_2,
0723     MSM8939_SLAVE_LPASS,
0724     MSM8939_SLAVE_USB_HS2
0725 };
0726
0727 static struct qcom_icc_node pcnoc_s_9 = {
0728     .name = "pcnoc_s_9",
0729     .id = MSM8939_PNOC_SLV_9,
0730     .buswidth = 4,
0731     .mas_rpm_id = -1,
0732     .slv_rpm_id = -1,
0733     .num_links = ARRAY_SIZE(pcnoc_s_9_links),
0734     .links = pcnoc_s_9_links,
0735 };
0736
0737 static const u16 pcnoc_snoc_mas_links[] = {
0738     MSM8939_PNOC_SNOC_SLV
0739 };
0740
0741 static struct qcom_icc_node pcnoc_snoc_mas = {
0742     .name = "pcnoc_snoc_mas",
0743     .id = MSM8939_PNOC_SNOC_MAS,
0744     .buswidth = 8,
0745     .mas_rpm_id = 29,
0746     .slv_rpm_id = -1,
0747     .num_links = ARRAY_SIZE(pcnoc_snoc_mas_links),
0748     .links = pcnoc_snoc_mas_links,
0749 };
0750
0751 static const u16 pcnoc_snoc_slv_links[] = {
0752     MSM8939_SNOC_INT_0,
0753     MSM8939_SNOC_INT_BIMC,
0754     MSM8939_SNOC_INT_1
0755 };
0756
0757 static struct qcom_icc_node pcnoc_snoc_slv = {
0758     .name = "pcnoc_snoc_slv",
0759     .id = MSM8939_PNOC_SNOC_SLV,
0760     .buswidth = 8,
0761     .mas_rpm_id = -1,
0762     .slv_rpm_id = 45,
0763     .num_links = ARRAY_SIZE(pcnoc_snoc_slv_links),
0764     .links = pcnoc_snoc_slv_links,
0765 };
0766
0767 static const u16 qdss_int_links[] = {
0768     MSM8939_SNOC_INT_0,
0769     MSM8939_SNOC_INT_BIMC
0770 };
0771
0772 static struct qcom_icc_node qdss_int = {
0773     .name = "qdss_int",
0774     .id = MSM8939_SNOC_QDSS_INT,
0775     .buswidth = 8,
0776     .mas_rpm_id = -1,
0777     .slv_rpm_id = -1,
0778     .qos.ap_owned = true,
0779     .qos.qos_mode = NOC_QOS_MODE_INVALID,
0780     .num_links = ARRAY_SIZE(qdss_int_links),
0781     .links = qdss_int_links,
0782 };
0783
0784 static struct qcom_icc_node slv_apps_l2 = {
0785     .name = "slv_apps_l2",
0786     .id = MSM8939_SLAVE_AMPSS_L2,
0787     .buswidth = 16,
0788     .mas_rpm_id = -1,
0789     .slv_rpm_id = -1,
0790 };
0791
0792 static struct qcom_icc_node slv_apss = {
0793     .name = "slv_apss",
0794     .id = MSM8939_SLAVE_APSS,
0795     .buswidth = 4,
0796     .mas_rpm_id = -1,
0797     .slv_rpm_id = -1,
0798 };
0799
0800 static struct qcom_icc_node slv_audio = {
0801     .name = "slv_audio",
0802     .id = MSM8939_SLAVE_LPASS,
0803     .buswidth = 4,
0804     .mas_rpm_id = -1,
0805     .slv_rpm_id = -1,
0806 };
0807
0808 static struct qcom_icc_node slv_bimc_cfg = {
0809     .name = "slv_bimc_cfg",
0810     .id = MSM8939_SLAVE_BIMC_CFG,
0811     .buswidth = 4,
0812     .mas_rpm_id = -1,
0813     .slv_rpm_id = -1,
0814 };
0815
0816 static struct qcom_icc_node slv_blsp_1 = {
0817     .name = "slv_blsp_1",
0818     .id = MSM8939_SLAVE_BLSP_1,
0819     .buswidth = 4,
0820     .mas_rpm_id = -1,
0821     .slv_rpm_id = -1,
0822 };
0823
0824 static struct qcom_icc_node slv_boot_rom = {
0825     .name = "slv_boot_rom",
0826     .id = MSM8939_SLAVE_BOOT_ROM,
0827     .buswidth = 4,
0828     .mas_rpm_id = -1,
0829     .slv_rpm_id = -1,
0830 };
0831
0832 static struct qcom_icc_node slv_camera_cfg = {
0833     .name = "slv_camera_cfg",
0834     .id = MSM8939_SLAVE_CAMERA_CFG,
0835     .buswidth = 4,
0836     .mas_rpm_id = -1,
0837     .slv_rpm_id = -1,
0838 };
0839
0840 static struct qcom_icc_node slv_cats_0 = {
0841     .name = "slv_cats_0",
0842     .id = MSM8939_SLAVE_CATS_128,
0843     .buswidth = 16,
0844     .mas_rpm_id = -1,
0845     .slv_rpm_id = -1,
0846 };
0847
0848 static struct qcom_icc_node slv_cats_1 = {
0849     .name = "slv_cats_1",
0850     .id = MSM8939_SLAVE_OCMEM_64,
0851     .buswidth = 8,
0852     .mas_rpm_id = -1,
0853     .slv_rpm_id = -1,
0854 };
0855
0856 static struct qcom_icc_node slv_clk_ctl = {
0857     .name = "slv_clk_ctl",
0858     .id = MSM8939_SLAVE_CLK_CTL,
0859     .buswidth = 4,
0860     .mas_rpm_id = -1,
0861     .slv_rpm_id = -1,
0862 };
0863
0864 static struct qcom_icc_node slv_crypto_0_cfg = {
0865     .name = "slv_crypto_0_cfg",
0866     .id = MSM8939_SLAVE_CRYPTO_0_CFG,
0867     .buswidth = 4,
0868     .mas_rpm_id = -1,
0869     .slv_rpm_id = -1,
0870 };
0871
0872 static struct qcom_icc_node slv_dehr_cfg = {
0873     .name = "slv_dehr_cfg",
0874     .id = MSM8939_SLAVE_DEHR_CFG,
0875     .buswidth = 4,
0876     .mas_rpm_id = -1,
0877     .slv_rpm_id = -1,
0878 };
0879
0880 static struct qcom_icc_node slv_display_cfg = {
0881     .name = "slv_display_cfg",
0882     .id = MSM8939_SLAVE_DISPLAY_CFG,
0883     .buswidth = 4,
0884     .mas_rpm_id = -1,
0885     .slv_rpm_id = -1,
0886 };
0887
0888 static struct qcom_icc_node slv_ebi_ch0 = {
0889     .name = "slv_ebi_ch0",
0890     .id = MSM8939_SLAVE_EBI_CH0,
0891     .buswidth = 16,
0892     .mas_rpm_id = -1,
0893     .slv_rpm_id = 0,
0894 };
0895
0896 static struct qcom_icc_node slv_gfx_cfg = {
0897     .name = "slv_gfx_cfg",
0898     .id = MSM8939_SLAVE_GRAPHICS_3D_CFG,
0899     .buswidth = 4,
0900     .mas_rpm_id = -1,
0901     .slv_rpm_id = -1,
0902 };
0903
0904 static struct qcom_icc_node slv_imem_cfg = {
0905     .name = "slv_imem_cfg",
0906     .id = MSM8939_SLAVE_IMEM_CFG,
0907     .buswidth = 4,
0908     .mas_rpm_id = -1,
0909     .slv_rpm_id = -1,
0910 };
0911
0912 static struct qcom_icc_node slv_imem = {
0913     .name = "slv_imem",
0914     .id = MSM8939_SLAVE_IMEM,
0915     .buswidth = 8,
0916     .mas_rpm_id = -1,
0917     .slv_rpm_id = 26,
0918 };
0919
0920 static struct qcom_icc_node slv_mpm = {
0921     .name = "slv_mpm",
0922     .id = MSM8939_SLAVE_MPM,
0923     .buswidth = 4,
0924     .mas_rpm_id = -1,
0925     .slv_rpm_id = -1,
0926 };
0927
0928 static struct qcom_icc_node slv_msg_ram = {
0929     .name = "slv_msg_ram",
0930     .id = MSM8939_SLAVE_MSG_RAM,
0931     .buswidth = 4,
0932     .mas_rpm_id = -1,
0933     .slv_rpm_id = -1,
0934 };
0935
0936 static struct qcom_icc_node slv_mss = {
0937     .name = "slv_mss",
0938     .id = MSM8939_SLAVE_MSS,
0939     .buswidth = 4,
0940     .mas_rpm_id = -1,
0941     .slv_rpm_id = -1,
0942 };
0943
0944 static struct qcom_icc_node slv_pdm = {
0945     .name = "slv_pdm",
0946     .id = MSM8939_SLAVE_PDM,
0947     .buswidth = 4,
0948     .mas_rpm_id = -1,
0949     .slv_rpm_id = -1,
0950 };
0951
0952 static struct qcom_icc_node slv_pmic_arb = {
0953     .name = "slv_pmic_arb",
0954     .id = MSM8939_SLAVE_PMIC_ARB,
0955     .buswidth = 4,
0956     .mas_rpm_id = -1,
0957     .slv_rpm_id = -1,
0958 };
0959
0960 static struct qcom_icc_node slv_pcnoc_cfg = {
0961     .name = "slv_pcnoc_cfg",
0962     .id = MSM8939_SLAVE_PNOC_CFG,
0963     .buswidth = 4,
0964     .mas_rpm_id = -1,
0965     .slv_rpm_id = -1,
0966 };
0967
0968 static struct qcom_icc_node slv_prng = {
0969     .name = "slv_prng",
0970     .id = MSM8939_SLAVE_PRNG,
0971     .buswidth = 4,
0972     .mas_rpm_id = -1,
0973     .slv_rpm_id = -1,
0974 };
0975
0976 static struct qcom_icc_node slv_qdss_cfg = {
0977     .name = "slv_qdss_cfg",
0978     .id = MSM8939_SLAVE_QDSS_CFG,
0979     .buswidth = 4,
0980     .mas_rpm_id = -1,
0981     .slv_rpm_id = -1,
0982 };
0983
0984 static struct qcom_icc_node slv_qdss_stm = {
0985     .name = "slv_qdss_stm",
0986     .id = MSM8939_SLAVE_QDSS_STM,
0987     .buswidth = 4,
0988     .mas_rpm_id = -1,
0989     .slv_rpm_id = 30,
0990 };
0991
0992 static struct qcom_icc_node slv_rbcpr_cfg = {
0993     .name = "slv_rbcpr_cfg",
0994     .id = MSM8939_SLAVE_RBCPR_CFG,
0995     .buswidth = 4,
0996     .mas_rpm_id = -1,
0997     .slv_rpm_id = -1,
0998 };
0999
1000 static struct qcom_icc_node slv_sdcc_1 = {
1001     .name = "slv_sdcc_1",
1002     .id = MSM8939_SLAVE_SDCC_1,
1003     .buswidth = 4,
1004     .mas_rpm_id = -1,
1005     .slv_rpm_id = -1,
1006 };
1007
1008 static struct qcom_icc_node slv_sdcc_2 = {
1009     .name = "slv_sdcc_2",
1010     .id = MSM8939_SLAVE_SDCC_2,
1011     .buswidth = 4,
1012     .mas_rpm_id = -1,
1013     .slv_rpm_id = -1,
1014 };
1015
1016 static struct qcom_icc_node slv_security = {
1017     .name = "slv_security",
1018     .id = MSM8939_SLAVE_SECURITY,
1019     .buswidth = 4,
1020     .mas_rpm_id = -1,
1021     .slv_rpm_id = -1,
1022 };
1023
1024 static struct qcom_icc_node slv_snoc_cfg = {
1025     .name = "slv_snoc_cfg",
1026     .id = MSM8939_SLAVE_SNOC_CFG,
1027     .buswidth = 4,
1028     .mas_rpm_id = -1,
1029     .slv_rpm_id = -1,
1030 };
1031
1032 static struct qcom_icc_node slv_spdm = {
1033     .name = "slv_spdm",
1034     .id = MSM8939_SLAVE_SPDM,
1035     .buswidth = 4,
1036     .mas_rpm_id = -1,
1037     .slv_rpm_id = -1,
1038 };
1039
1040 static struct qcom_icc_node slv_srvc_snoc = {
1041     .name = "slv_srvc_snoc",
1042     .id = MSM8939_SLAVE_SRVC_SNOC,
1043     .buswidth = 8,
1044     .mas_rpm_id = -1,
1045     .slv_rpm_id = -1,
1046 };
1047
1048 static struct qcom_icc_node slv_tcsr = {
1049     .name = "slv_tcsr",
1050     .id = MSM8939_SLAVE_TCSR,
1051     .buswidth = 4,
1052     .mas_rpm_id = -1,
1053     .slv_rpm_id = -1,
1054 };
1055
1056 static struct qcom_icc_node slv_tlmm = {
1057     .name = "slv_tlmm",
1058     .id = MSM8939_SLAVE_TLMM,
1059     .buswidth = 4,
1060     .mas_rpm_id = -1,
1061     .slv_rpm_id = -1,
1062 };
1063
1064 static struct qcom_icc_node slv_usb_hs1 = {
1065     .name = "slv_usb_hs1",
1066     .id = MSM8939_SLAVE_USB_HS1,
1067     .buswidth = 4,
1068     .mas_rpm_id = -1,
1069     .slv_rpm_id = -1,
1070 };
1071
1072 static struct qcom_icc_node slv_usb_hs2 = {
1073     .name = "slv_usb_hs2",
1074     .id = MSM8939_SLAVE_USB_HS2,
1075     .buswidth = 4,
1076     .mas_rpm_id = -1,
1077     .slv_rpm_id = -1,
1078 };
1079
1080 static struct qcom_icc_node slv_venus_cfg = {
1081     .name = "slv_venus_cfg",
1082     .id = MSM8939_SLAVE_VENUS_CFG,
1083     .buswidth = 4,
1084     .mas_rpm_id = -1,
1085     .slv_rpm_id = -1,
1086 };
1087
1088 static const u16 snoc_bimc_0_mas_links[] = {
1089     MSM8939_SNOC_BIMC_0_SLV
1090 };
1091
1092 static struct qcom_icc_node snoc_bimc_0_mas = {
1093     .name = "snoc_bimc_0_mas",
1094     .id = MSM8939_SNOC_BIMC_0_MAS,
1095     .buswidth = 16,
1096     .mas_rpm_id = -1,
1097     .slv_rpm_id = -1,
1098     .qos.ap_owned = true,
1099     .qos.qos_mode = NOC_QOS_MODE_INVALID,
1100     .num_links = ARRAY_SIZE(snoc_bimc_0_mas_links),
1101     .links = snoc_bimc_0_mas_links,
1102 };
1103
1104 static const u16 snoc_bimc_0_slv_links[] = {
1105     MSM8939_SLAVE_EBI_CH0
1106 };
1107
1108 static struct qcom_icc_node snoc_bimc_0_slv = {
1109     .name = "snoc_bimc_0_slv",
1110     .id = MSM8939_SNOC_BIMC_0_SLV,
1111     .buswidth = 16,
1112     .mas_rpm_id = -1,
1113     .slv_rpm_id = -1,
1114     .qos.ap_owned = true,
1115     .qos.qos_mode = NOC_QOS_MODE_INVALID,
1116     .num_links = ARRAY_SIZE(snoc_bimc_0_slv_links),
1117     .links = snoc_bimc_0_slv_links,
1118 };
1119
1120 static const u16 snoc_bimc_1_mas_links[] = {
1121     MSM8939_SNOC_BIMC_1_SLV
1122 };
1123
1124 static struct qcom_icc_node snoc_bimc_1_mas = {
1125     .name = "snoc_bimc_1_mas",
1126     .id = MSM8939_SNOC_BIMC_1_MAS,
1127     .buswidth = 16,
1128     .mas_rpm_id = 76,
1129     .slv_rpm_id = -1,
1130     .num_links = ARRAY_SIZE(snoc_bimc_1_mas_links),
1131     .links = snoc_bimc_1_mas_links,
1132 };
1133
1134 static const u16 snoc_bimc_1_slv_links[] = {
1135     MSM8939_SLAVE_EBI_CH0
1136 };
1137
1138 static struct qcom_icc_node snoc_bimc_1_slv = {
1139     .name = "snoc_bimc_1_slv",
1140     .id = MSM8939_SNOC_BIMC_1_SLV,
1141     .buswidth = 16,
1142     .mas_rpm_id = -1,
1143     .slv_rpm_id = 104,
1144     .num_links = ARRAY_SIZE(snoc_bimc_1_slv_links),
1145     .links = snoc_bimc_1_slv_links,
1146 };
1147
1148 static const u16 snoc_bimc_2_mas_links[] = {
1149     MSM8939_SNOC_BIMC_2_SLV
1150 };
1151
1152 static struct qcom_icc_node snoc_bimc_2_mas = {
1153     .name = "snoc_bimc_2_mas",
1154     .id = MSM8939_SNOC_BIMC_2_MAS,
1155     .buswidth = 16,
1156     .mas_rpm_id = -1,
1157     .slv_rpm_id = -1,
1158     .qos.ap_owned = true,
1159     .qos.qos_mode = NOC_QOS_MODE_INVALID,
1160     .num_links = ARRAY_SIZE(snoc_bimc_2_mas_links),
1161     .links = snoc_bimc_2_mas_links,
1162 };
1163
1164 static const u16 snoc_bimc_2_slv_links[] = {
1165     MSM8939_SLAVE_EBI_CH0
1166 };
1167
1168 static struct qcom_icc_node snoc_bimc_2_slv = {
1169     .name = "snoc_bimc_2_slv",
1170     .id = MSM8939_SNOC_BIMC_2_SLV,
1171     .buswidth = 16,
1172     .mas_rpm_id = -1,
1173     .slv_rpm_id = -1,
1174     .qos.ap_owned = true,
1175     .qos.qos_mode = NOC_QOS_MODE_INVALID,
1176     .num_links = ARRAY_SIZE(snoc_bimc_2_slv_links),
1177     .links = snoc_bimc_2_slv_links,
1178 };
1179
1180 static const u16 snoc_int_0_links[] = {
1181     MSM8939_SLAVE_QDSS_STM,
1182     MSM8939_SLAVE_IMEM,
1183     MSM8939_SNOC_PNOC_MAS
1184 };
1185
1186 static struct qcom_icc_node snoc_int_0 = {
1187     .name = "snoc_int_0",
1188     .id = MSM8939_SNOC_INT_0,
1189     .buswidth = 8,
1190     .mas_rpm_id = 99,
1191     .slv_rpm_id = 130,
1192     .num_links = ARRAY_SIZE(snoc_int_0_links),
1193     .links = snoc_int_0_links,
1194 };
1195
1196 static const u16 snoc_int_1_links[] = {
1197     MSM8939_SLAVE_APSS,
1198     MSM8939_SLAVE_CATS_128,
1199     MSM8939_SLAVE_OCMEM_64
1200 };
1201
1202 static struct qcom_icc_node snoc_int_1 = {
1203     .name = "snoc_int_1",
1204     .id = MSM8939_SNOC_INT_1,
1205     .buswidth = 8,
1206     .mas_rpm_id = -1,
1207     .slv_rpm_id = -1,
1208     .num_links = ARRAY_SIZE(snoc_int_1_links),
1209     .links = snoc_int_1_links,
1210 };
1211
1212 static const u16 snoc_int_bimc_links[] = {
1213     MSM8939_SNOC_BIMC_1_MAS
1214 };
1215
1216 static struct qcom_icc_node snoc_int_bimc = {
1217     .name = "snoc_int_bimc",
1218     .id = MSM8939_SNOC_INT_BIMC,
1219     .buswidth = 8,
1220     .mas_rpm_id = 101,
1221     .slv_rpm_id = 132,
1222     .num_links = ARRAY_SIZE(snoc_int_bimc_links),
1223     .links = snoc_int_bimc_links,
1224 };
1225
1226 static const u16 snoc_pcnoc_mas_links[] = {
1227     MSM8939_SNOC_PNOC_SLV
1228 };
1229
1230 static struct qcom_icc_node snoc_pcnoc_mas = {
1231     .name = "snoc_pcnoc_mas",
1232     .id = MSM8939_SNOC_PNOC_MAS,
1233     .buswidth = 8,
1234     .mas_rpm_id = -1,
1235     .slv_rpm_id = -1,
1236     .num_links = ARRAY_SIZE(snoc_pcnoc_mas_links),
1237     .links = snoc_pcnoc_mas_links,
1238 };
1239
1240 static const u16 snoc_pcnoc_slv_links[] = {
1241     MSM8939_PNOC_INT_0
1242 };
1243
1244 static struct qcom_icc_node snoc_pcnoc_slv = {
1245     .name = "snoc_pcnoc_slv",
1246     .id = MSM8939_SNOC_PNOC_SLV,
1247     .buswidth = 8,
1248     .mas_rpm_id = -1,
1249     .slv_rpm_id = -1,
1250     .num_links = ARRAY_SIZE(snoc_pcnoc_slv_links),
1251     .links = snoc_pcnoc_slv_links,
1252 };
1253
1254 static struct qcom_icc_node * const msm8939_snoc_nodes[] = {
1255     [BIMC_SNOC_SLV] = &bimc_snoc_slv,
1256     [MASTER_QDSS_BAM] = &mas_qdss_bam,
1257     [MASTER_QDSS_ETR] = &mas_qdss_etr,
1258     [MASTER_SNOC_CFG] = &mas_snoc_cfg,
1259     [PCNOC_SNOC_SLV] = &pcnoc_snoc_slv,
1260     [SLAVE_APSS] = &slv_apss,
1261     [SLAVE_CATS_128] = &slv_cats_0,
1262     [SLAVE_OCMEM_64] = &slv_cats_1,
1263     [SLAVE_IMEM] = &slv_imem,
1264     [SLAVE_QDSS_STM] = &slv_qdss_stm,
1265     [SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
1266     [SNOC_BIMC_0_MAS] = &snoc_bimc_0_mas,
1267     [SNOC_BIMC_1_MAS] = &snoc_bimc_1_mas,
1268     [SNOC_BIMC_2_MAS] = &snoc_bimc_2_mas,
1269     [SNOC_INT_0] = &snoc_int_0,
1270     [SNOC_INT_1] = &snoc_int_1,
1271     [SNOC_INT_BIMC] = &snoc_int_bimc,
1272     [SNOC_PCNOC_MAS] = &snoc_pcnoc_mas,
1273     [SNOC_QDSS_INT] = &qdss_int,
1274 };
1275
1276 static const struct regmap_config msm8939_snoc_regmap_config = {
1277     .reg_bits   = 32,
1278     .reg_stride = 4,
1279     .val_bits   = 32,
1280     .max_register   = 0x14080,
1281     .fast_io    = true,
1282 };
1283
1284 static const struct qcom_icc_desc msm8939_snoc = {
1285     .type = QCOM_ICC_NOC,
1286     .nodes = msm8939_snoc_nodes,
1287     .num_nodes = ARRAY_SIZE(msm8939_snoc_nodes),
1288     .regmap_cfg = &msm8939_snoc_regmap_config,
1289     .qos_offset = 0x7000,
1290 };
1291
1292 static struct qcom_icc_node * const msm8939_snoc_mm_nodes[] = {
1293     [MASTER_VIDEO_P0] = &mas_video,
1294     [MASTER_JPEG] = &mas_jpeg,
1295     [MASTER_VFE] = &mas_vfe,
1296     [MASTER_MDP_PORT0] = &mas_mdp0,
1297     [MASTER_MDP_PORT1] = &mas_mdp1,
1298     [MASTER_CPP] = &mas_cpp,
1299     [SNOC_MM_INT_0] = &mm_int_0,
1300     [SNOC_MM_INT_1] = &mm_int_1,
1301     [SNOC_MM_INT_2] = &mm_int_2,
1302 };
1303
1304 static const struct qcom_icc_desc msm8939_snoc_mm = {
1305     .type = QCOM_ICC_NOC,
1306     .nodes = msm8939_snoc_mm_nodes,
1307     .num_nodes = ARRAY_SIZE(msm8939_snoc_mm_nodes),
1308     .regmap_cfg = &msm8939_snoc_regmap_config,
1309     .qos_offset = 0x7000,
1310 };
1311
1312 static struct qcom_icc_node * const msm8939_bimc_nodes[] = {
1313     [BIMC_SNOC_MAS] = &bimc_snoc_mas,
1314     [MASTER_AMPSS_M0] = &mas_apss,
1315     [MASTER_GRAPHICS_3D] = &mas_gfx,
1316     [MASTER_TCU0] = &mas_tcu0,
1317     [SLAVE_AMPSS_L2] = &slv_apps_l2,
1318     [SLAVE_EBI_CH0] = &slv_ebi_ch0,
1319     [SNOC_BIMC_0_SLV] = &snoc_bimc_0_slv,
1320     [SNOC_BIMC_1_SLV] = &snoc_bimc_1_slv,
1321     [SNOC_BIMC_2_SLV] = &snoc_bimc_2_slv,
1322 };
1323
1324 static const struct regmap_config msm8939_bimc_regmap_config = {
1325     .reg_bits   = 32,
1326     .reg_stride = 4,
1327     .val_bits   = 32,
1328     .max_register   = 0x62000,
1329     .fast_io    = true,
1330 };
1331
1332 static const struct qcom_icc_desc msm8939_bimc = {
1333     .type = QCOM_ICC_BIMC,
1334     .nodes = msm8939_bimc_nodes,
1335     .num_nodes = ARRAY_SIZE(msm8939_bimc_nodes),
1336     .regmap_cfg = &msm8939_bimc_regmap_config,
1337     .qos_offset = 0x8000,
1338 };
1339
1340 static struct qcom_icc_node * const msm8939_pcnoc_nodes[] = {
1341     [MASTER_BLSP_1] = &mas_blsp_1,
1342     [MASTER_DEHR] = &mas_dehr,
1343     [MASTER_LPASS] = &mas_audio,
1344     [MASTER_CRYPTO_CORE0] = &mas_pcnoc_crypto_0,
1345     [MASTER_SDCC_1] = &mas_pcnoc_sdcc_1,
1346     [MASTER_SDCC_2] = &mas_pcnoc_sdcc_2,
1347     [MASTER_SPDM] = &mas_spdm,
1348     [MASTER_USB_HS1] = &mas_usb_hs1,
1349     [MASTER_USB_HS2] = &mas_usb_hs2,
1350     [PCNOC_INT_0] = &pcnoc_int_0,
1351     [PCNOC_INT_1] = &pcnoc_int_1,
1352     [PCNOC_MAS_0] = &pcnoc_m_0,
1353     [PCNOC_MAS_1] = &pcnoc_m_1,
1354     [PCNOC_SLV_0] = &pcnoc_s_0,
1355     [PCNOC_SLV_1] = &pcnoc_s_1,
1356     [PCNOC_SLV_2] = &pcnoc_s_2,
1357     [PCNOC_SLV_3] = &pcnoc_s_3,
1358     [PCNOC_SLV_4] = &pcnoc_s_4,
1359     [PCNOC_SLV_8] = &pcnoc_s_8,
1360     [PCNOC_SLV_9] = &pcnoc_s_9,
1361     [PCNOC_SNOC_MAS] = &pcnoc_snoc_mas,
1362     [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1363     [SLAVE_BLSP_1] = &slv_blsp_1,
1364     [SLAVE_BOOT_ROM] = &slv_boot_rom,
1365     [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1366     [SLAVE_CLK_CTL] = &slv_clk_ctl,
1367     [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1368     [SLAVE_DEHR_CFG] = &slv_dehr_cfg,
1369     [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1370     [SLAVE_GRAPHICS_3D_CFG] = &slv_gfx_cfg,
1371     [SLAVE_IMEM_CFG] = &slv_imem_cfg,
1372     [SLAVE_LPASS] = &slv_audio,
1373     [SLAVE_MPM] = &slv_mpm,
1374     [SLAVE_MSG_RAM] = &slv_msg_ram,
1375     [SLAVE_MSS] = &slv_mss,
1376     [SLAVE_PDM] = &slv_pdm,
1377     [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1378     [SLAVE_PCNOC_CFG] = &slv_pcnoc_cfg,
1379     [SLAVE_PRNG] = &slv_prng,
1380     [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1381     [SLAVE_RBCPR_CFG] = &slv_rbcpr_cfg,
1382     [SLAVE_SDCC_1] = &slv_sdcc_1,
1383     [SLAVE_SDCC_2] = &slv_sdcc_2,
1384     [SLAVE_SECURITY] = &slv_security,
1385     [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1386     [SLAVE_SPDM] = &slv_spdm,
1387     [SLAVE_TCSR] = &slv_tcsr,
1388     [SLAVE_TLMM] = &slv_tlmm,
1389     [SLAVE_USB_HS1] = &slv_usb_hs1,
1390     [SLAVE_USB_HS2] = &slv_usb_hs2,
1391     [SLAVE_VENUS_CFG] = &slv_venus_cfg,
1392     [SNOC_PCNOC_SLV] = &snoc_pcnoc_slv,
1393 };
1394
1395 static const struct regmap_config msm8939_pcnoc_regmap_config = {
1396     .reg_bits   = 32,
1397     .reg_stride = 4,
1398     .val_bits   = 32,
1399     .max_register   = 0x11000,
1400     .fast_io    = true,
1401 };
1402
1403 static const struct qcom_icc_desc msm8939_pcnoc = {
1404     .type = QCOM_ICC_NOC,
1405     .nodes = msm8939_pcnoc_nodes,
1406     .num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes),
1407     .regmap_cfg = &msm8939_pcnoc_regmap_config,
1408     .qos_offset = 0x7000,
1409 };
1410
1411 static const struct of_device_id msm8939_noc_of_match[] = {
1412     { .compatible = "qcom,msm8939-bimc", .data = &msm8939_bimc },
1413     { .compatible = "qcom,msm8939-pcnoc", .data = &msm8939_pcnoc },
1414     { .compatible = "qcom,msm8939-snoc", .data = &msm8939_snoc },
1415     { .compatible = "qcom,msm8939-snoc-mm", .data = &msm8939_snoc_mm },
1416     { }
1417 };
1418 MODULE_DEVICE_TABLE(of, msm8939_noc_of_match);
1419
1420 static struct platform_driver msm8939_noc_driver = {
1421     .probe = qnoc_probe,
1422     .remove = qnoc_remove,
1423     .driver = {
1424         .name = "qnoc-msm8939",
1425         .of_match_table = msm8939_noc_of_match,
1426         .sync_state = icc_sync_state,
1427     },
1428 };
1429 module_platform_driver(msm8939_noc_driver);
1430 MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
1431 MODULE_DESCRIPTION("Qualcomm MSM8939 NoC driver");
1432 MODULE_LICENSE("GPL v2");