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0007 #include <linux/clk.h>
0008 #include <linux/device.h>
0009 #include <linux/interconnect-provider.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/regmap.h>
0014 #include <linux/of_device.h>
0015
0016 #include <dt-bindings/interconnect/qcom,msm8916.h>
0017
0018 #include "smd-rpm.h"
0019 #include "icc-rpm.h"
0020
0021 enum {
0022 MSM8916_BIMC_SNOC_MAS = 1,
0023 MSM8916_BIMC_SNOC_SLV,
0024 MSM8916_MASTER_AMPSS_M0,
0025 MSM8916_MASTER_LPASS,
0026 MSM8916_MASTER_BLSP_1,
0027 MSM8916_MASTER_DEHR,
0028 MSM8916_MASTER_GRAPHICS_3D,
0029 MSM8916_MASTER_JPEG,
0030 MSM8916_MASTER_MDP_PORT0,
0031 MSM8916_MASTER_CRYPTO_CORE0,
0032 MSM8916_MASTER_SDCC_1,
0033 MSM8916_MASTER_SDCC_2,
0034 MSM8916_MASTER_QDSS_BAM,
0035 MSM8916_MASTER_QDSS_ETR,
0036 MSM8916_MASTER_SNOC_CFG,
0037 MSM8916_MASTER_SPDM,
0038 MSM8916_MASTER_TCU0,
0039 MSM8916_MASTER_TCU1,
0040 MSM8916_MASTER_USB_HS,
0041 MSM8916_MASTER_VFE,
0042 MSM8916_MASTER_VIDEO_P0,
0043 MSM8916_SNOC_MM_INT_0,
0044 MSM8916_SNOC_MM_INT_1,
0045 MSM8916_SNOC_MM_INT_2,
0046 MSM8916_SNOC_MM_INT_BIMC,
0047 MSM8916_PNOC_INT_0,
0048 MSM8916_PNOC_INT_1,
0049 MSM8916_PNOC_MAS_0,
0050 MSM8916_PNOC_MAS_1,
0051 MSM8916_PNOC_SLV_0,
0052 MSM8916_PNOC_SLV_1,
0053 MSM8916_PNOC_SLV_2,
0054 MSM8916_PNOC_SLV_3,
0055 MSM8916_PNOC_SLV_4,
0056 MSM8916_PNOC_SLV_8,
0057 MSM8916_PNOC_SLV_9,
0058 MSM8916_PNOC_SNOC_MAS,
0059 MSM8916_PNOC_SNOC_SLV,
0060 MSM8916_SNOC_QDSS_INT,
0061 MSM8916_SLAVE_AMPSS_L2,
0062 MSM8916_SLAVE_APSS,
0063 MSM8916_SLAVE_LPASS,
0064 MSM8916_SLAVE_BIMC_CFG,
0065 MSM8916_SLAVE_BLSP_1,
0066 MSM8916_SLAVE_BOOT_ROM,
0067 MSM8916_SLAVE_CAMERA_CFG,
0068 MSM8916_SLAVE_CATS_128,
0069 MSM8916_SLAVE_OCMEM_64,
0070 MSM8916_SLAVE_CLK_CTL,
0071 MSM8916_SLAVE_CRYPTO_0_CFG,
0072 MSM8916_SLAVE_DEHR_CFG,
0073 MSM8916_SLAVE_DISPLAY_CFG,
0074 MSM8916_SLAVE_EBI_CH0,
0075 MSM8916_SLAVE_GRAPHICS_3D_CFG,
0076 MSM8916_SLAVE_IMEM_CFG,
0077 MSM8916_SLAVE_IMEM,
0078 MSM8916_SLAVE_MPM,
0079 MSM8916_SLAVE_MSG_RAM,
0080 MSM8916_SLAVE_MSS,
0081 MSM8916_SLAVE_PDM,
0082 MSM8916_SLAVE_PMIC_ARB,
0083 MSM8916_SLAVE_PNOC_CFG,
0084 MSM8916_SLAVE_PRNG,
0085 MSM8916_SLAVE_QDSS_CFG,
0086 MSM8916_SLAVE_QDSS_STM,
0087 MSM8916_SLAVE_RBCPR_CFG,
0088 MSM8916_SLAVE_SDCC_1,
0089 MSM8916_SLAVE_SDCC_2,
0090 MSM8916_SLAVE_SECURITY,
0091 MSM8916_SLAVE_SNOC_CFG,
0092 MSM8916_SLAVE_SPDM,
0093 MSM8916_SLAVE_SRVC_SNOC,
0094 MSM8916_SLAVE_TCSR,
0095 MSM8916_SLAVE_TLMM,
0096 MSM8916_SLAVE_USB_HS,
0097 MSM8916_SLAVE_VENUS_CFG,
0098 MSM8916_SNOC_BIMC_0_MAS,
0099 MSM8916_SNOC_BIMC_0_SLV,
0100 MSM8916_SNOC_BIMC_1_MAS,
0101 MSM8916_SNOC_BIMC_1_SLV,
0102 MSM8916_SNOC_INT_0,
0103 MSM8916_SNOC_INT_1,
0104 MSM8916_SNOC_INT_BIMC,
0105 MSM8916_SNOC_PNOC_MAS,
0106 MSM8916_SNOC_PNOC_SLV,
0107 };
0108
0109 static const u16 bimc_snoc_mas_links[] = {
0110 MSM8916_BIMC_SNOC_SLV
0111 };
0112
0113 static struct qcom_icc_node bimc_snoc_mas = {
0114 .name = "bimc_snoc_mas",
0115 .id = MSM8916_BIMC_SNOC_MAS,
0116 .buswidth = 8,
0117 .mas_rpm_id = -1,
0118 .slv_rpm_id = -1,
0119 .qos.ap_owned = true,
0120 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0121 .num_links = ARRAY_SIZE(bimc_snoc_mas_links),
0122 .links = bimc_snoc_mas_links,
0123 };
0124
0125 static const u16 bimc_snoc_slv_links[] = {
0126 MSM8916_SNOC_INT_0,
0127 MSM8916_SNOC_INT_1
0128 };
0129
0130 static struct qcom_icc_node bimc_snoc_slv = {
0131 .name = "bimc_snoc_slv",
0132 .id = MSM8916_BIMC_SNOC_SLV,
0133 .buswidth = 8,
0134 .mas_rpm_id = -1,
0135 .slv_rpm_id = -1,
0136 .qos.ap_owned = true,
0137 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0138 .num_links = ARRAY_SIZE(bimc_snoc_slv_links),
0139 .links = bimc_snoc_slv_links,
0140 };
0141
0142 static const u16 mas_apss_links[] = {
0143 MSM8916_SLAVE_EBI_CH0,
0144 MSM8916_BIMC_SNOC_MAS,
0145 MSM8916_SLAVE_AMPSS_L2
0146 };
0147
0148 static struct qcom_icc_node mas_apss = {
0149 .name = "mas_apss",
0150 .id = MSM8916_MASTER_AMPSS_M0,
0151 .buswidth = 8,
0152 .mas_rpm_id = -1,
0153 .slv_rpm_id = -1,
0154 .qos.ap_owned = true,
0155 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0156 .qos.areq_prio = 0,
0157 .qos.prio_level = 0,
0158 .qos.qos_port = 0,
0159 .num_links = ARRAY_SIZE(mas_apss_links),
0160 .links = mas_apss_links,
0161 };
0162
0163 static const u16 mas_audio_links[] = {
0164 MSM8916_PNOC_MAS_0
0165 };
0166
0167 static struct qcom_icc_node mas_audio = {
0168 .name = "mas_audio",
0169 .id = MSM8916_MASTER_LPASS,
0170 .buswidth = 4,
0171 .mas_rpm_id = -1,
0172 .slv_rpm_id = -1,
0173 .num_links = ARRAY_SIZE(mas_audio_links),
0174 .links = mas_audio_links,
0175 };
0176
0177 static const u16 mas_blsp_1_links[] = {
0178 MSM8916_PNOC_MAS_1
0179 };
0180
0181 static struct qcom_icc_node mas_blsp_1 = {
0182 .name = "mas_blsp_1",
0183 .id = MSM8916_MASTER_BLSP_1,
0184 .buswidth = 4,
0185 .mas_rpm_id = -1,
0186 .slv_rpm_id = -1,
0187 .num_links = ARRAY_SIZE(mas_blsp_1_links),
0188 .links = mas_blsp_1_links,
0189 };
0190
0191 static const u16 mas_dehr_links[] = {
0192 MSM8916_PNOC_MAS_0
0193 };
0194
0195 static struct qcom_icc_node mas_dehr = {
0196 .name = "mas_dehr",
0197 .id = MSM8916_MASTER_DEHR,
0198 .buswidth = 4,
0199 .mas_rpm_id = -1,
0200 .slv_rpm_id = -1,
0201 .num_links = ARRAY_SIZE(mas_dehr_links),
0202 .links = mas_dehr_links,
0203 };
0204
0205 static const u16 mas_gfx_links[] = {
0206 MSM8916_SLAVE_EBI_CH0,
0207 MSM8916_BIMC_SNOC_MAS,
0208 MSM8916_SLAVE_AMPSS_L2
0209 };
0210
0211 static struct qcom_icc_node mas_gfx = {
0212 .name = "mas_gfx",
0213 .id = MSM8916_MASTER_GRAPHICS_3D,
0214 .buswidth = 8,
0215 .mas_rpm_id = -1,
0216 .slv_rpm_id = -1,
0217 .qos.ap_owned = true,
0218 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0219 .qos.areq_prio = 0,
0220 .qos.prio_level = 0,
0221 .qos.qos_port = 2,
0222 .num_links = ARRAY_SIZE(mas_gfx_links),
0223 .links = mas_gfx_links,
0224 };
0225
0226 static const u16 mas_jpeg_links[] = {
0227 MSM8916_SNOC_MM_INT_0,
0228 MSM8916_SNOC_MM_INT_2
0229 };
0230
0231 static struct qcom_icc_node mas_jpeg = {
0232 .name = "mas_jpeg",
0233 .id = MSM8916_MASTER_JPEG,
0234 .buswidth = 16,
0235 .mas_rpm_id = -1,
0236 .slv_rpm_id = -1,
0237 .qos.ap_owned = true,
0238 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0239 .qos.areq_prio = 0,
0240 .qos.prio_level = 0,
0241 .qos.qos_port = 6,
0242 .num_links = ARRAY_SIZE(mas_jpeg_links),
0243 .links = mas_jpeg_links,
0244 };
0245
0246 static const u16 mas_mdp_links[] = {
0247 MSM8916_SNOC_MM_INT_0,
0248 MSM8916_SNOC_MM_INT_2
0249 };
0250
0251 static struct qcom_icc_node mas_mdp = {
0252 .name = "mas_mdp",
0253 .id = MSM8916_MASTER_MDP_PORT0,
0254 .buswidth = 16,
0255 .mas_rpm_id = -1,
0256 .slv_rpm_id = -1,
0257 .qos.ap_owned = true,
0258 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0259 .qos.areq_prio = 0,
0260 .qos.prio_level = 0,
0261 .qos.qos_port = 7,
0262 .num_links = ARRAY_SIZE(mas_mdp_links),
0263 .links = mas_mdp_links,
0264 };
0265
0266 static const u16 mas_pcnoc_crypto_0_links[] = {
0267 MSM8916_PNOC_INT_1
0268 };
0269
0270 static struct qcom_icc_node mas_pcnoc_crypto_0 = {
0271 .name = "mas_pcnoc_crypto_0",
0272 .id = MSM8916_MASTER_CRYPTO_CORE0,
0273 .buswidth = 8,
0274 .mas_rpm_id = -1,
0275 .slv_rpm_id = -1,
0276 .num_links = ARRAY_SIZE(mas_pcnoc_crypto_0_links),
0277 .links = mas_pcnoc_crypto_0_links,
0278 };
0279
0280 static const u16 mas_pcnoc_sdcc_1_links[] = {
0281 MSM8916_PNOC_INT_1
0282 };
0283
0284 static struct qcom_icc_node mas_pcnoc_sdcc_1 = {
0285 .name = "mas_pcnoc_sdcc_1",
0286 .id = MSM8916_MASTER_SDCC_1,
0287 .buswidth = 8,
0288 .mas_rpm_id = -1,
0289 .slv_rpm_id = -1,
0290 .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_1_links),
0291 .links = mas_pcnoc_sdcc_1_links,
0292 };
0293
0294 static const u16 mas_pcnoc_sdcc_2_links[] = {
0295 MSM8916_PNOC_INT_1
0296 };
0297
0298 static struct qcom_icc_node mas_pcnoc_sdcc_2 = {
0299 .name = "mas_pcnoc_sdcc_2",
0300 .id = MSM8916_MASTER_SDCC_2,
0301 .buswidth = 8,
0302 .mas_rpm_id = -1,
0303 .slv_rpm_id = -1,
0304 .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_2_links),
0305 .links = mas_pcnoc_sdcc_2_links,
0306 };
0307
0308 static const u16 mas_qdss_bam_links[] = {
0309 MSM8916_SNOC_QDSS_INT
0310 };
0311
0312 static struct qcom_icc_node mas_qdss_bam = {
0313 .name = "mas_qdss_bam",
0314 .id = MSM8916_MASTER_QDSS_BAM,
0315 .buswidth = 8,
0316 .mas_rpm_id = -1,
0317 .slv_rpm_id = -1,
0318 .qos.ap_owned = true,
0319 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0320 .qos.areq_prio = 1,
0321 .qos.prio_level = 1,
0322 .qos.qos_port = 11,
0323 .num_links = ARRAY_SIZE(mas_qdss_bam_links),
0324 .links = mas_qdss_bam_links,
0325 };
0326
0327 static const u16 mas_qdss_etr_links[] = {
0328 MSM8916_SNOC_QDSS_INT
0329 };
0330
0331 static struct qcom_icc_node mas_qdss_etr = {
0332 .name = "mas_qdss_etr",
0333 .id = MSM8916_MASTER_QDSS_ETR,
0334 .buswidth = 8,
0335 .mas_rpm_id = -1,
0336 .slv_rpm_id = -1,
0337 .qos.ap_owned = true,
0338 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0339 .qos.areq_prio = 1,
0340 .qos.prio_level = 1,
0341 .qos.qos_port = 10,
0342 .num_links = ARRAY_SIZE(mas_qdss_etr_links),
0343 .links = mas_qdss_etr_links,
0344 };
0345
0346 static const u16 mas_snoc_cfg_links[] = {
0347 MSM8916_SNOC_QDSS_INT
0348 };
0349
0350 static struct qcom_icc_node mas_snoc_cfg = {
0351 .name = "mas_snoc_cfg",
0352 .id = MSM8916_MASTER_SNOC_CFG,
0353 .buswidth = 4,
0354 .mas_rpm_id = -1,
0355 .slv_rpm_id = -1,
0356 .num_links = ARRAY_SIZE(mas_snoc_cfg_links),
0357 .links = mas_snoc_cfg_links,
0358 };
0359
0360 static const u16 mas_spdm_links[] = {
0361 MSM8916_PNOC_MAS_0
0362 };
0363
0364 static struct qcom_icc_node mas_spdm = {
0365 .name = "mas_spdm",
0366 .id = MSM8916_MASTER_SPDM,
0367 .buswidth = 4,
0368 .mas_rpm_id = -1,
0369 .slv_rpm_id = -1,
0370 .num_links = ARRAY_SIZE(mas_spdm_links),
0371 .links = mas_spdm_links,
0372 };
0373
0374 static const u16 mas_tcu0_links[] = {
0375 MSM8916_SLAVE_EBI_CH0,
0376 MSM8916_BIMC_SNOC_MAS,
0377 MSM8916_SLAVE_AMPSS_L2
0378 };
0379
0380 static struct qcom_icc_node mas_tcu0 = {
0381 .name = "mas_tcu0",
0382 .id = MSM8916_MASTER_TCU0,
0383 .buswidth = 8,
0384 .mas_rpm_id = -1,
0385 .slv_rpm_id = -1,
0386 .qos.ap_owned = true,
0387 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0388 .qos.areq_prio = 2,
0389 .qos.prio_level = 2,
0390 .qos.qos_port = 5,
0391 .num_links = ARRAY_SIZE(mas_tcu0_links),
0392 .links = mas_tcu0_links,
0393 };
0394
0395 static const u16 mas_tcu1_links[] = {
0396 MSM8916_SLAVE_EBI_CH0,
0397 MSM8916_BIMC_SNOC_MAS,
0398 MSM8916_SLAVE_AMPSS_L2
0399 };
0400
0401 static struct qcom_icc_node mas_tcu1 = {
0402 .name = "mas_tcu1",
0403 .id = MSM8916_MASTER_TCU1,
0404 .buswidth = 8,
0405 .mas_rpm_id = -1,
0406 .slv_rpm_id = -1,
0407 .qos.ap_owned = true,
0408 .qos.qos_mode = NOC_QOS_MODE_FIXED,
0409 .qos.areq_prio = 2,
0410 .qos.prio_level = 2,
0411 .qos.qos_port = 6,
0412 .num_links = ARRAY_SIZE(mas_tcu1_links),
0413 .links = mas_tcu1_links,
0414 };
0415
0416 static const u16 mas_usb_hs_links[] = {
0417 MSM8916_PNOC_MAS_1
0418 };
0419
0420 static struct qcom_icc_node mas_usb_hs = {
0421 .name = "mas_usb_hs",
0422 .id = MSM8916_MASTER_USB_HS,
0423 .buswidth = 4,
0424 .mas_rpm_id = -1,
0425 .slv_rpm_id = -1,
0426 .num_links = ARRAY_SIZE(mas_usb_hs_links),
0427 .links = mas_usb_hs_links,
0428 };
0429
0430 static const u16 mas_vfe_links[] = {
0431 MSM8916_SNOC_MM_INT_1,
0432 MSM8916_SNOC_MM_INT_2
0433 };
0434
0435 static struct qcom_icc_node mas_vfe = {
0436 .name = "mas_vfe",
0437 .id = MSM8916_MASTER_VFE,
0438 .buswidth = 16,
0439 .mas_rpm_id = -1,
0440 .slv_rpm_id = -1,
0441 .qos.ap_owned = true,
0442 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0443 .qos.areq_prio = 0,
0444 .qos.prio_level = 0,
0445 .qos.qos_port = 9,
0446 .num_links = ARRAY_SIZE(mas_vfe_links),
0447 .links = mas_vfe_links,
0448 };
0449
0450 static const u16 mas_video_links[] = {
0451 MSM8916_SNOC_MM_INT_0,
0452 MSM8916_SNOC_MM_INT_2
0453 };
0454
0455 static struct qcom_icc_node mas_video = {
0456 .name = "mas_video",
0457 .id = MSM8916_MASTER_VIDEO_P0,
0458 .buswidth = 16,
0459 .mas_rpm_id = -1,
0460 .slv_rpm_id = -1,
0461 .qos.ap_owned = true,
0462 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
0463 .qos.areq_prio = 0,
0464 .qos.prio_level = 0,
0465 .qos.qos_port = 8,
0466 .num_links = ARRAY_SIZE(mas_video_links),
0467 .links = mas_video_links,
0468 };
0469
0470 static const u16 mm_int_0_links[] = {
0471 MSM8916_SNOC_MM_INT_BIMC
0472 };
0473
0474 static struct qcom_icc_node mm_int_0 = {
0475 .name = "mm_int_0",
0476 .id = MSM8916_SNOC_MM_INT_0,
0477 .buswidth = 16,
0478 .mas_rpm_id = -1,
0479 .slv_rpm_id = -1,
0480 .qos.ap_owned = true,
0481 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0482 .num_links = ARRAY_SIZE(mm_int_0_links),
0483 .links = mm_int_0_links,
0484 };
0485
0486 static const u16 mm_int_1_links[] = {
0487 MSM8916_SNOC_MM_INT_BIMC
0488 };
0489
0490 static struct qcom_icc_node mm_int_1 = {
0491 .name = "mm_int_1",
0492 .id = MSM8916_SNOC_MM_INT_1,
0493 .buswidth = 16,
0494 .mas_rpm_id = -1,
0495 .slv_rpm_id = -1,
0496 .qos.ap_owned = true,
0497 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0498 .num_links = ARRAY_SIZE(mm_int_1_links),
0499 .links = mm_int_1_links,
0500 };
0501
0502 static const u16 mm_int_2_links[] = {
0503 MSM8916_SNOC_INT_0
0504 };
0505
0506 static struct qcom_icc_node mm_int_2 = {
0507 .name = "mm_int_2",
0508 .id = MSM8916_SNOC_MM_INT_2,
0509 .buswidth = 16,
0510 .mas_rpm_id = -1,
0511 .slv_rpm_id = -1,
0512 .qos.ap_owned = true,
0513 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0514 .num_links = ARRAY_SIZE(mm_int_2_links),
0515 .links = mm_int_2_links,
0516 };
0517
0518 static const u16 mm_int_bimc_links[] = {
0519 MSM8916_SNOC_BIMC_1_MAS
0520 };
0521
0522 static struct qcom_icc_node mm_int_bimc = {
0523 .name = "mm_int_bimc",
0524 .id = MSM8916_SNOC_MM_INT_BIMC,
0525 .buswidth = 16,
0526 .mas_rpm_id = -1,
0527 .slv_rpm_id = -1,
0528 .qos.ap_owned = true,
0529 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0530 .num_links = ARRAY_SIZE(mm_int_bimc_links),
0531 .links = mm_int_bimc_links,
0532 };
0533
0534 static const u16 pcnoc_int_0_links[] = {
0535 MSM8916_PNOC_SNOC_MAS,
0536 MSM8916_PNOC_SLV_0,
0537 MSM8916_PNOC_SLV_1,
0538 MSM8916_PNOC_SLV_2,
0539 MSM8916_PNOC_SLV_3,
0540 MSM8916_PNOC_SLV_4,
0541 MSM8916_PNOC_SLV_8,
0542 MSM8916_PNOC_SLV_9
0543 };
0544
0545 static struct qcom_icc_node pcnoc_int_0 = {
0546 .name = "pcnoc_int_0",
0547 .id = MSM8916_PNOC_INT_0,
0548 .buswidth = 8,
0549 .mas_rpm_id = -1,
0550 .slv_rpm_id = -1,
0551 .num_links = ARRAY_SIZE(pcnoc_int_0_links),
0552 .links = pcnoc_int_0_links,
0553 };
0554
0555 static const u16 pcnoc_int_1_links[] = {
0556 MSM8916_PNOC_SNOC_MAS
0557 };
0558
0559 static struct qcom_icc_node pcnoc_int_1 = {
0560 .name = "pcnoc_int_1",
0561 .id = MSM8916_PNOC_INT_1,
0562 .buswidth = 8,
0563 .mas_rpm_id = -1,
0564 .slv_rpm_id = -1,
0565 .num_links = ARRAY_SIZE(pcnoc_int_1_links),
0566 .links = pcnoc_int_1_links,
0567 };
0568
0569 static const u16 pcnoc_m_0_links[] = {
0570 MSM8916_PNOC_INT_0
0571 };
0572
0573 static struct qcom_icc_node pcnoc_m_0 = {
0574 .name = "pcnoc_m_0",
0575 .id = MSM8916_PNOC_MAS_0,
0576 .buswidth = 8,
0577 .mas_rpm_id = -1,
0578 .slv_rpm_id = -1,
0579 .num_links = ARRAY_SIZE(pcnoc_m_0_links),
0580 .links = pcnoc_m_0_links,
0581 };
0582
0583 static const u16 pcnoc_m_1_links[] = {
0584 MSM8916_PNOC_SNOC_MAS
0585 };
0586
0587 static struct qcom_icc_node pcnoc_m_1 = {
0588 .name = "pcnoc_m_1",
0589 .id = MSM8916_PNOC_MAS_1,
0590 .buswidth = 8,
0591 .mas_rpm_id = -1,
0592 .slv_rpm_id = -1,
0593 .num_links = ARRAY_SIZE(pcnoc_m_1_links),
0594 .links = pcnoc_m_1_links,
0595 };
0596
0597 static const u16 pcnoc_s_0_links[] = {
0598 MSM8916_SLAVE_CLK_CTL,
0599 MSM8916_SLAVE_TLMM,
0600 MSM8916_SLAVE_TCSR,
0601 MSM8916_SLAVE_SECURITY,
0602 MSM8916_SLAVE_MSS
0603 };
0604
0605 static struct qcom_icc_node pcnoc_s_0 = {
0606 .name = "pcnoc_s_0",
0607 .id = MSM8916_PNOC_SLV_0,
0608 .buswidth = 4,
0609 .mas_rpm_id = -1,
0610 .slv_rpm_id = -1,
0611 .num_links = ARRAY_SIZE(pcnoc_s_0_links),
0612 .links = pcnoc_s_0_links,
0613 };
0614
0615 static const u16 pcnoc_s_1_links[] = {
0616 MSM8916_SLAVE_IMEM_CFG,
0617 MSM8916_SLAVE_CRYPTO_0_CFG,
0618 MSM8916_SLAVE_MSG_RAM,
0619 MSM8916_SLAVE_PDM,
0620 MSM8916_SLAVE_PRNG
0621 };
0622
0623 static struct qcom_icc_node pcnoc_s_1 = {
0624 .name = "pcnoc_s_1",
0625 .id = MSM8916_PNOC_SLV_1,
0626 .buswidth = 4,
0627 .mas_rpm_id = -1,
0628 .slv_rpm_id = -1,
0629 .num_links = ARRAY_SIZE(pcnoc_s_1_links),
0630 .links = pcnoc_s_1_links,
0631 };
0632
0633 static const u16 pcnoc_s_2_links[] = {
0634 MSM8916_SLAVE_SPDM,
0635 MSM8916_SLAVE_BOOT_ROM,
0636 MSM8916_SLAVE_BIMC_CFG,
0637 MSM8916_SLAVE_PNOC_CFG,
0638 MSM8916_SLAVE_PMIC_ARB
0639 };
0640
0641 static struct qcom_icc_node pcnoc_s_2 = {
0642 .name = "pcnoc_s_2",
0643 .id = MSM8916_PNOC_SLV_2,
0644 .buswidth = 4,
0645 .mas_rpm_id = -1,
0646 .slv_rpm_id = -1,
0647 .num_links = ARRAY_SIZE(pcnoc_s_2_links),
0648 .links = pcnoc_s_2_links,
0649 };
0650
0651 static const u16 pcnoc_s_3_links[] = {
0652 MSM8916_SLAVE_MPM,
0653 MSM8916_SLAVE_SNOC_CFG,
0654 MSM8916_SLAVE_RBCPR_CFG,
0655 MSM8916_SLAVE_QDSS_CFG,
0656 MSM8916_SLAVE_DEHR_CFG
0657 };
0658
0659 static struct qcom_icc_node pcnoc_s_3 = {
0660 .name = "pcnoc_s_3",
0661 .id = MSM8916_PNOC_SLV_3,
0662 .buswidth = 4,
0663 .mas_rpm_id = -1,
0664 .slv_rpm_id = -1,
0665 .num_links = ARRAY_SIZE(pcnoc_s_3_links),
0666 .links = pcnoc_s_3_links,
0667 };
0668
0669 static const u16 pcnoc_s_4_links[] = {
0670 MSM8916_SLAVE_VENUS_CFG,
0671 MSM8916_SLAVE_CAMERA_CFG,
0672 MSM8916_SLAVE_DISPLAY_CFG
0673 };
0674
0675 static struct qcom_icc_node pcnoc_s_4 = {
0676 .name = "pcnoc_s_4",
0677 .id = MSM8916_PNOC_SLV_4,
0678 .buswidth = 4,
0679 .mas_rpm_id = -1,
0680 .slv_rpm_id = -1,
0681 .num_links = ARRAY_SIZE(pcnoc_s_4_links),
0682 .links = pcnoc_s_4_links,
0683 };
0684
0685 static const u16 pcnoc_s_8_links[] = {
0686 MSM8916_SLAVE_USB_HS,
0687 MSM8916_SLAVE_SDCC_1,
0688 MSM8916_SLAVE_BLSP_1
0689 };
0690
0691 static struct qcom_icc_node pcnoc_s_8 = {
0692 .name = "pcnoc_s_8",
0693 .id = MSM8916_PNOC_SLV_8,
0694 .buswidth = 4,
0695 .mas_rpm_id = -1,
0696 .slv_rpm_id = -1,
0697 .num_links = ARRAY_SIZE(pcnoc_s_8_links),
0698 .links = pcnoc_s_8_links,
0699 };
0700
0701 static const u16 pcnoc_s_9_links[] = {
0702 MSM8916_SLAVE_SDCC_2,
0703 MSM8916_SLAVE_LPASS,
0704 MSM8916_SLAVE_GRAPHICS_3D_CFG
0705 };
0706
0707 static struct qcom_icc_node pcnoc_s_9 = {
0708 .name = "pcnoc_s_9",
0709 .id = MSM8916_PNOC_SLV_9,
0710 .buswidth = 4,
0711 .mas_rpm_id = -1,
0712 .slv_rpm_id = -1,
0713 .num_links = ARRAY_SIZE(pcnoc_s_9_links),
0714 .links = pcnoc_s_9_links,
0715 };
0716
0717 static const u16 pcnoc_snoc_mas_links[] = {
0718 MSM8916_PNOC_SNOC_SLV
0719 };
0720
0721 static struct qcom_icc_node pcnoc_snoc_mas = {
0722 .name = "pcnoc_snoc_mas",
0723 .id = MSM8916_PNOC_SNOC_MAS,
0724 .buswidth = 8,
0725 .mas_rpm_id = 29,
0726 .slv_rpm_id = -1,
0727 .num_links = ARRAY_SIZE(pcnoc_snoc_mas_links),
0728 .links = pcnoc_snoc_mas_links,
0729 };
0730
0731 static const u16 pcnoc_snoc_slv_links[] = {
0732 MSM8916_SNOC_INT_0,
0733 MSM8916_SNOC_INT_BIMC,
0734 MSM8916_SNOC_INT_1
0735 };
0736
0737 static struct qcom_icc_node pcnoc_snoc_slv = {
0738 .name = "pcnoc_snoc_slv",
0739 .id = MSM8916_PNOC_SNOC_SLV,
0740 .buswidth = 8,
0741 .mas_rpm_id = -1,
0742 .slv_rpm_id = 45,
0743 .num_links = ARRAY_SIZE(pcnoc_snoc_slv_links),
0744 .links = pcnoc_snoc_slv_links,
0745 };
0746
0747 static const u16 qdss_int_links[] = {
0748 MSM8916_SNOC_INT_0,
0749 MSM8916_SNOC_INT_BIMC
0750 };
0751
0752 static struct qcom_icc_node qdss_int = {
0753 .name = "qdss_int",
0754 .id = MSM8916_SNOC_QDSS_INT,
0755 .buswidth = 8,
0756 .mas_rpm_id = -1,
0757 .slv_rpm_id = -1,
0758 .qos.ap_owned = true,
0759 .qos.qos_mode = NOC_QOS_MODE_INVALID,
0760 .num_links = ARRAY_SIZE(qdss_int_links),
0761 .links = qdss_int_links,
0762 };
0763
0764 static struct qcom_icc_node slv_apps_l2 = {
0765 .name = "slv_apps_l2",
0766 .id = MSM8916_SLAVE_AMPSS_L2,
0767 .buswidth = 8,
0768 .mas_rpm_id = -1,
0769 .slv_rpm_id = -1,
0770 };
0771
0772 static struct qcom_icc_node slv_apss = {
0773 .name = "slv_apss",
0774 .id = MSM8916_SLAVE_APSS,
0775 .buswidth = 4,
0776 .mas_rpm_id = -1,
0777 .slv_rpm_id = -1,
0778 };
0779
0780 static struct qcom_icc_node slv_audio = {
0781 .name = "slv_audio",
0782 .id = MSM8916_SLAVE_LPASS,
0783 .buswidth = 4,
0784 .mas_rpm_id = -1,
0785 .slv_rpm_id = -1,
0786 };
0787
0788 static struct qcom_icc_node slv_bimc_cfg = {
0789 .name = "slv_bimc_cfg",
0790 .id = MSM8916_SLAVE_BIMC_CFG,
0791 .buswidth = 4,
0792 .mas_rpm_id = -1,
0793 .slv_rpm_id = -1,
0794 };
0795
0796 static struct qcom_icc_node slv_blsp_1 = {
0797 .name = "slv_blsp_1",
0798 .id = MSM8916_SLAVE_BLSP_1,
0799 .buswidth = 4,
0800 .mas_rpm_id = -1,
0801 .slv_rpm_id = -1,
0802 };
0803
0804 static struct qcom_icc_node slv_boot_rom = {
0805 .name = "slv_boot_rom",
0806 .id = MSM8916_SLAVE_BOOT_ROM,
0807 .buswidth = 4,
0808 .mas_rpm_id = -1,
0809 .slv_rpm_id = -1,
0810 };
0811
0812 static struct qcom_icc_node slv_camera_cfg = {
0813 .name = "slv_camera_cfg",
0814 .id = MSM8916_SLAVE_CAMERA_CFG,
0815 .buswidth = 4,
0816 .mas_rpm_id = -1,
0817 .slv_rpm_id = -1,
0818 };
0819
0820 static struct qcom_icc_node slv_cats_0 = {
0821 .name = "slv_cats_0",
0822 .id = MSM8916_SLAVE_CATS_128,
0823 .buswidth = 16,
0824 .mas_rpm_id = -1,
0825 .slv_rpm_id = -1,
0826 };
0827
0828 static struct qcom_icc_node slv_cats_1 = {
0829 .name = "slv_cats_1",
0830 .id = MSM8916_SLAVE_OCMEM_64,
0831 .buswidth = 8,
0832 .mas_rpm_id = -1,
0833 .slv_rpm_id = -1,
0834 };
0835
0836 static struct qcom_icc_node slv_clk_ctl = {
0837 .name = "slv_clk_ctl",
0838 .id = MSM8916_SLAVE_CLK_CTL,
0839 .buswidth = 4,
0840 .mas_rpm_id = -1,
0841 .slv_rpm_id = -1,
0842 };
0843
0844 static struct qcom_icc_node slv_crypto_0_cfg = {
0845 .name = "slv_crypto_0_cfg",
0846 .id = MSM8916_SLAVE_CRYPTO_0_CFG,
0847 .buswidth = 4,
0848 .mas_rpm_id = -1,
0849 .slv_rpm_id = -1,
0850 };
0851
0852 static struct qcom_icc_node slv_dehr_cfg = {
0853 .name = "slv_dehr_cfg",
0854 .id = MSM8916_SLAVE_DEHR_CFG,
0855 .buswidth = 4,
0856 .mas_rpm_id = -1,
0857 .slv_rpm_id = -1,
0858 };
0859
0860 static struct qcom_icc_node slv_display_cfg = {
0861 .name = "slv_display_cfg",
0862 .id = MSM8916_SLAVE_DISPLAY_CFG,
0863 .buswidth = 4,
0864 .mas_rpm_id = -1,
0865 .slv_rpm_id = -1,
0866 };
0867
0868 static struct qcom_icc_node slv_ebi_ch0 = {
0869 .name = "slv_ebi_ch0",
0870 .id = MSM8916_SLAVE_EBI_CH0,
0871 .buswidth = 8,
0872 .mas_rpm_id = -1,
0873 .slv_rpm_id = 0,
0874 };
0875
0876 static struct qcom_icc_node slv_gfx_cfg = {
0877 .name = "slv_gfx_cfg",
0878 .id = MSM8916_SLAVE_GRAPHICS_3D_CFG,
0879 .buswidth = 4,
0880 .mas_rpm_id = -1,
0881 .slv_rpm_id = -1,
0882 };
0883
0884 static struct qcom_icc_node slv_imem_cfg = {
0885 .name = "slv_imem_cfg",
0886 .id = MSM8916_SLAVE_IMEM_CFG,
0887 .buswidth = 4,
0888 .mas_rpm_id = -1,
0889 .slv_rpm_id = -1,
0890 };
0891
0892 static struct qcom_icc_node slv_imem = {
0893 .name = "slv_imem",
0894 .id = MSM8916_SLAVE_IMEM,
0895 .buswidth = 8,
0896 .mas_rpm_id = -1,
0897 .slv_rpm_id = 26,
0898 };
0899
0900 static struct qcom_icc_node slv_mpm = {
0901 .name = "slv_mpm",
0902 .id = MSM8916_SLAVE_MPM,
0903 .buswidth = 4,
0904 .mas_rpm_id = -1,
0905 .slv_rpm_id = -1,
0906 };
0907
0908 static struct qcom_icc_node slv_msg_ram = {
0909 .name = "slv_msg_ram",
0910 .id = MSM8916_SLAVE_MSG_RAM,
0911 .buswidth = 4,
0912 .mas_rpm_id = -1,
0913 .slv_rpm_id = -1,
0914 };
0915
0916 static struct qcom_icc_node slv_mss = {
0917 .name = "slv_mss",
0918 .id = MSM8916_SLAVE_MSS,
0919 .buswidth = 4,
0920 .mas_rpm_id = -1,
0921 .slv_rpm_id = -1,
0922 };
0923
0924 static struct qcom_icc_node slv_pdm = {
0925 .name = "slv_pdm",
0926 .id = MSM8916_SLAVE_PDM,
0927 .buswidth = 4,
0928 .mas_rpm_id = -1,
0929 .slv_rpm_id = -1,
0930 };
0931
0932 static struct qcom_icc_node slv_pmic_arb = {
0933 .name = "slv_pmic_arb",
0934 .id = MSM8916_SLAVE_PMIC_ARB,
0935 .buswidth = 4,
0936 .mas_rpm_id = -1,
0937 .slv_rpm_id = -1,
0938 };
0939
0940 static struct qcom_icc_node slv_pcnoc_cfg = {
0941 .name = "slv_pcnoc_cfg",
0942 .id = MSM8916_SLAVE_PNOC_CFG,
0943 .buswidth = 4,
0944 .mas_rpm_id = -1,
0945 .slv_rpm_id = -1,
0946 };
0947
0948 static struct qcom_icc_node slv_prng = {
0949 .name = "slv_prng",
0950 .id = MSM8916_SLAVE_PRNG,
0951 .buswidth = 4,
0952 .mas_rpm_id = -1,
0953 .slv_rpm_id = -1,
0954 };
0955
0956 static struct qcom_icc_node slv_qdss_cfg = {
0957 .name = "slv_qdss_cfg",
0958 .id = MSM8916_SLAVE_QDSS_CFG,
0959 .buswidth = 4,
0960 .mas_rpm_id = -1,
0961 .slv_rpm_id = -1,
0962 };
0963
0964 static struct qcom_icc_node slv_qdss_stm = {
0965 .name = "slv_qdss_stm",
0966 .id = MSM8916_SLAVE_QDSS_STM,
0967 .buswidth = 4,
0968 .mas_rpm_id = -1,
0969 .slv_rpm_id = 30,
0970 };
0971
0972 static struct qcom_icc_node slv_rbcpr_cfg = {
0973 .name = "slv_rbcpr_cfg",
0974 .id = MSM8916_SLAVE_RBCPR_CFG,
0975 .buswidth = 4,
0976 .mas_rpm_id = -1,
0977 .slv_rpm_id = -1,
0978 };
0979
0980 static struct qcom_icc_node slv_sdcc_1 = {
0981 .name = "slv_sdcc_1",
0982 .id = MSM8916_SLAVE_SDCC_1,
0983 .buswidth = 4,
0984 .mas_rpm_id = -1,
0985 .slv_rpm_id = -1,
0986 };
0987
0988 static struct qcom_icc_node slv_sdcc_2 = {
0989 .name = "slv_sdcc_2",
0990 .id = MSM8916_SLAVE_SDCC_2,
0991 .buswidth = 4,
0992 .mas_rpm_id = -1,
0993 .slv_rpm_id = -1,
0994 };
0995
0996 static struct qcom_icc_node slv_security = {
0997 .name = "slv_security",
0998 .id = MSM8916_SLAVE_SECURITY,
0999 .buswidth = 4,
1000 .mas_rpm_id = -1,
1001 .slv_rpm_id = -1,
1002 };
1003
1004 static struct qcom_icc_node slv_snoc_cfg = {
1005 .name = "slv_snoc_cfg",
1006 .id = MSM8916_SLAVE_SNOC_CFG,
1007 .buswidth = 4,
1008 .mas_rpm_id = -1,
1009 .slv_rpm_id = -1,
1010 };
1011
1012 static struct qcom_icc_node slv_spdm = {
1013 .name = "slv_spdm",
1014 .id = MSM8916_SLAVE_SPDM,
1015 .buswidth = 4,
1016 .mas_rpm_id = -1,
1017 .slv_rpm_id = -1,
1018 };
1019
1020 static struct qcom_icc_node slv_srvc_snoc = {
1021 .name = "slv_srvc_snoc",
1022 .id = MSM8916_SLAVE_SRVC_SNOC,
1023 .buswidth = 8,
1024 .mas_rpm_id = -1,
1025 .slv_rpm_id = -1,
1026 };
1027
1028 static struct qcom_icc_node slv_tcsr = {
1029 .name = "slv_tcsr",
1030 .id = MSM8916_SLAVE_TCSR,
1031 .buswidth = 4,
1032 .mas_rpm_id = -1,
1033 .slv_rpm_id = -1,
1034 };
1035
1036 static struct qcom_icc_node slv_tlmm = {
1037 .name = "slv_tlmm",
1038 .id = MSM8916_SLAVE_TLMM,
1039 .buswidth = 4,
1040 .mas_rpm_id = -1,
1041 .slv_rpm_id = -1,
1042 };
1043
1044 static struct qcom_icc_node slv_usb_hs = {
1045 .name = "slv_usb_hs",
1046 .id = MSM8916_SLAVE_USB_HS,
1047 .buswidth = 4,
1048 .mas_rpm_id = -1,
1049 .slv_rpm_id = -1,
1050 };
1051
1052 static struct qcom_icc_node slv_venus_cfg = {
1053 .name = "slv_venus_cfg",
1054 .id = MSM8916_SLAVE_VENUS_CFG,
1055 .buswidth = 4,
1056 .mas_rpm_id = -1,
1057 .slv_rpm_id = -1,
1058 };
1059
1060 static const u16 snoc_bimc_0_mas_links[] = {
1061 MSM8916_SNOC_BIMC_0_SLV
1062 };
1063
1064 static struct qcom_icc_node snoc_bimc_0_mas = {
1065 .name = "snoc_bimc_0_mas",
1066 .id = MSM8916_SNOC_BIMC_0_MAS,
1067 .buswidth = 8,
1068 .mas_rpm_id = 3,
1069 .slv_rpm_id = -1,
1070 .num_links = ARRAY_SIZE(snoc_bimc_0_mas_links),
1071 .links = snoc_bimc_0_mas_links,
1072 };
1073
1074 static const u16 snoc_bimc_0_slv_links[] = {
1075 MSM8916_SLAVE_EBI_CH0
1076 };
1077
1078 static struct qcom_icc_node snoc_bimc_0_slv = {
1079 .name = "snoc_bimc_0_slv",
1080 .id = MSM8916_SNOC_BIMC_0_SLV,
1081 .buswidth = 8,
1082 .mas_rpm_id = -1,
1083 .slv_rpm_id = 24,
1084 .num_links = ARRAY_SIZE(snoc_bimc_0_slv_links),
1085 .links = snoc_bimc_0_slv_links,
1086 };
1087
1088 static const u16 snoc_bimc_1_mas_links[] = {
1089 MSM8916_SNOC_BIMC_1_SLV
1090 };
1091
1092 static struct qcom_icc_node snoc_bimc_1_mas = {
1093 .name = "snoc_bimc_1_mas",
1094 .id = MSM8916_SNOC_BIMC_1_MAS,
1095 .buswidth = 16,
1096 .mas_rpm_id = -1,
1097 .slv_rpm_id = -1,
1098 .qos.ap_owned = true,
1099 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1100 .num_links = ARRAY_SIZE(snoc_bimc_1_mas_links),
1101 .links = snoc_bimc_1_mas_links,
1102 };
1103
1104 static const u16 snoc_bimc_1_slv_links[] = {
1105 MSM8916_SLAVE_EBI_CH0
1106 };
1107
1108 static struct qcom_icc_node snoc_bimc_1_slv = {
1109 .name = "snoc_bimc_1_slv",
1110 .id = MSM8916_SNOC_BIMC_1_SLV,
1111 .buswidth = 8,
1112 .mas_rpm_id = -1,
1113 .slv_rpm_id = -1,
1114 .qos.ap_owned = true,
1115 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1116 .num_links = ARRAY_SIZE(snoc_bimc_1_slv_links),
1117 .links = snoc_bimc_1_slv_links,
1118 };
1119
1120 static const u16 snoc_int_0_links[] = {
1121 MSM8916_SLAVE_QDSS_STM,
1122 MSM8916_SLAVE_IMEM,
1123 MSM8916_SNOC_PNOC_MAS
1124 };
1125
1126 static struct qcom_icc_node snoc_int_0 = {
1127 .name = "snoc_int_0",
1128 .id = MSM8916_SNOC_INT_0,
1129 .buswidth = 8,
1130 .mas_rpm_id = 99,
1131 .slv_rpm_id = 130,
1132 .num_links = ARRAY_SIZE(snoc_int_0_links),
1133 .links = snoc_int_0_links,
1134 };
1135
1136 static const u16 snoc_int_1_links[] = {
1137 MSM8916_SLAVE_APSS,
1138 MSM8916_SLAVE_CATS_128,
1139 MSM8916_SLAVE_OCMEM_64
1140 };
1141
1142 static struct qcom_icc_node snoc_int_1 = {
1143 .name = "snoc_int_1",
1144 .id = MSM8916_SNOC_INT_1,
1145 .buswidth = 8,
1146 .mas_rpm_id = -1,
1147 .slv_rpm_id = -1,
1148 .num_links = ARRAY_SIZE(snoc_int_1_links),
1149 .links = snoc_int_1_links,
1150 };
1151
1152 static const u16 snoc_int_bimc_links[] = {
1153 MSM8916_SNOC_BIMC_0_MAS
1154 };
1155
1156 static struct qcom_icc_node snoc_int_bimc = {
1157 .name = "snoc_int_bimc",
1158 .id = MSM8916_SNOC_INT_BIMC,
1159 .buswidth = 8,
1160 .mas_rpm_id = 101,
1161 .slv_rpm_id = 132,
1162 .num_links = ARRAY_SIZE(snoc_int_bimc_links),
1163 .links = snoc_int_bimc_links,
1164 };
1165
1166 static const u16 snoc_pcnoc_mas_links[] = {
1167 MSM8916_SNOC_PNOC_SLV
1168 };
1169
1170 static struct qcom_icc_node snoc_pcnoc_mas = {
1171 .name = "snoc_pcnoc_mas",
1172 .id = MSM8916_SNOC_PNOC_MAS,
1173 .buswidth = 8,
1174 .mas_rpm_id = -1,
1175 .slv_rpm_id = -1,
1176 .num_links = ARRAY_SIZE(snoc_pcnoc_mas_links),
1177 .links = snoc_pcnoc_mas_links,
1178 };
1179
1180 static const u16 snoc_pcnoc_slv_links[] = {
1181 MSM8916_PNOC_INT_0
1182 };
1183
1184 static struct qcom_icc_node snoc_pcnoc_slv = {
1185 .name = "snoc_pcnoc_slv",
1186 .id = MSM8916_SNOC_PNOC_SLV,
1187 .buswidth = 8,
1188 .mas_rpm_id = -1,
1189 .slv_rpm_id = -1,
1190 .num_links = ARRAY_SIZE(snoc_pcnoc_slv_links),
1191 .links = snoc_pcnoc_slv_links,
1192 };
1193
1194 static struct qcom_icc_node * const msm8916_snoc_nodes[] = {
1195 [BIMC_SNOC_SLV] = &bimc_snoc_slv,
1196 [MASTER_JPEG] = &mas_jpeg,
1197 [MASTER_MDP_PORT0] = &mas_mdp,
1198 [MASTER_QDSS_BAM] = &mas_qdss_bam,
1199 [MASTER_QDSS_ETR] = &mas_qdss_etr,
1200 [MASTER_SNOC_CFG] = &mas_snoc_cfg,
1201 [MASTER_VFE] = &mas_vfe,
1202 [MASTER_VIDEO_P0] = &mas_video,
1203 [SNOC_MM_INT_0] = &mm_int_0,
1204 [SNOC_MM_INT_1] = &mm_int_1,
1205 [SNOC_MM_INT_2] = &mm_int_2,
1206 [SNOC_MM_INT_BIMC] = &mm_int_bimc,
1207 [PCNOC_SNOC_SLV] = &pcnoc_snoc_slv,
1208 [SLAVE_APSS] = &slv_apss,
1209 [SLAVE_CATS_128] = &slv_cats_0,
1210 [SLAVE_OCMEM_64] = &slv_cats_1,
1211 [SLAVE_IMEM] = &slv_imem,
1212 [SLAVE_QDSS_STM] = &slv_qdss_stm,
1213 [SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
1214 [SNOC_BIMC_0_MAS] = &snoc_bimc_0_mas,
1215 [SNOC_BIMC_1_MAS] = &snoc_bimc_1_mas,
1216 [SNOC_INT_0] = &snoc_int_0,
1217 [SNOC_INT_1] = &snoc_int_1,
1218 [SNOC_INT_BIMC] = &snoc_int_bimc,
1219 [SNOC_PCNOC_MAS] = &snoc_pcnoc_mas,
1220 [SNOC_QDSS_INT] = &qdss_int,
1221 };
1222
1223 static const struct regmap_config msm8916_snoc_regmap_config = {
1224 .reg_bits = 32,
1225 .reg_stride = 4,
1226 .val_bits = 32,
1227 .max_register = 0x14000,
1228 .fast_io = true,
1229 };
1230
1231 static const struct qcom_icc_desc msm8916_snoc = {
1232 .type = QCOM_ICC_NOC,
1233 .nodes = msm8916_snoc_nodes,
1234 .num_nodes = ARRAY_SIZE(msm8916_snoc_nodes),
1235 .regmap_cfg = &msm8916_snoc_regmap_config,
1236 .qos_offset = 0x7000,
1237 };
1238
1239 static struct qcom_icc_node * const msm8916_bimc_nodes[] = {
1240 [BIMC_SNOC_MAS] = &bimc_snoc_mas,
1241 [MASTER_AMPSS_M0] = &mas_apss,
1242 [MASTER_GRAPHICS_3D] = &mas_gfx,
1243 [MASTER_TCU0] = &mas_tcu0,
1244 [MASTER_TCU1] = &mas_tcu1,
1245 [SLAVE_AMPSS_L2] = &slv_apps_l2,
1246 [SLAVE_EBI_CH0] = &slv_ebi_ch0,
1247 [SNOC_BIMC_0_SLV] = &snoc_bimc_0_slv,
1248 [SNOC_BIMC_1_SLV] = &snoc_bimc_1_slv,
1249 };
1250
1251 static const struct regmap_config msm8916_bimc_regmap_config = {
1252 .reg_bits = 32,
1253 .reg_stride = 4,
1254 .val_bits = 32,
1255 .max_register = 0x62000,
1256 .fast_io = true,
1257 };
1258
1259 static const struct qcom_icc_desc msm8916_bimc = {
1260 .type = QCOM_ICC_BIMC,
1261 .nodes = msm8916_bimc_nodes,
1262 .num_nodes = ARRAY_SIZE(msm8916_bimc_nodes),
1263 .regmap_cfg = &msm8916_bimc_regmap_config,
1264 .qos_offset = 0x8000,
1265 };
1266
1267 static struct qcom_icc_node * const msm8916_pcnoc_nodes[] = {
1268 [MASTER_BLSP_1] = &mas_blsp_1,
1269 [MASTER_DEHR] = &mas_dehr,
1270 [MASTER_LPASS] = &mas_audio,
1271 [MASTER_CRYPTO_CORE0] = &mas_pcnoc_crypto_0,
1272 [MASTER_SDCC_1] = &mas_pcnoc_sdcc_1,
1273 [MASTER_SDCC_2] = &mas_pcnoc_sdcc_2,
1274 [MASTER_SPDM] = &mas_spdm,
1275 [MASTER_USB_HS] = &mas_usb_hs,
1276 [PCNOC_INT_0] = &pcnoc_int_0,
1277 [PCNOC_INT_1] = &pcnoc_int_1,
1278 [PCNOC_MAS_0] = &pcnoc_m_0,
1279 [PCNOC_MAS_1] = &pcnoc_m_1,
1280 [PCNOC_SLV_0] = &pcnoc_s_0,
1281 [PCNOC_SLV_1] = &pcnoc_s_1,
1282 [PCNOC_SLV_2] = &pcnoc_s_2,
1283 [PCNOC_SLV_3] = &pcnoc_s_3,
1284 [PCNOC_SLV_4] = &pcnoc_s_4,
1285 [PCNOC_SLV_8] = &pcnoc_s_8,
1286 [PCNOC_SLV_9] = &pcnoc_s_9,
1287 [PCNOC_SNOC_MAS] = &pcnoc_snoc_mas,
1288 [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1289 [SLAVE_BLSP_1] = &slv_blsp_1,
1290 [SLAVE_BOOT_ROM] = &slv_boot_rom,
1291 [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1292 [SLAVE_CLK_CTL] = &slv_clk_ctl,
1293 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1294 [SLAVE_DEHR_CFG] = &slv_dehr_cfg,
1295 [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1296 [SLAVE_GRAPHICS_3D_CFG] = &slv_gfx_cfg,
1297 [SLAVE_IMEM_CFG] = &slv_imem_cfg,
1298 [SLAVE_LPASS] = &slv_audio,
1299 [SLAVE_MPM] = &slv_mpm,
1300 [SLAVE_MSG_RAM] = &slv_msg_ram,
1301 [SLAVE_MSS] = &slv_mss,
1302 [SLAVE_PDM] = &slv_pdm,
1303 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1304 [SLAVE_PCNOC_CFG] = &slv_pcnoc_cfg,
1305 [SLAVE_PRNG] = &slv_prng,
1306 [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1307 [SLAVE_RBCPR_CFG] = &slv_rbcpr_cfg,
1308 [SLAVE_SDCC_1] = &slv_sdcc_1,
1309 [SLAVE_SDCC_2] = &slv_sdcc_2,
1310 [SLAVE_SECURITY] = &slv_security,
1311 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1312 [SLAVE_SPDM] = &slv_spdm,
1313 [SLAVE_TCSR] = &slv_tcsr,
1314 [SLAVE_TLMM] = &slv_tlmm,
1315 [SLAVE_USB_HS] = &slv_usb_hs,
1316 [SLAVE_VENUS_CFG] = &slv_venus_cfg,
1317 [SNOC_PCNOC_SLV] = &snoc_pcnoc_slv,
1318 };
1319
1320 static const struct regmap_config msm8916_pcnoc_regmap_config = {
1321 .reg_bits = 32,
1322 .reg_stride = 4,
1323 .val_bits = 32,
1324 .max_register = 0x11000,
1325 .fast_io = true,
1326 };
1327
1328 static const struct qcom_icc_desc msm8916_pcnoc = {
1329 .type = QCOM_ICC_NOC,
1330 .nodes = msm8916_pcnoc_nodes,
1331 .num_nodes = ARRAY_SIZE(msm8916_pcnoc_nodes),
1332 .regmap_cfg = &msm8916_pcnoc_regmap_config,
1333 .qos_offset = 0x7000,
1334 };
1335
1336 static const struct of_device_id msm8916_noc_of_match[] = {
1337 { .compatible = "qcom,msm8916-bimc", .data = &msm8916_bimc },
1338 { .compatible = "qcom,msm8916-pcnoc", .data = &msm8916_pcnoc },
1339 { .compatible = "qcom,msm8916-snoc", .data = &msm8916_snoc },
1340 { }
1341 };
1342 MODULE_DEVICE_TABLE(of, msm8916_noc_of_match);
1343
1344 static struct platform_driver msm8916_noc_driver = {
1345 .probe = qnoc_probe,
1346 .remove = qnoc_remove,
1347 .driver = {
1348 .name = "qnoc-msm8916",
1349 .of_match_table = msm8916_noc_of_match,
1350 },
1351 };
1352 module_platform_driver(msm8916_noc_driver);
1353 MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>");
1354 MODULE_DESCRIPTION("Qualcomm MSM8916 NoC driver");
1355 MODULE_LICENSE("GPL v2");
