interconnect/qcom/icc-rpm.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2020 Linaro Ltd
0004  */
0005
0006 #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H
0007 #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H
0008
0009 #include <dt-bindings/interconnect/qcom,icc.h>
0010
0011 #define RPM_BUS_MASTER_REQ  0x73616d62
0012 #define RPM_BUS_SLAVE_REQ   0x766c7362
0013
0014 #define to_qcom_provider(_provider) \
0015     container_of(_provider, struct qcom_icc_provider, provider)
0016
0017 enum qcom_icc_type {
0018     QCOM_ICC_NOC,
0019     QCOM_ICC_BIMC,
0020     QCOM_ICC_QNOC,
0021 };
0022
0023 /**
0024  * struct qcom_icc_provider - Qualcomm specific interconnect provider
0025  * @provider: generic interconnect provider
0026  * @bus_clks: the clk_bulk_data table of bus clocks
0027  * @num_clks: the total number of clk_bulk_data entries
0028  * @type: the ICC provider type
0029  * @qos_offset: offset to QoS registers
0030  * @regmap: regmap for QoS registers read/write access
0031  * @bus_clk_rate: bus clock rate in Hz
0032  */
0033 struct qcom_icc_provider {
0034     struct icc_provider provider;
0035     int num_clks;
0036     enum qcom_icc_type type;
0037     struct regmap *regmap;
0038     unsigned int qos_offset;
0039     u64 *bus_clk_rate;
0040     struct clk_bulk_data bus_clks[];
0041 };
0042
0043 /**
0044  * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters
0045  * @areq_prio: node requests priority
0046  * @prio_level: priority level for bus communication
0047  * @limit_commands: activate/deactivate limiter mode during runtime
0048  * @ap_owned: indicates if the node is owned by the AP or by the RPM
0049  * @qos_mode: default qos mode for this node
0050  * @qos_port: qos port number for finding qos registers of this node
0051  * @urg_fwd_en: enable urgent forwarding
0052  */
0053 struct qcom_icc_qos {
0054     u32 areq_prio;
0055     u32 prio_level;
0056     bool limit_commands;
0057     bool ap_owned;
0058     int qos_mode;
0059     int qos_port;
0060     bool urg_fwd_en;
0061 };
0062
0063 /**
0064  * struct qcom_icc_node - Qualcomm specific interconnect nodes
0065  * @name: the node name used in debugfs
0066  * @id: a unique node identifier
0067  * @links: an array of nodes where we can go next while traversing
0068  * @num_links: the total number of @links
0069  * @buswidth: width of the interconnect between a node and the bus (bytes)
0070  * @sum_avg: current sum aggregate value of all avg bw requests
0071  * @max_peak: current max aggregate value of all peak bw requests
0072  * @mas_rpm_id: RPM id for devices that are bus masters
0073  * @slv_rpm_id: RPM id for devices that are bus slaves
0074  * @qos: NoC QoS setting parameters
0075  */
0076 struct qcom_icc_node {
0077     unsigned char *name;
0078     u16 id;
0079     const u16 *links;
0080     u16 num_links;
0081     u16 buswidth;
0082     u64 sum_avg[QCOM_ICC_NUM_BUCKETS];
0083     u64 max_peak[QCOM_ICC_NUM_BUCKETS];
0084     int mas_rpm_id;
0085     int slv_rpm_id;
0086     struct qcom_icc_qos qos;
0087 };
0088
0089 struct qcom_icc_desc {
0090     struct qcom_icc_node * const *nodes;
0091     size_t num_nodes;
0092     const char * const *clocks;
0093     size_t num_clocks;
0094     bool has_bus_pd;
0095     enum qcom_icc_type type;
0096     const struct regmap_config *regmap_cfg;
0097     unsigned int qos_offset;
0098 };
0099
0100 /* Valid for both NoC and BIMC */
0101 #define NOC_QOS_MODE_INVALID        -1
0102 #define NOC_QOS_MODE_FIXED      0x0
0103 #define NOC_QOS_MODE_BYPASS     0x2
0104
0105 int qnoc_probe(struct platform_device *pdev);
0106 int qnoc_remove(struct platform_device *pdev);
0107
0108 #endif