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0018 #include <linux/module.h>
0019 #include <linux/delay.h>
0020 #include <linux/sched.h>
0021 #include <linux/wait.h>
0022 #include <linux/input.h>
0023 #include <linux/device.h>
0024 #include <linux/interrupt.h>
0025 #include <linux/ucb1400.h>
0026
0027 #define UCB1400_TS_POLL_PERIOD 10
0028
0029 static bool adcsync;
0030 static int ts_delay = 55;
0031 static int ts_delay_pressure;
0032
0033
0034 static void ucb1400_ts_mode_int(struct ucb1400_ts *ucb)
0035 {
0036 ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
0037 UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
0038 UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
0039 UCB_TS_CR_MODE_INT);
0040 }
0041
0042
0043
0044
0045
0046 static unsigned int ucb1400_ts_read_pressure(struct ucb1400_ts *ucb)
0047 {
0048 ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
0049 UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
0050 UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
0051 UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
0052
0053 udelay(ts_delay_pressure);
0054
0055 return ucb1400_adc_read(ucb->ac97, UCB_ADC_INP_TSPY, adcsync);
0056 }
0057
0058
0059
0060
0061
0062
0063
0064 static unsigned int ucb1400_ts_read_xpos(struct ucb1400_ts *ucb)
0065 {
0066 ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
0067 UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
0068 UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
0069 ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
0070 UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
0071 UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
0072 ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
0073 UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
0074 UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
0075
0076 udelay(ts_delay);
0077
0078 return ucb1400_adc_read(ucb->ac97, UCB_ADC_INP_TSPY, adcsync);
0079 }
0080
0081
0082
0083
0084
0085
0086
0087 static int ucb1400_ts_read_ypos(struct ucb1400_ts *ucb)
0088 {
0089 ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
0090 UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
0091 UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
0092 ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
0093 UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
0094 UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
0095 ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
0096 UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
0097 UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
0098
0099 udelay(ts_delay);
0100
0101 return ucb1400_adc_read(ucb->ac97, UCB_ADC_INP_TSPX, adcsync);
0102 }
0103
0104
0105
0106
0107
0108 static unsigned int ucb1400_ts_read_xres(struct ucb1400_ts *ucb)
0109 {
0110 ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
0111 UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
0112 UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
0113 return ucb1400_adc_read(ucb->ac97, 0, adcsync);
0114 }
0115
0116
0117
0118
0119
0120 static unsigned int ucb1400_ts_read_yres(struct ucb1400_ts *ucb)
0121 {
0122 ucb1400_reg_write(ucb->ac97, UCB_TS_CR,
0123 UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
0124 UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
0125 return ucb1400_adc_read(ucb->ac97, 0, adcsync);
0126 }
0127
0128 static int ucb1400_ts_pen_up(struct ucb1400_ts *ucb)
0129 {
0130 unsigned short val = ucb1400_reg_read(ucb->ac97, UCB_TS_CR);
0131
0132 return val & (UCB_TS_CR_TSPX_LOW | UCB_TS_CR_TSMX_LOW);
0133 }
0134
0135 static void ucb1400_ts_irq_enable(struct ucb1400_ts *ucb)
0136 {
0137 ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, UCB_IE_TSPX);
0138 ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, 0);
0139 ucb1400_reg_write(ucb->ac97, UCB_IE_FAL, UCB_IE_TSPX);
0140 }
0141
0142 static void ucb1400_ts_irq_disable(struct ucb1400_ts *ucb)
0143 {
0144 ucb1400_reg_write(ucb->ac97, UCB_IE_FAL, 0);
0145 }
0146
0147 static void ucb1400_ts_report_event(struct input_dev *idev, u16 pressure, u16 x, u16 y)
0148 {
0149 input_report_abs(idev, ABS_X, x);
0150 input_report_abs(idev, ABS_Y, y);
0151 input_report_abs(idev, ABS_PRESSURE, pressure);
0152 input_report_key(idev, BTN_TOUCH, 1);
0153 input_sync(idev);
0154 }
0155
0156 static void ucb1400_ts_event_release(struct input_dev *idev)
0157 {
0158 input_report_abs(idev, ABS_PRESSURE, 0);
0159 input_report_key(idev, BTN_TOUCH, 0);
0160 input_sync(idev);
0161 }
0162
0163 static void ucb1400_clear_pending_irq(struct ucb1400_ts *ucb)
0164 {
0165 unsigned int isr;
0166
0167 isr = ucb1400_reg_read(ucb->ac97, UCB_IE_STATUS);
0168 ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, isr);
0169 ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, 0);
0170
0171 if (isr & UCB_IE_TSPX)
0172 ucb1400_ts_irq_disable(ucb);
0173 else
0174 dev_dbg(&ucb->ts_idev->dev,
0175 "ucb1400: unexpected IE_STATUS = %#x\n", isr);
0176 }
0177
0178
0179
0180
0181
0182
0183
0184
0185 static irqreturn_t ucb1400_irq(int irqnr, void *devid)
0186 {
0187 struct ucb1400_ts *ucb = devid;
0188 unsigned int x, y, p;
0189
0190 if (unlikely(irqnr != ucb->irq))
0191 return IRQ_NONE;
0192
0193 ucb1400_clear_pending_irq(ucb);
0194
0195
0196 msleep(UCB1400_TS_POLL_PERIOD);
0197
0198 while (!ucb->stopped && !ucb1400_ts_pen_up(ucb)) {
0199 ucb1400_adc_enable(ucb->ac97);
0200 x = ucb1400_ts_read_xpos(ucb);
0201 y = ucb1400_ts_read_ypos(ucb);
0202 p = ucb1400_ts_read_pressure(ucb);
0203 ucb1400_adc_disable(ucb->ac97);
0204
0205 ucb1400_ts_report_event(ucb->ts_idev, p, x, y);
0206
0207 wait_event_timeout(ucb->ts_wait, ucb->stopped,
0208 msecs_to_jiffies(UCB1400_TS_POLL_PERIOD));
0209 }
0210
0211 ucb1400_ts_event_release(ucb->ts_idev);
0212
0213 if (!ucb->stopped) {
0214
0215 ucb1400_ts_mode_int(ucb);
0216 ucb1400_ts_irq_enable(ucb);
0217 }
0218
0219 return IRQ_HANDLED;
0220 }
0221
0222 static void ucb1400_ts_stop(struct ucb1400_ts *ucb)
0223 {
0224
0225 ucb->stopped = true;
0226 mb();
0227 wake_up(&ucb->ts_wait);
0228 disable_irq(ucb->irq);
0229
0230 ucb1400_ts_irq_disable(ucb);
0231 ucb1400_reg_write(ucb->ac97, UCB_TS_CR, 0);
0232 }
0233
0234
0235 static void ucb1400_ts_start(struct ucb1400_ts *ucb)
0236 {
0237
0238 ucb->stopped = false;
0239 mb();
0240
0241 ucb1400_ts_mode_int(ucb);
0242 ucb1400_ts_irq_enable(ucb);
0243
0244 enable_irq(ucb->irq);
0245 }
0246
0247 static int ucb1400_ts_open(struct input_dev *idev)
0248 {
0249 struct ucb1400_ts *ucb = input_get_drvdata(idev);
0250
0251 ucb1400_ts_start(ucb);
0252
0253 return 0;
0254 }
0255
0256 static void ucb1400_ts_close(struct input_dev *idev)
0257 {
0258 struct ucb1400_ts *ucb = input_get_drvdata(idev);
0259
0260 ucb1400_ts_stop(ucb);
0261 }
0262
0263 #ifndef NO_IRQ
0264 #define NO_IRQ 0
0265 #endif
0266
0267
0268
0269
0270
0271 static int ucb1400_ts_detect_irq(struct ucb1400_ts *ucb,
0272 struct platform_device *pdev)
0273 {
0274 unsigned long mask, timeout;
0275
0276 mask = probe_irq_on();
0277
0278
0279 ucb1400_reg_write(ucb->ac97, UCB_IE_RIS, UCB_IE_ADC);
0280 ucb1400_reg_write(ucb->ac97, UCB_IE_FAL, UCB_IE_ADC);
0281 ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, 0xffff);
0282 ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, 0);
0283
0284
0285 ucb1400_reg_write(ucb->ac97, UCB_ADC_CR, UCB_ADC_ENA);
0286 ucb1400_reg_write(ucb->ac97, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
0287
0288
0289 timeout = jiffies + HZ/2;
0290 while (!(ucb1400_reg_read(ucb->ac97, UCB_ADC_DATA) &
0291 UCB_ADC_DAT_VALID)) {
0292 cpu_relax();
0293 if (time_after(jiffies, timeout)) {
0294 dev_err(&pdev->dev, "timed out in IRQ probe\n");
0295 probe_irq_off(mask);
0296 return -ENODEV;
0297 }
0298 }
0299 ucb1400_reg_write(ucb->ac97, UCB_ADC_CR, 0);
0300
0301
0302 ucb1400_reg_write(ucb->ac97, UCB_IE_RIS, 0);
0303 ucb1400_reg_write(ucb->ac97, UCB_IE_FAL, 0);
0304 ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, 0xffff);
0305 ucb1400_reg_write(ucb->ac97, UCB_IE_CLEAR, 0);
0306
0307
0308 ucb->irq = probe_irq_off(mask);
0309 if (ucb->irq < 0 || ucb->irq == NO_IRQ)
0310 return -ENODEV;
0311
0312 return 0;
0313 }
0314
0315 static int ucb1400_ts_probe(struct platform_device *pdev)
0316 {
0317 struct ucb1400_ts *ucb = dev_get_platdata(&pdev->dev);
0318 int error, x_res, y_res;
0319 u16 fcsr;
0320
0321 ucb->ts_idev = input_allocate_device();
0322 if (!ucb->ts_idev) {
0323 error = -ENOMEM;
0324 goto err;
0325 }
0326
0327
0328 if (ucb->irq < 0) {
0329 error = ucb1400_ts_detect_irq(ucb, pdev);
0330 if (error) {
0331 dev_err(&pdev->dev, "IRQ probe failed\n");
0332 goto err_free_devs;
0333 }
0334 }
0335 dev_dbg(&pdev->dev, "found IRQ %d\n", ucb->irq);
0336
0337 init_waitqueue_head(&ucb->ts_wait);
0338
0339 input_set_drvdata(ucb->ts_idev, ucb);
0340
0341 ucb->ts_idev->dev.parent = &pdev->dev;
0342 ucb->ts_idev->name = "UCB1400 touchscreen interface";
0343 ucb->ts_idev->id.vendor = ucb1400_reg_read(ucb->ac97,
0344 AC97_VENDOR_ID1);
0345 ucb->ts_idev->id.product = ucb->id;
0346 ucb->ts_idev->open = ucb1400_ts_open;
0347 ucb->ts_idev->close = ucb1400_ts_close;
0348 ucb->ts_idev->evbit[0] = BIT_MASK(EV_ABS) | BIT_MASK(EV_KEY);
0349 ucb->ts_idev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
0350
0351
0352
0353
0354
0355
0356 fcsr = ucb1400_reg_read(ucb->ac97, UCB_FCSR);
0357 ucb1400_reg_write(ucb->ac97, UCB_FCSR, fcsr | UCB_FCSR_AVE);
0358
0359 ucb1400_adc_enable(ucb->ac97);
0360 x_res = ucb1400_ts_read_xres(ucb);
0361 y_res = ucb1400_ts_read_yres(ucb);
0362 ucb1400_adc_disable(ucb->ac97);
0363 dev_dbg(&pdev->dev, "x/y = %d/%d\n", x_res, y_res);
0364
0365 input_set_abs_params(ucb->ts_idev, ABS_X, 0, x_res, 0, 0);
0366 input_set_abs_params(ucb->ts_idev, ABS_Y, 0, y_res, 0, 0);
0367 input_set_abs_params(ucb->ts_idev, ABS_PRESSURE, 0, 0, 0, 0);
0368
0369 ucb1400_ts_stop(ucb);
0370
0371 error = request_threaded_irq(ucb->irq, NULL, ucb1400_irq,
0372 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
0373 "UCB1400", ucb);
0374 if (error) {
0375 dev_err(&pdev->dev,
0376 "unable to grab irq%d: %d\n", ucb->irq, error);
0377 goto err_free_devs;
0378 }
0379
0380 error = input_register_device(ucb->ts_idev);
0381 if (error)
0382 goto err_free_irq;
0383
0384 return 0;
0385
0386 err_free_irq:
0387 free_irq(ucb->irq, ucb);
0388 err_free_devs:
0389 input_free_device(ucb->ts_idev);
0390 err:
0391 return error;
0392 }
0393
0394 static int ucb1400_ts_remove(struct platform_device *pdev)
0395 {
0396 struct ucb1400_ts *ucb = dev_get_platdata(&pdev->dev);
0397
0398 free_irq(ucb->irq, ucb);
0399 input_unregister_device(ucb->ts_idev);
0400
0401 return 0;
0402 }
0403
0404 static int __maybe_unused ucb1400_ts_suspend(struct device *dev)
0405 {
0406 struct ucb1400_ts *ucb = dev_get_platdata(dev);
0407 struct input_dev *idev = ucb->ts_idev;
0408
0409 mutex_lock(&idev->mutex);
0410
0411 if (input_device_enabled(idev))
0412 ucb1400_ts_stop(ucb);
0413
0414 mutex_unlock(&idev->mutex);
0415 return 0;
0416 }
0417
0418 static int __maybe_unused ucb1400_ts_resume(struct device *dev)
0419 {
0420 struct ucb1400_ts *ucb = dev_get_platdata(dev);
0421 struct input_dev *idev = ucb->ts_idev;
0422
0423 mutex_lock(&idev->mutex);
0424
0425 if (input_device_enabled(idev))
0426 ucb1400_ts_start(ucb);
0427
0428 mutex_unlock(&idev->mutex);
0429 return 0;
0430 }
0431
0432 static SIMPLE_DEV_PM_OPS(ucb1400_ts_pm_ops,
0433 ucb1400_ts_suspend, ucb1400_ts_resume);
0434
0435 static struct platform_driver ucb1400_ts_driver = {
0436 .probe = ucb1400_ts_probe,
0437 .remove = ucb1400_ts_remove,
0438 .driver = {
0439 .name = "ucb1400_ts",
0440 .pm = &ucb1400_ts_pm_ops,
0441 },
0442 };
0443 module_platform_driver(ucb1400_ts_driver);
0444
0445 module_param(adcsync, bool, 0444);
0446 MODULE_PARM_DESC(adcsync, "Synchronize touch readings with ADCSYNC pin.");
0447
0448 module_param(ts_delay, int, 0444);
0449 MODULE_PARM_DESC(ts_delay, "Delay between panel setup and"
0450 " position read. Default = 55us.");
0451
0452 module_param(ts_delay_pressure, int, 0444);
0453 MODULE_PARM_DESC(ts_delay_pressure,
0454 "delay between panel setup and pressure read."
0455 " Default = 0us.");
0456
0457 MODULE_DESCRIPTION("Philips UCB1400 touchscreen driver");
0458 MODULE_LICENSE("GPL");