input/touchscreen/tsc200x-core.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _TSC200X_CORE_H
0003 #define _TSC200X_CORE_H
0004
0005 /* control byte 1 */
0006 #define TSC200X_CMD         0x80
0007 #define TSC200X_CMD_NORMAL      0x00
0008 #define TSC200X_CMD_STOP        0x01
0009 #define TSC200X_CMD_12BIT       0x04
0010
0011 /* control byte 0 */
0012 #define TSC200X_REG_READ        0x01 /* R/W access */
0013 #define TSC200X_REG_PND0        0x02 /* Power Not Down Control */
0014 #define TSC200X_REG_X           (0x0 << 3)
0015 #define TSC200X_REG_Y           (0x1 << 3)
0016 #define TSC200X_REG_Z1          (0x2 << 3)
0017 #define TSC200X_REG_Z2          (0x3 << 3)
0018 #define TSC200X_REG_AUX         (0x4 << 3)
0019 #define TSC200X_REG_TEMP1       (0x5 << 3)
0020 #define TSC200X_REG_TEMP2       (0x6 << 3)
0021 #define TSC200X_REG_STATUS      (0x7 << 3)
0022 #define TSC200X_REG_AUX_HIGH        (0x8 << 3)
0023 #define TSC200X_REG_AUX_LOW     (0x9 << 3)
0024 #define TSC200X_REG_TEMP_HIGH       (0xA << 3)
0025 #define TSC200X_REG_TEMP_LOW        (0xB << 3)
0026 #define TSC200X_REG_CFR0        (0xC << 3)
0027 #define TSC200X_REG_CFR1        (0xD << 3)
0028 #define TSC200X_REG_CFR2        (0xE << 3)
0029 #define TSC200X_REG_CONV_FUNC       (0xF << 3)
0030
0031 /* configuration register 0 */
0032 #define TSC200X_CFR0_PRECHARGE_276US    0x0040
0033 #define TSC200X_CFR0_STABTIME_1MS   0x0300
0034 #define TSC200X_CFR0_CLOCK_1MHZ     0x1000
0035 #define TSC200X_CFR0_RESOLUTION12   0x2000
0036 #define TSC200X_CFR0_PENMODE        0x8000
0037 #define TSC200X_CFR0_INITVALUE      (TSC200X_CFR0_STABTIME_1MS    | \
0038                      TSC200X_CFR0_CLOCK_1MHZ      | \
0039                      TSC200X_CFR0_RESOLUTION12    | \
0040                      TSC200X_CFR0_PRECHARGE_276US | \
0041                      TSC200X_CFR0_PENMODE)
0042
0043 /* bits common to both read and write of configuration register 0 */
0044 #define TSC200X_CFR0_RW_MASK        0x3fff
0045
0046 /* configuration register 1 */
0047 #define TSC200X_CFR1_BATCHDELAY_4MS 0x0003
0048 #define TSC200X_CFR1_INITVALUE      TSC200X_CFR1_BATCHDELAY_4MS
0049
0050 /* configuration register 2 */
0051 #define TSC200X_CFR2_MAVE_Z     0x0004
0052 #define TSC200X_CFR2_MAVE_Y     0x0008
0053 #define TSC200X_CFR2_MAVE_X     0x0010
0054 #define TSC200X_CFR2_AVG_7      0x0800
0055 #define TSC200X_CFR2_MEDIUM_15      0x3000
0056 #define TSC200X_CFR2_INITVALUE      (TSC200X_CFR2_MAVE_X    | \
0057                      TSC200X_CFR2_MAVE_Y    | \
0058                      TSC200X_CFR2_MAVE_Z    | \
0059                      TSC200X_CFR2_MEDIUM_15 | \
0060                      TSC200X_CFR2_AVG_7)
0061
0062 #define MAX_12BIT           0xfff
0063 #define TSC200X_DEF_X_FUZZ      4
0064 #define TSC200X_DEF_Y_FUZZ      8
0065 #define TSC200X_DEF_P_FUZZ      2
0066 #define TSC200X_DEF_RESISTOR        280
0067
0068 #define TSC2005_SPI_MAX_SPEED_HZ    10000000
0069 #define TSC200X_PENUP_TIME_MS       40
0070
0071 extern const struct regmap_config tsc200x_regmap_config;
0072 extern const struct dev_pm_ops tsc200x_pm_ops;
0073
0074 int tsc200x_probe(struct device *dev, int irq, const struct input_id *tsc_id,
0075           struct regmap *regmap,
0076           int (*tsc200x_cmd)(struct device *dev, u8 cmd));
0077 void tsc200x_remove(struct device *dev);
0078
0079 #endif