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0007 #include <linux/errno.h>
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/gpio/consumer.h>
0011 #include <linux/input.h>
0012 #include <linux/slab.h>
0013 #include <linux/completion.h>
0014 #include <linux/delay.h>
0015 #include <linux/of.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/clk.h>
0019 #include <linux/io.h>
0020 #include <linux/log2.h>
0021
0022
0023 #define ADC_AIEN (0x1 << 7)
0024 #define ADC_CONV_DISABLE 0x1F
0025 #define ADC_AVGE (0x1 << 5)
0026 #define ADC_CAL (0x1 << 7)
0027 #define ADC_CALF 0x2
0028 #define ADC_12BIT_MODE (0x2 << 2)
0029 #define ADC_CONV_MODE_MASK (0x3 << 2)
0030 #define ADC_IPG_CLK 0x00
0031 #define ADC_INPUT_CLK_MASK 0x3
0032 #define ADC_CLK_DIV_8 (0x03 << 5)
0033 #define ADC_CLK_DIV_MASK (0x3 << 5)
0034 #define ADC_SHORT_SAMPLE_MODE (0x0 << 4)
0035 #define ADC_SAMPLE_MODE_MASK (0x1 << 4)
0036 #define ADC_HARDWARE_TRIGGER (0x1 << 13)
0037 #define ADC_AVGS_SHIFT 14
0038 #define ADC_AVGS_MASK (0x3 << 14)
0039 #define SELECT_CHANNEL_4 0x04
0040 #define SELECT_CHANNEL_1 0x01
0041 #define DISABLE_CONVERSION_INT (0x0 << 7)
0042
0043
0044 #define REG_ADC_HC0 0x00
0045 #define REG_ADC_HC1 0x04
0046 #define REG_ADC_HC2 0x08
0047 #define REG_ADC_HC3 0x0C
0048 #define REG_ADC_HC4 0x10
0049 #define REG_ADC_HS 0x14
0050 #define REG_ADC_R0 0x18
0051 #define REG_ADC_CFG 0x2C
0052 #define REG_ADC_GC 0x30
0053 #define REG_ADC_GS 0x34
0054
0055 #define ADC_TIMEOUT msecs_to_jiffies(100)
0056
0057
0058 #define REG_TSC_BASIC_SETING 0x00
0059 #define REG_TSC_PRE_CHARGE_TIME 0x10
0060 #define REG_TSC_FLOW_CONTROL 0x20
0061 #define REG_TSC_MEASURE_VALUE 0x30
0062 #define REG_TSC_INT_EN 0x40
0063 #define REG_TSC_INT_SIG_EN 0x50
0064 #define REG_TSC_INT_STATUS 0x60
0065 #define REG_TSC_DEBUG_MODE 0x70
0066 #define REG_TSC_DEBUG_MODE2 0x80
0067
0068
0069 #define DETECT_4_WIRE_MODE (0x0 << 4)
0070 #define AUTO_MEASURE 0x1
0071 #define MEASURE_SIGNAL 0x1
0072 #define DETECT_SIGNAL (0x1 << 4)
0073 #define VALID_SIGNAL (0x1 << 8)
0074 #define MEASURE_INT_EN 0x1
0075 #define MEASURE_SIG_EN 0x1
0076 #define VALID_SIG_EN (0x1 << 8)
0077 #define DE_GLITCH_2 (0x2 << 29)
0078 #define START_SENSE (0x1 << 12)
0079 #define TSC_DISABLE (0x1 << 16)
0080 #define DETECT_MODE 0x2
0081
0082 struct imx6ul_tsc {
0083 struct device *dev;
0084 struct input_dev *input;
0085 void __iomem *tsc_regs;
0086 void __iomem *adc_regs;
0087 struct clk *tsc_clk;
0088 struct clk *adc_clk;
0089 struct gpio_desc *xnur_gpio;
0090
0091 u32 measure_delay_time;
0092 u32 pre_charge_time;
0093 bool average_enable;
0094 u32 average_select;
0095
0096 struct completion completion;
0097 };
0098
0099
0100
0101
0102
0103 static int imx6ul_adc_init(struct imx6ul_tsc *tsc)
0104 {
0105 u32 adc_hc = 0;
0106 u32 adc_gc;
0107 u32 adc_gs;
0108 u32 adc_cfg;
0109 unsigned long timeout;
0110
0111 reinit_completion(&tsc->completion);
0112
0113 adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG);
0114 adc_cfg &= ~(ADC_CONV_MODE_MASK | ADC_INPUT_CLK_MASK);
0115 adc_cfg |= ADC_12BIT_MODE | ADC_IPG_CLK;
0116 adc_cfg &= ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE_MASK);
0117 adc_cfg |= ADC_CLK_DIV_8 | ADC_SHORT_SAMPLE_MODE;
0118 if (tsc->average_enable) {
0119 adc_cfg &= ~ADC_AVGS_MASK;
0120 adc_cfg |= (tsc->average_select) << ADC_AVGS_SHIFT;
0121 }
0122 adc_cfg &= ~ADC_HARDWARE_TRIGGER;
0123 writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG);
0124
0125
0126 adc_hc |= ADC_AIEN;
0127 adc_hc |= ADC_CONV_DISABLE;
0128 writel(adc_hc, tsc->adc_regs + REG_ADC_HC0);
0129
0130
0131 adc_gc = readl(tsc->adc_regs + REG_ADC_GC);
0132 adc_gc |= ADC_CAL;
0133 if (tsc->average_enable)
0134 adc_gc |= ADC_AVGE;
0135 writel(adc_gc, tsc->adc_regs + REG_ADC_GC);
0136
0137 timeout = wait_for_completion_timeout
0138 (&tsc->completion, ADC_TIMEOUT);
0139 if (timeout == 0) {
0140 dev_err(tsc->dev, "Timeout for adc calibration\n");
0141 return -ETIMEDOUT;
0142 }
0143
0144 adc_gs = readl(tsc->adc_regs + REG_ADC_GS);
0145 if (adc_gs & ADC_CALF) {
0146 dev_err(tsc->dev, "ADC calibration failed\n");
0147 return -EINVAL;
0148 }
0149
0150
0151 adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG);
0152 adc_cfg |= ADC_HARDWARE_TRIGGER;
0153 writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG);
0154
0155 return 0;
0156 }
0157
0158
0159
0160
0161
0162
0163 static void imx6ul_tsc_channel_config(struct imx6ul_tsc *tsc)
0164 {
0165 u32 adc_hc0, adc_hc1, adc_hc2, adc_hc3, adc_hc4;
0166
0167 adc_hc0 = DISABLE_CONVERSION_INT;
0168 writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0);
0169
0170 adc_hc1 = DISABLE_CONVERSION_INT | SELECT_CHANNEL_4;
0171 writel(adc_hc1, tsc->adc_regs + REG_ADC_HC1);
0172
0173 adc_hc2 = DISABLE_CONVERSION_INT;
0174 writel(adc_hc2, tsc->adc_regs + REG_ADC_HC2);
0175
0176 adc_hc3 = DISABLE_CONVERSION_INT | SELECT_CHANNEL_1;
0177 writel(adc_hc3, tsc->adc_regs + REG_ADC_HC3);
0178
0179 adc_hc4 = DISABLE_CONVERSION_INT;
0180 writel(adc_hc4, tsc->adc_regs + REG_ADC_HC4);
0181 }
0182
0183
0184
0185
0186
0187
0188 static void imx6ul_tsc_set(struct imx6ul_tsc *tsc)
0189 {
0190 u32 basic_setting = 0;
0191 u32 start;
0192
0193 basic_setting |= tsc->measure_delay_time << 8;
0194 basic_setting |= DETECT_4_WIRE_MODE | AUTO_MEASURE;
0195 writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETING);
0196
0197 writel(DE_GLITCH_2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2);
0198
0199 writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME);
0200 writel(MEASURE_INT_EN, tsc->tsc_regs + REG_TSC_INT_EN);
0201 writel(MEASURE_SIG_EN | VALID_SIG_EN,
0202 tsc->tsc_regs + REG_TSC_INT_SIG_EN);
0203
0204
0205 start = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
0206 start |= START_SENSE;
0207 start &= ~TSC_DISABLE;
0208 writel(start, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
0209 }
0210
0211 static int imx6ul_tsc_init(struct imx6ul_tsc *tsc)
0212 {
0213 int err;
0214
0215 err = imx6ul_adc_init(tsc);
0216 if (err)
0217 return err;
0218 imx6ul_tsc_channel_config(tsc);
0219 imx6ul_tsc_set(tsc);
0220
0221 return 0;
0222 }
0223
0224 static void imx6ul_tsc_disable(struct imx6ul_tsc *tsc)
0225 {
0226 u32 tsc_flow;
0227 u32 adc_cfg;
0228
0229
0230 tsc_flow = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
0231 tsc_flow |= TSC_DISABLE;
0232 writel(tsc_flow, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
0233
0234
0235 adc_cfg = readl(tsc->adc_regs + REG_ADC_HC0);
0236 adc_cfg |= ADC_CONV_DISABLE;
0237 writel(adc_cfg, tsc->adc_regs + REG_ADC_HC0);
0238 }
0239
0240
0241 static bool tsc_wait_detect_mode(struct imx6ul_tsc *tsc)
0242 {
0243 unsigned long timeout = jiffies + msecs_to_jiffies(2);
0244 u32 state_machine;
0245 u32 debug_mode2;
0246
0247 do {
0248 if (time_after(jiffies, timeout))
0249 return false;
0250
0251 usleep_range(200, 400);
0252 debug_mode2 = readl(tsc->tsc_regs + REG_TSC_DEBUG_MODE2);
0253 state_machine = (debug_mode2 >> 20) & 0x7;
0254 } while (state_machine != DETECT_MODE);
0255
0256 usleep_range(200, 400);
0257 return true;
0258 }
0259
0260 static irqreturn_t tsc_irq_fn(int irq, void *dev_id)
0261 {
0262 struct imx6ul_tsc *tsc = dev_id;
0263 u32 status;
0264 u32 value;
0265 u32 x, y;
0266 u32 start;
0267
0268 status = readl(tsc->tsc_regs + REG_TSC_INT_STATUS);
0269
0270
0271 writel(MEASURE_SIGNAL | DETECT_SIGNAL,
0272 tsc->tsc_regs + REG_TSC_INT_STATUS);
0273
0274
0275 start = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
0276 start |= START_SENSE;
0277 writel(start, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
0278
0279 if (status & MEASURE_SIGNAL) {
0280 value = readl(tsc->tsc_regs + REG_TSC_MEASURE_VALUE);
0281 x = (value >> 16) & 0x0fff;
0282 y = value & 0x0fff;
0283
0284
0285
0286
0287
0288 if (!tsc_wait_detect_mode(tsc) ||
0289 gpiod_get_value_cansleep(tsc->xnur_gpio)) {
0290 input_report_key(tsc->input, BTN_TOUCH, 1);
0291 input_report_abs(tsc->input, ABS_X, x);
0292 input_report_abs(tsc->input, ABS_Y, y);
0293 } else {
0294 input_report_key(tsc->input, BTN_TOUCH, 0);
0295 }
0296
0297 input_sync(tsc->input);
0298 }
0299
0300 return IRQ_HANDLED;
0301 }
0302
0303 static irqreturn_t adc_irq_fn(int irq, void *dev_id)
0304 {
0305 struct imx6ul_tsc *tsc = dev_id;
0306 u32 coco;
0307
0308 coco = readl(tsc->adc_regs + REG_ADC_HS);
0309 if (coco & 0x01) {
0310 readl(tsc->adc_regs + REG_ADC_R0);
0311 complete(&tsc->completion);
0312 }
0313
0314 return IRQ_HANDLED;
0315 }
0316
0317 static int imx6ul_tsc_start(struct imx6ul_tsc *tsc)
0318 {
0319 int err;
0320
0321 err = clk_prepare_enable(tsc->adc_clk);
0322 if (err) {
0323 dev_err(tsc->dev,
0324 "Could not prepare or enable the adc clock: %d\n",
0325 err);
0326 return err;
0327 }
0328
0329 err = clk_prepare_enable(tsc->tsc_clk);
0330 if (err) {
0331 dev_err(tsc->dev,
0332 "Could not prepare or enable the tsc clock: %d\n",
0333 err);
0334 goto disable_adc_clk;
0335 }
0336
0337 err = imx6ul_tsc_init(tsc);
0338 if (err)
0339 goto disable_tsc_clk;
0340
0341 return 0;
0342
0343 disable_tsc_clk:
0344 clk_disable_unprepare(tsc->tsc_clk);
0345 disable_adc_clk:
0346 clk_disable_unprepare(tsc->adc_clk);
0347 return err;
0348 }
0349
0350 static void imx6ul_tsc_stop(struct imx6ul_tsc *tsc)
0351 {
0352 imx6ul_tsc_disable(tsc);
0353
0354 clk_disable_unprepare(tsc->tsc_clk);
0355 clk_disable_unprepare(tsc->adc_clk);
0356 }
0357
0358
0359 static int imx6ul_tsc_open(struct input_dev *input_dev)
0360 {
0361 struct imx6ul_tsc *tsc = input_get_drvdata(input_dev);
0362
0363 return imx6ul_tsc_start(tsc);
0364 }
0365
0366 static void imx6ul_tsc_close(struct input_dev *input_dev)
0367 {
0368 struct imx6ul_tsc *tsc = input_get_drvdata(input_dev);
0369
0370 imx6ul_tsc_stop(tsc);
0371 }
0372
0373 static int imx6ul_tsc_probe(struct platform_device *pdev)
0374 {
0375 struct device_node *np = pdev->dev.of_node;
0376 struct imx6ul_tsc *tsc;
0377 struct input_dev *input_dev;
0378 int err;
0379 int tsc_irq;
0380 int adc_irq;
0381 u32 average_samples;
0382
0383 tsc = devm_kzalloc(&pdev->dev, sizeof(*tsc), GFP_KERNEL);
0384 if (!tsc)
0385 return -ENOMEM;
0386
0387 input_dev = devm_input_allocate_device(&pdev->dev);
0388 if (!input_dev)
0389 return -ENOMEM;
0390
0391 input_dev->name = "iMX6UL Touchscreen Controller";
0392 input_dev->id.bustype = BUS_HOST;
0393
0394 input_dev->open = imx6ul_tsc_open;
0395 input_dev->close = imx6ul_tsc_close;
0396
0397 input_set_capability(input_dev, EV_KEY, BTN_TOUCH);
0398 input_set_abs_params(input_dev, ABS_X, 0, 0xFFF, 0, 0);
0399 input_set_abs_params(input_dev, ABS_Y, 0, 0xFFF, 0, 0);
0400
0401 input_set_drvdata(input_dev, tsc);
0402
0403 tsc->dev = &pdev->dev;
0404 tsc->input = input_dev;
0405 init_completion(&tsc->completion);
0406
0407 tsc->xnur_gpio = devm_gpiod_get(&pdev->dev, "xnur", GPIOD_IN);
0408 if (IS_ERR(tsc->xnur_gpio)) {
0409 err = PTR_ERR(tsc->xnur_gpio);
0410 dev_err(&pdev->dev,
0411 "failed to request GPIO tsc_X- (xnur): %d\n", err);
0412 return err;
0413 }
0414
0415 tsc->tsc_regs = devm_platform_ioremap_resource(pdev, 0);
0416 if (IS_ERR(tsc->tsc_regs)) {
0417 err = PTR_ERR(tsc->tsc_regs);
0418 dev_err(&pdev->dev, "failed to remap tsc memory: %d\n", err);
0419 return err;
0420 }
0421
0422 tsc->adc_regs = devm_platform_ioremap_resource(pdev, 1);
0423 if (IS_ERR(tsc->adc_regs)) {
0424 err = PTR_ERR(tsc->adc_regs);
0425 dev_err(&pdev->dev, "failed to remap adc memory: %d\n", err);
0426 return err;
0427 }
0428
0429 tsc->tsc_clk = devm_clk_get(&pdev->dev, "tsc");
0430 if (IS_ERR(tsc->tsc_clk)) {
0431 err = PTR_ERR(tsc->tsc_clk);
0432 dev_err(&pdev->dev, "failed getting tsc clock: %d\n", err);
0433 return err;
0434 }
0435
0436 tsc->adc_clk = devm_clk_get(&pdev->dev, "adc");
0437 if (IS_ERR(tsc->adc_clk)) {
0438 err = PTR_ERR(tsc->adc_clk);
0439 dev_err(&pdev->dev, "failed getting adc clock: %d\n", err);
0440 return err;
0441 }
0442
0443 tsc_irq = platform_get_irq(pdev, 0);
0444 if (tsc_irq < 0)
0445 return tsc_irq;
0446
0447 adc_irq = platform_get_irq(pdev, 1);
0448 if (adc_irq < 0)
0449 return adc_irq;
0450
0451 err = devm_request_threaded_irq(tsc->dev, tsc_irq,
0452 NULL, tsc_irq_fn, IRQF_ONESHOT,
0453 dev_name(&pdev->dev), tsc);
0454 if (err) {
0455 dev_err(&pdev->dev,
0456 "failed requesting tsc irq %d: %d\n",
0457 tsc_irq, err);
0458 return err;
0459 }
0460
0461 err = devm_request_irq(tsc->dev, adc_irq, adc_irq_fn, 0,
0462 dev_name(&pdev->dev), tsc);
0463 if (err) {
0464 dev_err(&pdev->dev,
0465 "failed requesting adc irq %d: %d\n",
0466 adc_irq, err);
0467 return err;
0468 }
0469
0470 err = of_property_read_u32(np, "measure-delay-time",
0471 &tsc->measure_delay_time);
0472 if (err)
0473 tsc->measure_delay_time = 0xffff;
0474
0475 err = of_property_read_u32(np, "pre-charge-time",
0476 &tsc->pre_charge_time);
0477 if (err)
0478 tsc->pre_charge_time = 0xfff;
0479
0480 err = of_property_read_u32(np, "touchscreen-average-samples",
0481 &average_samples);
0482 if (err)
0483 average_samples = 1;
0484
0485 switch (average_samples) {
0486 case 1:
0487 tsc->average_enable = false;
0488 tsc->average_select = 0;
0489 break;
0490 case 4:
0491 case 8:
0492 case 16:
0493 case 32:
0494 tsc->average_enable = true;
0495 tsc->average_select = ilog2(average_samples) - 2;
0496 break;
0497 default:
0498 dev_err(&pdev->dev,
0499 "touchscreen-average-samples (%u) must be 1, 4, 8, 16 or 32\n",
0500 average_samples);
0501 return -EINVAL;
0502 }
0503
0504 err = input_register_device(tsc->input);
0505 if (err) {
0506 dev_err(&pdev->dev,
0507 "failed to register input device: %d\n", err);
0508 return err;
0509 }
0510
0511 platform_set_drvdata(pdev, tsc);
0512 return 0;
0513 }
0514
0515 static int __maybe_unused imx6ul_tsc_suspend(struct device *dev)
0516 {
0517 struct platform_device *pdev = to_platform_device(dev);
0518 struct imx6ul_tsc *tsc = platform_get_drvdata(pdev);
0519 struct input_dev *input_dev = tsc->input;
0520
0521 mutex_lock(&input_dev->mutex);
0522
0523 if (input_device_enabled(input_dev))
0524 imx6ul_tsc_stop(tsc);
0525
0526 mutex_unlock(&input_dev->mutex);
0527
0528 return 0;
0529 }
0530
0531 static int __maybe_unused imx6ul_tsc_resume(struct device *dev)
0532 {
0533 struct platform_device *pdev = to_platform_device(dev);
0534 struct imx6ul_tsc *tsc = platform_get_drvdata(pdev);
0535 struct input_dev *input_dev = tsc->input;
0536 int retval = 0;
0537
0538 mutex_lock(&input_dev->mutex);
0539
0540 if (input_device_enabled(input_dev))
0541 retval = imx6ul_tsc_start(tsc);
0542
0543 mutex_unlock(&input_dev->mutex);
0544
0545 return retval;
0546 }
0547
0548 static SIMPLE_DEV_PM_OPS(imx6ul_tsc_pm_ops,
0549 imx6ul_tsc_suspend, imx6ul_tsc_resume);
0550
0551 static const struct of_device_id imx6ul_tsc_match[] = {
0552 { .compatible = "fsl,imx6ul-tsc", },
0553 { }
0554 };
0555 MODULE_DEVICE_TABLE(of, imx6ul_tsc_match);
0556
0557 static struct platform_driver imx6ul_tsc_driver = {
0558 .driver = {
0559 .name = "imx6ul-tsc",
0560 .of_match_table = imx6ul_tsc_match,
0561 .pm = &imx6ul_tsc_pm_ops,
0562 },
0563 .probe = imx6ul_tsc_probe,
0564 };
0565 module_platform_driver(imx6ul_tsc_driver);
0566
0567 MODULE_AUTHOR("Haibo Chen <haibo.chen@freescale.com>");
0568 MODULE_DESCRIPTION("Freescale i.MX6UL Touchscreen controller driver");
0569 MODULE_LICENSE("GPL v2");