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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2012-2017 Hideep, Inc.
0004  */
0005 
0006 #include <linux/module.h>
0007 #include <linux/of.h>
0008 #include <linux/firmware.h>
0009 #include <linux/delay.h>
0010 #include <linux/gpio/consumer.h>
0011 #include <linux/i2c.h>
0012 #include <linux/acpi.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/regmap.h>
0015 #include <linux/sysfs.h>
0016 #include <linux/input.h>
0017 #include <linux/input/mt.h>
0018 #include <linux/input/touchscreen.h>
0019 #include <linux/regulator/consumer.h>
0020 #include <asm/unaligned.h>
0021 
0022 #define HIDEEP_TS_NAME          "HiDeep Touchscreen"
0023 #define HIDEEP_I2C_NAME         "hideep_ts"
0024 
0025 #define HIDEEP_MT_MAX           10
0026 #define HIDEEP_KEY_MAX          3
0027 
0028 /* count(2) + touch data(100) + key data(6) */
0029 #define HIDEEP_MAX_EVENT        108UL
0030 
0031 #define HIDEEP_TOUCH_EVENT_INDEX    2
0032 #define HIDEEP_KEY_EVENT_INDEX      102
0033 
0034 /* Touch & key event */
0035 #define HIDEEP_EVENT_ADDR       0x240
0036 
0037 /* command list */
0038 #define HIDEEP_RESET_CMD        0x9800
0039 
0040 /* event bit */
0041 #define HIDEEP_MT_RELEASED      BIT(4)
0042 #define HIDEEP_KEY_PRESSED      BIT(7)
0043 #define HIDEEP_KEY_FIRST_PRESSED    BIT(8)
0044 #define HIDEEP_KEY_PRESSED_MASK     (HIDEEP_KEY_PRESSED | \
0045                      HIDEEP_KEY_FIRST_PRESSED)
0046 
0047 #define HIDEEP_KEY_IDX_MASK     0x0f
0048 
0049 /* For NVM */
0050 #define HIDEEP_YRAM_BASE        0x40000000
0051 #define HIDEEP_PERIPHERAL_BASE      0x50000000
0052 #define HIDEEP_ESI_BASE         (HIDEEP_PERIPHERAL_BASE + 0x00000000)
0053 #define HIDEEP_FLASH_BASE       (HIDEEP_PERIPHERAL_BASE + 0x01000000)
0054 #define HIDEEP_SYSCON_BASE      (HIDEEP_PERIPHERAL_BASE + 0x02000000)
0055 
0056 #define HIDEEP_SYSCON_MOD_CON       (HIDEEP_SYSCON_BASE + 0x0000)
0057 #define HIDEEP_SYSCON_SPC_CON       (HIDEEP_SYSCON_BASE + 0x0004)
0058 #define HIDEEP_SYSCON_CLK_CON       (HIDEEP_SYSCON_BASE + 0x0008)
0059 #define HIDEEP_SYSCON_CLK_ENA       (HIDEEP_SYSCON_BASE + 0x000C)
0060 #define HIDEEP_SYSCON_RST_CON       (HIDEEP_SYSCON_BASE + 0x0010)
0061 #define HIDEEP_SYSCON_WDT_CON       (HIDEEP_SYSCON_BASE + 0x0014)
0062 #define HIDEEP_SYSCON_WDT_CNT       (HIDEEP_SYSCON_BASE + 0x0018)
0063 #define HIDEEP_SYSCON_PWR_CON       (HIDEEP_SYSCON_BASE + 0x0020)
0064 #define HIDEEP_SYSCON_PGM_ID        (HIDEEP_SYSCON_BASE + 0x00F4)
0065 
0066 #define HIDEEP_FLASH_CON        (HIDEEP_FLASH_BASE + 0x0000)
0067 #define HIDEEP_FLASH_STA        (HIDEEP_FLASH_BASE + 0x0004)
0068 #define HIDEEP_FLASH_CFG        (HIDEEP_FLASH_BASE + 0x0008)
0069 #define HIDEEP_FLASH_TIM        (HIDEEP_FLASH_BASE + 0x000C)
0070 #define HIDEEP_FLASH_CACHE_CFG      (HIDEEP_FLASH_BASE + 0x0010)
0071 #define HIDEEP_FLASH_PIO_SIG        (HIDEEP_FLASH_BASE + 0x400000)
0072 
0073 #define HIDEEP_ESI_TX_INVALID       (HIDEEP_ESI_BASE + 0x0008)
0074 
0075 #define HIDEEP_PERASE           0x00040000
0076 #define HIDEEP_WRONLY           0x00100000
0077 
0078 #define HIDEEP_NVM_MASK_OFS     0x0000000C
0079 #define HIDEEP_NVM_DEFAULT_PAGE     0
0080 #define HIDEEP_NVM_SFR_WPAGE        1
0081 #define HIDEEP_NVM_SFR_RPAGE        2
0082 
0083 #define HIDEEP_PIO_SIG          0x00400000
0084 #define HIDEEP_PROT_MODE        0x03400000
0085 
0086 #define HIDEEP_NVM_PAGE_SIZE        128
0087 
0088 #define HIDEEP_DWZ_INFO         0x000002C0
0089 
0090 struct hideep_event {
0091     __le16 x;
0092     __le16 y;
0093     __le16 z;
0094     u8 w;
0095     u8 flag;
0096     u8 type;
0097     u8 index;
0098 };
0099 
0100 struct dwz_info {
0101     __be32 code_start;
0102     u8 code_crc[12];
0103 
0104     __be32 c_code_start;
0105     __be16 gen_ver;
0106     __be16 c_code_len;
0107 
0108     __be32 vr_start;
0109     __be16 rsv0;
0110     __be16 vr_len;
0111 
0112     __be32 ft_start;
0113     __be16 vr_version;
0114     __be16 ft_len;
0115 
0116     __be16 core_ver;
0117     __be16 boot_ver;
0118 
0119     __be16 release_ver;
0120     __be16 custom_ver;
0121 
0122     u8 factory_id;
0123     u8 panel_type;
0124     u8 model_name[6];
0125 
0126     __be16 extra_option;
0127     __be16 product_code;
0128 
0129     __be16 vendor_id;
0130     __be16 product_id;
0131 };
0132 
0133 struct pgm_packet {
0134     struct {
0135         u8 unused[3];
0136         u8 len;
0137         __be32 addr;
0138     } header;
0139     __be32 payload[HIDEEP_NVM_PAGE_SIZE / sizeof(__be32)];
0140 };
0141 
0142 #define HIDEEP_XFER_BUF_SIZE    sizeof(struct pgm_packet)
0143 
0144 struct hideep_ts {
0145     struct i2c_client *client;
0146     struct input_dev *input_dev;
0147     struct regmap *reg;
0148 
0149     struct touchscreen_properties prop;
0150 
0151     struct gpio_desc *reset_gpio;
0152 
0153     struct regulator *vcc_vdd;
0154     struct regulator *vcc_vid;
0155 
0156     struct mutex dev_mutex;
0157 
0158     u32 tch_count;
0159     u32 lpm_count;
0160 
0161     /*
0162      * Data buffer to read packet from the device (contacts and key
0163      * states). We align it on double-word boundary to keep word-sized
0164      * fields in contact data and double-word-sized fields in program
0165      * packet aligned.
0166      */
0167     u8 xfer_buf[HIDEEP_XFER_BUF_SIZE] __aligned(4);
0168 
0169     int key_num;
0170     u32 key_codes[HIDEEP_KEY_MAX];
0171 
0172     struct dwz_info dwz_info;
0173 
0174     unsigned int fw_size;
0175     u32 nvm_mask;
0176 };
0177 
0178 static int hideep_pgm_w_mem(struct hideep_ts *ts, u32 addr,
0179                 const __be32 *data, size_t count)
0180 {
0181     struct pgm_packet *packet = (void *)ts->xfer_buf;
0182     size_t len = count * sizeof(*data);
0183     struct i2c_msg msg = {
0184         .addr   = ts->client->addr,
0185         .len    = len + sizeof(packet->header.len) +
0186                 sizeof(packet->header.addr),
0187         .buf    = &packet->header.len,
0188     };
0189     int ret;
0190 
0191     if (len > HIDEEP_NVM_PAGE_SIZE)
0192         return -EINVAL;
0193 
0194     packet->header.len = 0x80 | (count - 1);
0195     packet->header.addr = cpu_to_be32(addr);
0196     memcpy(packet->payload, data, len);
0197 
0198     ret = i2c_transfer(ts->client->adapter, &msg, 1);
0199     if (ret != 1)
0200         return ret < 0 ? ret : -EIO;
0201 
0202     return 0;
0203 }
0204 
0205 static int hideep_pgm_r_mem(struct hideep_ts *ts, u32 addr,
0206                 __be32 *data, size_t count)
0207 {
0208     struct pgm_packet *packet = (void *)ts->xfer_buf;
0209     size_t len = count * sizeof(*data);
0210     struct i2c_msg msg[] = {
0211         {
0212             .addr   = ts->client->addr,
0213             .len    = sizeof(packet->header.len) +
0214                     sizeof(packet->header.addr),
0215             .buf    = &packet->header.len,
0216         },
0217         {
0218             .addr   = ts->client->addr,
0219             .flags  = I2C_M_RD,
0220             .len    = len,
0221             .buf    = (u8 *)data,
0222         },
0223     };
0224     int ret;
0225 
0226     if (len > HIDEEP_NVM_PAGE_SIZE)
0227         return -EINVAL;
0228 
0229     packet->header.len = count - 1;
0230     packet->header.addr = cpu_to_be32(addr);
0231 
0232     ret = i2c_transfer(ts->client->adapter, msg, ARRAY_SIZE(msg));
0233     if (ret != ARRAY_SIZE(msg))
0234         return ret < 0 ? ret : -EIO;
0235 
0236     return 0;
0237 }
0238 
0239 static int hideep_pgm_r_reg(struct hideep_ts *ts, u32 addr, u32 *val)
0240 {
0241     __be32 data;
0242     int error;
0243 
0244     error = hideep_pgm_r_mem(ts, addr, &data, 1);
0245     if (error) {
0246         dev_err(&ts->client->dev,
0247             "read of register %#08x failed: %d\n",
0248             addr, error);
0249         return error;
0250     }
0251 
0252     *val = be32_to_cpu(data);
0253     return 0;
0254 }
0255 
0256 static int hideep_pgm_w_reg(struct hideep_ts *ts, u32 addr, u32 val)
0257 {
0258     __be32 data = cpu_to_be32(val);
0259     int error;
0260 
0261     error = hideep_pgm_w_mem(ts, addr, &data, 1);
0262     if (error) {
0263         dev_err(&ts->client->dev,
0264             "write to register %#08x (%#08x) failed: %d\n",
0265             addr, val, error);
0266         return error;
0267     }
0268 
0269     return 0;
0270 }
0271 
0272 #define SW_RESET_IN_PGM(clk)                    \
0273 {                               \
0274     hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CNT, (clk)); \
0275     hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x03);  \
0276     hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x01);  \
0277 }
0278 
0279 #define SET_FLASH_PIO(ce)                   \
0280     hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON,          \
0281              0x01 | ((ce) << 1))
0282 
0283 #define SET_PIO_SIG(x, y)                   \
0284     hideep_pgm_w_reg(ts, HIDEEP_FLASH_PIO_SIG + (x), (y))
0285 
0286 #define SET_FLASH_HWCONTROL()                   \
0287     hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, 0x00)
0288 
0289 #define NVM_W_SFR(x, y)                     \
0290 {                               \
0291     SET_FLASH_PIO(1);                   \
0292     SET_PIO_SIG(x, y);                  \
0293     SET_FLASH_PIO(0);                   \
0294 }
0295 
0296 static void hideep_pgm_set(struct hideep_ts *ts)
0297 {
0298     hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x00);
0299     hideep_pgm_w_reg(ts, HIDEEP_SYSCON_SPC_CON, 0x00);
0300     hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_ENA, 0xFF);
0301     hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_CON, 0x01);
0302     hideep_pgm_w_reg(ts, HIDEEP_SYSCON_PWR_CON, 0x01);
0303     hideep_pgm_w_reg(ts, HIDEEP_FLASH_TIM, 0x03);
0304     hideep_pgm_w_reg(ts, HIDEEP_FLASH_CACHE_CFG, 0x00);
0305 }
0306 
0307 static int hideep_pgm_get_pattern(struct hideep_ts *ts, u32 *pattern)
0308 {
0309     u16 p1 = 0xAF39;
0310     u16 p2 = 0xDF9D;
0311     int error;
0312 
0313     error = regmap_bulk_write(ts->reg, p1, &p2, 1);
0314     if (error) {
0315         dev_err(&ts->client->dev,
0316             "%s: regmap_bulk_write() failed with %d\n",
0317             __func__, error);
0318         return error;
0319     }
0320 
0321     usleep_range(1000, 1100);
0322 
0323     /* flush invalid Tx load register */
0324     error = hideep_pgm_w_reg(ts, HIDEEP_ESI_TX_INVALID, 0x01);
0325     if (error)
0326         return error;
0327 
0328     error = hideep_pgm_r_reg(ts, HIDEEP_SYSCON_PGM_ID, pattern);
0329     if (error)
0330         return error;
0331 
0332     return 0;
0333 }
0334 
0335 static int hideep_enter_pgm(struct hideep_ts *ts)
0336 {
0337     int retry_count = 10;
0338     u32 pattern;
0339     int error;
0340 
0341     while (retry_count--) {
0342         error = hideep_pgm_get_pattern(ts, &pattern);
0343         if (error) {
0344             dev_err(&ts->client->dev,
0345                 "hideep_pgm_get_pattern failed: %d\n", error);
0346         } else if (pattern != 0x39AF9DDF) {
0347             dev_err(&ts->client->dev, "%s: bad pattern: %#08x\n",
0348                 __func__, pattern);
0349         } else {
0350             dev_dbg(&ts->client->dev, "found magic code");
0351 
0352             hideep_pgm_set(ts);
0353             usleep_range(1000, 1100);
0354 
0355             return 0;
0356         }
0357     }
0358 
0359     dev_err(&ts->client->dev, "failed to  enter pgm mode\n");
0360     SW_RESET_IN_PGM(1000);
0361     return -EIO;
0362 }
0363 
0364 static int hideep_nvm_unlock(struct hideep_ts *ts)
0365 {
0366     u32 unmask_code;
0367     int error;
0368 
0369     hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_RPAGE);
0370     error = hideep_pgm_r_reg(ts, 0x0000000C, &unmask_code);
0371     hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
0372     if (error)
0373         return error;
0374 
0375     /* make it unprotected code */
0376     unmask_code &= ~HIDEEP_PROT_MODE;
0377 
0378     /* compare unmask code */
0379     if (unmask_code != ts->nvm_mask)
0380         dev_warn(&ts->client->dev,
0381              "read mask code different %#08x vs %#08x",
0382              unmask_code, ts->nvm_mask);
0383 
0384     hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_WPAGE);
0385     SET_FLASH_PIO(0);
0386 
0387     NVM_W_SFR(HIDEEP_NVM_MASK_OFS, ts->nvm_mask);
0388     SET_FLASH_HWCONTROL();
0389     hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
0390 
0391     return 0;
0392 }
0393 
0394 static int hideep_check_status(struct hideep_ts *ts)
0395 {
0396     int time_out = 100;
0397     int status;
0398     int error;
0399 
0400     while (time_out--) {
0401         error = hideep_pgm_r_reg(ts, HIDEEP_FLASH_STA, &status);
0402         if (!error && status)
0403             return 0;
0404 
0405         usleep_range(1000, 1100);
0406     }
0407 
0408     return -ETIMEDOUT;
0409 }
0410 
0411 static int hideep_program_page(struct hideep_ts *ts, u32 addr,
0412                    const __be32 *ucode, size_t xfer_count)
0413 {
0414     u32 val;
0415     int error;
0416 
0417     error = hideep_check_status(ts);
0418     if (error)
0419         return -EBUSY;
0420 
0421     addr &= ~(HIDEEP_NVM_PAGE_SIZE - 1);
0422 
0423     SET_FLASH_PIO(0);
0424     SET_FLASH_PIO(1);
0425 
0426     /* erase page */
0427     SET_PIO_SIG(HIDEEP_PERASE | addr, 0xFFFFFFFF);
0428 
0429     SET_FLASH_PIO(0);
0430 
0431     error = hideep_check_status(ts);
0432     if (error)
0433         return -EBUSY;
0434 
0435     /* write page */
0436     SET_FLASH_PIO(1);
0437 
0438     val = be32_to_cpu(ucode[0]);
0439     SET_PIO_SIG(HIDEEP_WRONLY | addr, val);
0440 
0441     hideep_pgm_w_mem(ts, HIDEEP_FLASH_PIO_SIG | HIDEEP_WRONLY,
0442              ucode, xfer_count);
0443 
0444     val = be32_to_cpu(ucode[xfer_count - 1]);
0445     SET_PIO_SIG(124, val);
0446 
0447     SET_FLASH_PIO(0);
0448 
0449     usleep_range(1000, 1100);
0450 
0451     error = hideep_check_status(ts);
0452     if (error)
0453         return -EBUSY;
0454 
0455     SET_FLASH_HWCONTROL();
0456 
0457     return 0;
0458 }
0459 
0460 static int hideep_program_nvm(struct hideep_ts *ts,
0461                   const __be32 *ucode, size_t ucode_len)
0462 {
0463     struct pgm_packet *packet_r = (void *)ts->xfer_buf;
0464     __be32 *current_ucode = packet_r->payload;
0465     size_t xfer_len;
0466     size_t xfer_count;
0467     u32 addr = 0;
0468     int error;
0469 
0470        error = hideep_nvm_unlock(ts);
0471        if (error)
0472                return error;
0473 
0474     while (ucode_len > 0) {
0475         xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
0476         xfer_count = xfer_len / sizeof(*ucode);
0477 
0478         error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
0479                      current_ucode, xfer_count);
0480         if (error) {
0481             dev_err(&ts->client->dev,
0482                 "%s: failed to read page at offset %#08x: %d\n",
0483                 __func__, addr, error);
0484             return error;
0485         }
0486 
0487         /* See if the page needs updating */
0488         if (memcmp(ucode, current_ucode, xfer_len)) {
0489             error = hideep_program_page(ts, addr,
0490                             ucode, xfer_count);
0491             if (error) {
0492                 dev_err(&ts->client->dev,
0493                     "%s: iwrite failure @%#08x: %d\n",
0494                     __func__, addr, error);
0495                 return error;
0496             }
0497 
0498             usleep_range(1000, 1100);
0499         }
0500 
0501         ucode += xfer_count;
0502         addr += xfer_len;
0503         ucode_len -= xfer_len;
0504     }
0505 
0506     return 0;
0507 }
0508 
0509 static int hideep_verify_nvm(struct hideep_ts *ts,
0510                  const __be32 *ucode, size_t ucode_len)
0511 {
0512     struct pgm_packet *packet_r = (void *)ts->xfer_buf;
0513     __be32 *current_ucode = packet_r->payload;
0514     size_t xfer_len;
0515     size_t xfer_count;
0516     u32 addr = 0;
0517     int i;
0518     int error;
0519 
0520     while (ucode_len > 0) {
0521         xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
0522         xfer_count = xfer_len / sizeof(*ucode);
0523 
0524         error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
0525                      current_ucode, xfer_count);
0526         if (error) {
0527             dev_err(&ts->client->dev,
0528                 "%s: failed to read page at offset %#08x: %d\n",
0529                 __func__, addr, error);
0530             return error;
0531         }
0532 
0533         if (memcmp(ucode, current_ucode, xfer_len)) {
0534             const u8 *ucode_bytes = (const u8 *)ucode;
0535             const u8 *current_bytes = (const u8 *)current_ucode;
0536 
0537             for (i = 0; i < xfer_len; i++)
0538                 if (ucode_bytes[i] != current_bytes[i])
0539                     dev_err(&ts->client->dev,
0540                         "%s: mismatch @%#08x: (%#02x vs %#02x)\n",
0541                         __func__, addr + i,
0542                         ucode_bytes[i],
0543                         current_bytes[i]);
0544 
0545             return -EIO;
0546         }
0547 
0548         ucode += xfer_count;
0549         addr += xfer_len;
0550         ucode_len -= xfer_len;
0551     }
0552 
0553     return 0;
0554 }
0555 
0556 static int hideep_load_dwz(struct hideep_ts *ts)
0557 {
0558     u16 product_code;
0559     int error;
0560 
0561     error = hideep_enter_pgm(ts);
0562     if (error)
0563         return error;
0564 
0565     msleep(50);
0566 
0567     error = hideep_pgm_r_mem(ts, HIDEEP_DWZ_INFO,
0568                  (void *)&ts->dwz_info,
0569                  sizeof(ts->dwz_info) / sizeof(__be32));
0570 
0571     SW_RESET_IN_PGM(10);
0572     msleep(50);
0573 
0574     if (error) {
0575         dev_err(&ts->client->dev,
0576             "failed to fetch DWZ data: %d\n", error);
0577         return error;
0578     }
0579 
0580     product_code = be16_to_cpu(ts->dwz_info.product_code);
0581 
0582     switch (product_code & 0xF0) {
0583     case 0x40:
0584         dev_dbg(&ts->client->dev, "used crimson IC");
0585         ts->fw_size = 1024 * 48;
0586         ts->nvm_mask = 0x00310000;
0587         break;
0588     case 0x60:
0589         dev_dbg(&ts->client->dev, "used lime IC");
0590         ts->fw_size = 1024 * 64;
0591         ts->nvm_mask = 0x0030027B;
0592         break;
0593     default:
0594         dev_err(&ts->client->dev, "product code is wrong: %#04x",
0595             product_code);
0596         return -EINVAL;
0597     }
0598 
0599     dev_dbg(&ts->client->dev, "firmware release version: %#04x",
0600         be16_to_cpu(ts->dwz_info.release_ver));
0601 
0602     return 0;
0603 }
0604 
0605 static int hideep_flash_firmware(struct hideep_ts *ts,
0606                  const __be32 *ucode, size_t ucode_len)
0607 {
0608     int retry_cnt = 3;
0609     int error;
0610 
0611     while (retry_cnt--) {
0612         error = hideep_program_nvm(ts, ucode, ucode_len);
0613         if (!error) {
0614             error = hideep_verify_nvm(ts, ucode, ucode_len);
0615             if (!error)
0616                 return 0;
0617         }
0618     }
0619 
0620     return error;
0621 }
0622 
0623 static int hideep_update_firmware(struct hideep_ts *ts,
0624                   const __be32 *ucode, size_t ucode_len)
0625 {
0626     int error, error2;
0627 
0628     dev_dbg(&ts->client->dev, "starting firmware update");
0629 
0630     /* enter program mode */
0631     error = hideep_enter_pgm(ts);
0632     if (error)
0633         return error;
0634 
0635     error = hideep_flash_firmware(ts, ucode, ucode_len);
0636     if (error)
0637         dev_err(&ts->client->dev,
0638             "firmware update failed: %d\n", error);
0639     else
0640         dev_dbg(&ts->client->dev, "firmware updated successfully\n");
0641 
0642     SW_RESET_IN_PGM(1000);
0643 
0644     error2 = hideep_load_dwz(ts);
0645     if (error2)
0646         dev_err(&ts->client->dev,
0647             "failed to load dwz after firmware update: %d\n",
0648             error2);
0649 
0650     return error ?: error2;
0651 }
0652 
0653 static int hideep_power_on(struct hideep_ts *ts)
0654 {
0655     int error = 0;
0656 
0657     error = regulator_enable(ts->vcc_vdd);
0658     if (error)
0659         dev_err(&ts->client->dev,
0660             "failed to enable 'vdd' regulator: %d", error);
0661 
0662     usleep_range(999, 1000);
0663 
0664     error = regulator_enable(ts->vcc_vid);
0665     if (error)
0666         dev_err(&ts->client->dev,
0667             "failed to enable 'vcc_vid' regulator: %d",
0668             error);
0669 
0670     msleep(30);
0671 
0672     if (ts->reset_gpio) {
0673         gpiod_set_value_cansleep(ts->reset_gpio, 0);
0674     } else {
0675         error = regmap_write(ts->reg, HIDEEP_RESET_CMD, 0x01);
0676         if (error)
0677             dev_err(&ts->client->dev,
0678                 "failed to send 'reset' command: %d\n", error);
0679     }
0680 
0681     msleep(50);
0682 
0683     return error;
0684 }
0685 
0686 static void hideep_power_off(void *data)
0687 {
0688     struct hideep_ts *ts = data;
0689 
0690     if (ts->reset_gpio)
0691         gpiod_set_value(ts->reset_gpio, 1);
0692 
0693     regulator_disable(ts->vcc_vid);
0694     regulator_disable(ts->vcc_vdd);
0695 }
0696 
0697 #define __GET_MT_TOOL_TYPE(type) ((type) == 0x01 ? MT_TOOL_FINGER : MT_TOOL_PEN)
0698 
0699 static void hideep_report_slot(struct input_dev *input,
0700                    const struct hideep_event *event)
0701 {
0702     input_mt_slot(input, event->index & 0x0f);
0703     input_mt_report_slot_state(input,
0704                    __GET_MT_TOOL_TYPE(event->type),
0705                    !(event->flag & HIDEEP_MT_RELEASED));
0706     if (!(event->flag & HIDEEP_MT_RELEASED)) {
0707         input_report_abs(input, ABS_MT_POSITION_X,
0708                  le16_to_cpup(&event->x));
0709         input_report_abs(input, ABS_MT_POSITION_Y,
0710                  le16_to_cpup(&event->y));
0711         input_report_abs(input, ABS_MT_PRESSURE,
0712                  le16_to_cpup(&event->z));
0713         input_report_abs(input, ABS_MT_TOUCH_MAJOR, event->w);
0714     }
0715 }
0716 
0717 static void hideep_parse_and_report(struct hideep_ts *ts)
0718 {
0719     const struct hideep_event *events =
0720             (void *)&ts->xfer_buf[HIDEEP_TOUCH_EVENT_INDEX];
0721     const u8 *keys = &ts->xfer_buf[HIDEEP_KEY_EVENT_INDEX];
0722     int touch_count = ts->xfer_buf[0];
0723     int key_count = ts->xfer_buf[1] & 0x0f;
0724     int lpm_count = ts->xfer_buf[1] & 0xf0;
0725     int i;
0726 
0727     /* get touch event count */
0728     dev_dbg(&ts->client->dev, "mt = %d, key = %d, lpm = %02x",
0729         touch_count, key_count, lpm_count);
0730 
0731     touch_count = min(touch_count, HIDEEP_MT_MAX);
0732     for (i = 0; i < touch_count; i++)
0733         hideep_report_slot(ts->input_dev, events + i);
0734 
0735     key_count = min(key_count, HIDEEP_KEY_MAX);
0736     for (i = 0; i < key_count; i++) {
0737         u8 key_data = keys[i * 2];
0738 
0739         input_report_key(ts->input_dev,
0740                  ts->key_codes[key_data & HIDEEP_KEY_IDX_MASK],
0741                  key_data & HIDEEP_KEY_PRESSED_MASK);
0742     }
0743 
0744     input_mt_sync_frame(ts->input_dev);
0745     input_sync(ts->input_dev);
0746 }
0747 
0748 static irqreturn_t hideep_irq(int irq, void *handle)
0749 {
0750     struct hideep_ts *ts = handle;
0751     int error;
0752 
0753     BUILD_BUG_ON(HIDEEP_MAX_EVENT > HIDEEP_XFER_BUF_SIZE);
0754 
0755     error = regmap_bulk_read(ts->reg, HIDEEP_EVENT_ADDR,
0756                  ts->xfer_buf, HIDEEP_MAX_EVENT / 2);
0757     if (error) {
0758         dev_err(&ts->client->dev, "failed to read events: %d\n", error);
0759         goto out;
0760     }
0761 
0762     hideep_parse_and_report(ts);
0763 
0764 out:
0765     return IRQ_HANDLED;
0766 }
0767 
0768 static int hideep_get_axis_info(struct hideep_ts *ts)
0769 {
0770     __le16 val[2];
0771     int error;
0772 
0773     error = regmap_bulk_read(ts->reg, 0x28, val, ARRAY_SIZE(val));
0774     if (error)
0775         return error;
0776 
0777     ts->prop.max_x = le16_to_cpup(val);
0778     ts->prop.max_y = le16_to_cpup(val + 1);
0779 
0780     dev_dbg(&ts->client->dev, "X: %d, Y: %d",
0781         ts->prop.max_x, ts->prop.max_y);
0782 
0783     return 0;
0784 }
0785 
0786 static int hideep_init_input(struct hideep_ts *ts)
0787 {
0788     struct device *dev = &ts->client->dev;
0789     int i;
0790     int error;
0791 
0792     ts->input_dev = devm_input_allocate_device(dev);
0793     if (!ts->input_dev) {
0794         dev_err(dev, "failed to allocate input device\n");
0795         return -ENOMEM;
0796     }
0797 
0798     ts->input_dev->name = HIDEEP_TS_NAME;
0799     ts->input_dev->id.bustype = BUS_I2C;
0800     input_set_drvdata(ts->input_dev, ts);
0801 
0802     input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_X);
0803     input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_Y);
0804     input_set_abs_params(ts->input_dev, ABS_MT_PRESSURE, 0, 65535, 0, 0);
0805     input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
0806     input_set_abs_params(ts->input_dev, ABS_MT_TOOL_TYPE,
0807                  0, MT_TOOL_MAX, 0, 0);
0808     touchscreen_parse_properties(ts->input_dev, true, &ts->prop);
0809 
0810     if (ts->prop.max_x == 0 || ts->prop.max_y == 0) {
0811         error = hideep_get_axis_info(ts);
0812         if (error)
0813             return error;
0814     }
0815 
0816     error = input_mt_init_slots(ts->input_dev, HIDEEP_MT_MAX,
0817                     INPUT_MT_DIRECT);
0818     if (error)
0819         return error;
0820 
0821     ts->key_num = device_property_count_u32(dev, "linux,keycodes");
0822     if (ts->key_num > HIDEEP_KEY_MAX) {
0823         dev_err(dev, "too many keys defined: %d\n",
0824             ts->key_num);
0825         return -EINVAL;
0826     }
0827 
0828     if (ts->key_num <= 0) {
0829         dev_dbg(dev,
0830             "missing or malformed 'linux,keycodes' property\n");
0831     } else {
0832         error = device_property_read_u32_array(dev, "linux,keycodes",
0833                                ts->key_codes,
0834                                ts->key_num);
0835         if (error) {
0836             dev_dbg(dev, "failed to read keymap: %d", error);
0837             return error;
0838         }
0839 
0840         if (ts->key_num) {
0841             ts->input_dev->keycode = ts->key_codes;
0842             ts->input_dev->keycodesize = sizeof(ts->key_codes[0]);
0843             ts->input_dev->keycodemax = ts->key_num;
0844 
0845             for (i = 0; i < ts->key_num; i++)
0846                 input_set_capability(ts->input_dev, EV_KEY,
0847                     ts->key_codes[i]);
0848         }
0849     }
0850 
0851     error = input_register_device(ts->input_dev);
0852     if (error) {
0853         dev_err(dev, "failed to register input device: %d", error);
0854         return error;
0855     }
0856 
0857     return 0;
0858 }
0859 
0860 static ssize_t hideep_update_fw(struct device *dev,
0861                 struct device_attribute *attr,
0862                 const char *buf, size_t count)
0863 {
0864     struct i2c_client *client = to_i2c_client(dev);
0865     struct hideep_ts *ts = i2c_get_clientdata(client);
0866     const struct firmware *fw_entry;
0867     char *fw_name;
0868     int mode;
0869     int error;
0870 
0871     error = kstrtoint(buf, 0, &mode);
0872     if (error)
0873         return error;
0874 
0875     fw_name = kasprintf(GFP_KERNEL, "hideep_ts_%04x.bin",
0876                 be16_to_cpu(ts->dwz_info.product_id));
0877     if (!fw_name)
0878         return -ENOMEM;
0879 
0880     error = request_firmware(&fw_entry, fw_name, dev);
0881     if (error) {
0882         dev_err(dev, "failed to request firmware %s: %d",
0883             fw_name, error);
0884         goto out_free_fw_name;
0885     }
0886 
0887     if (fw_entry->size % sizeof(__be32)) {
0888         dev_err(dev, "invalid firmware size %zu\n", fw_entry->size);
0889         error = -EINVAL;
0890         goto out_release_fw;
0891     }
0892 
0893     if (fw_entry->size > ts->fw_size) {
0894         dev_err(dev, "fw size (%zu) is too big (memory size %d)\n",
0895             fw_entry->size, ts->fw_size);
0896         error = -EFBIG;
0897         goto out_release_fw;
0898     }
0899 
0900     mutex_lock(&ts->dev_mutex);
0901     disable_irq(client->irq);
0902 
0903     error = hideep_update_firmware(ts, (const __be32 *)fw_entry->data,
0904                        fw_entry->size);
0905 
0906     enable_irq(client->irq);
0907     mutex_unlock(&ts->dev_mutex);
0908 
0909 out_release_fw:
0910     release_firmware(fw_entry);
0911 out_free_fw_name:
0912     kfree(fw_name);
0913 
0914     return error ?: count;
0915 }
0916 
0917 static ssize_t hideep_fw_version_show(struct device *dev,
0918                       struct device_attribute *attr, char *buf)
0919 {
0920     struct i2c_client *client = to_i2c_client(dev);
0921     struct hideep_ts *ts = i2c_get_clientdata(client);
0922     ssize_t len;
0923 
0924     mutex_lock(&ts->dev_mutex);
0925     len = scnprintf(buf, PAGE_SIZE, "%04x\n",
0926             be16_to_cpu(ts->dwz_info.release_ver));
0927     mutex_unlock(&ts->dev_mutex);
0928 
0929     return len;
0930 }
0931 
0932 static ssize_t hideep_product_id_show(struct device *dev,
0933                       struct device_attribute *attr, char *buf)
0934 {
0935     struct i2c_client *client = to_i2c_client(dev);
0936     struct hideep_ts *ts = i2c_get_clientdata(client);
0937     ssize_t len;
0938 
0939     mutex_lock(&ts->dev_mutex);
0940     len = scnprintf(buf, PAGE_SIZE, "%04x\n",
0941             be16_to_cpu(ts->dwz_info.product_id));
0942     mutex_unlock(&ts->dev_mutex);
0943 
0944     return len;
0945 }
0946 
0947 static DEVICE_ATTR(version, 0664, hideep_fw_version_show, NULL);
0948 static DEVICE_ATTR(product_id, 0664, hideep_product_id_show, NULL);
0949 static DEVICE_ATTR(update_fw, 0664, NULL, hideep_update_fw);
0950 
0951 static struct attribute *hideep_ts_sysfs_entries[] = {
0952     &dev_attr_version.attr,
0953     &dev_attr_product_id.attr,
0954     &dev_attr_update_fw.attr,
0955     NULL,
0956 };
0957 
0958 static const struct attribute_group hideep_ts_attr_group = {
0959     .attrs = hideep_ts_sysfs_entries,
0960 };
0961 
0962 static int __maybe_unused hideep_suspend(struct device *dev)
0963 {
0964     struct i2c_client *client = to_i2c_client(dev);
0965     struct hideep_ts *ts = i2c_get_clientdata(client);
0966 
0967     disable_irq(client->irq);
0968     hideep_power_off(ts);
0969 
0970     return 0;
0971 }
0972 
0973 static int __maybe_unused hideep_resume(struct device *dev)
0974 {
0975     struct i2c_client *client = to_i2c_client(dev);
0976     struct hideep_ts *ts = i2c_get_clientdata(client);
0977     int error;
0978 
0979     error = hideep_power_on(ts);
0980     if (error) {
0981         dev_err(&client->dev, "power on failed");
0982         return error;
0983     }
0984 
0985     enable_irq(client->irq);
0986 
0987     return 0;
0988 }
0989 
0990 static SIMPLE_DEV_PM_OPS(hideep_pm_ops, hideep_suspend, hideep_resume);
0991 
0992 static const struct regmap_config hideep_regmap_config = {
0993     .reg_bits = 16,
0994     .reg_format_endian = REGMAP_ENDIAN_LITTLE,
0995     .val_bits = 16,
0996     .val_format_endian = REGMAP_ENDIAN_LITTLE,
0997     .max_register = 0xffff,
0998 };
0999 
1000 static int hideep_probe(struct i2c_client *client,
1001             const struct i2c_device_id *id)
1002 {
1003     struct hideep_ts *ts;
1004     int error;
1005 
1006     /* check i2c bus */
1007     if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1008         dev_err(&client->dev, "check i2c device error");
1009         return -ENODEV;
1010     }
1011 
1012     if (client->irq <= 0) {
1013         dev_err(&client->dev, "missing irq: %d\n", client->irq);
1014         return -EINVAL;
1015     }
1016 
1017     ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
1018     if (!ts)
1019         return -ENOMEM;
1020 
1021     ts->client = client;
1022     i2c_set_clientdata(client, ts);
1023     mutex_init(&ts->dev_mutex);
1024 
1025     ts->reg = devm_regmap_init_i2c(client, &hideep_regmap_config);
1026     if (IS_ERR(ts->reg)) {
1027         error = PTR_ERR(ts->reg);
1028         dev_err(&client->dev,
1029             "failed to initialize regmap: %d\n", error);
1030         return error;
1031     }
1032 
1033     ts->vcc_vdd = devm_regulator_get(&client->dev, "vdd");
1034     if (IS_ERR(ts->vcc_vdd))
1035         return PTR_ERR(ts->vcc_vdd);
1036 
1037     ts->vcc_vid = devm_regulator_get(&client->dev, "vid");
1038     if (IS_ERR(ts->vcc_vid))
1039         return PTR_ERR(ts->vcc_vid);
1040 
1041     ts->reset_gpio = devm_gpiod_get_optional(&client->dev,
1042                          "reset", GPIOD_OUT_HIGH);
1043     if (IS_ERR(ts->reset_gpio))
1044         return PTR_ERR(ts->reset_gpio);
1045 
1046     error = hideep_power_on(ts);
1047     if (error) {
1048         dev_err(&client->dev, "power on failed: %d\n", error);
1049         return error;
1050     }
1051 
1052     error = devm_add_action_or_reset(&client->dev, hideep_power_off, ts);
1053     if (error)
1054         return error;
1055 
1056     error = hideep_load_dwz(ts);
1057     if (error) {
1058         dev_err(&client->dev, "failed to load dwz: %d", error);
1059         return error;
1060     }
1061 
1062     error = hideep_init_input(ts);
1063     if (error)
1064         return error;
1065 
1066     error = devm_request_threaded_irq(&client->dev, client->irq,
1067                       NULL, hideep_irq, IRQF_ONESHOT,
1068                       client->name, ts);
1069     if (error) {
1070         dev_err(&client->dev, "failed to request irq %d: %d\n",
1071             client->irq, error);
1072         return error;
1073     }
1074 
1075     error = devm_device_add_group(&client->dev, &hideep_ts_attr_group);
1076     if (error) {
1077         dev_err(&client->dev,
1078             "failed to add sysfs attributes: %d\n", error);
1079         return error;
1080     }
1081 
1082     return 0;
1083 }
1084 
1085 static const struct i2c_device_id hideep_i2c_id[] = {
1086     { HIDEEP_I2C_NAME, 0 },
1087     { }
1088 };
1089 MODULE_DEVICE_TABLE(i2c, hideep_i2c_id);
1090 
1091 #ifdef CONFIG_ACPI
1092 static const struct acpi_device_id hideep_acpi_id[] = {
1093     { "HIDP0001", 0 },
1094     { }
1095 };
1096 MODULE_DEVICE_TABLE(acpi, hideep_acpi_id);
1097 #endif
1098 
1099 #ifdef CONFIG_OF
1100 static const struct of_device_id hideep_match_table[] = {
1101     { .compatible = "hideep,hideep-ts" },
1102     { }
1103 };
1104 MODULE_DEVICE_TABLE(of, hideep_match_table);
1105 #endif
1106 
1107 static struct i2c_driver hideep_driver = {
1108     .driver = {
1109         .name           = HIDEEP_I2C_NAME,
1110         .of_match_table     = of_match_ptr(hideep_match_table),
1111         .acpi_match_table   = ACPI_PTR(hideep_acpi_id),
1112         .pm         = &hideep_pm_ops,
1113     },
1114     .id_table   = hideep_i2c_id,
1115     .probe      = hideep_probe,
1116 };
1117 
1118 module_i2c_driver(hideep_driver);
1119 
1120 MODULE_DESCRIPTION("Driver for HiDeep Touchscreen Controller");
1121 MODULE_AUTHOR("anthony.kim@hideep.com");
1122 MODULE_LICENSE("GPL v2");
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