input/serio/i8042-snirm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 #ifndef _I8042_SNIRM_H
0003 #define _I8042_SNIRM_H
0004
0005 #include <asm/sni.h>
0006
0007
0008 /*
0009  * Names.
0010  */
0011
0012 #define I8042_KBD_PHYS_DESC "onboard/serio0"
0013 #define I8042_AUX_PHYS_DESC "onboard/serio1"
0014 #define I8042_MUX_PHYS_DESC "onboard/serio%d"
0015
0016 /*
0017  * IRQs.
0018  */
0019 static int i8042_kbd_irq;
0020 static int i8042_aux_irq;
0021 #define I8042_KBD_IRQ i8042_kbd_irq
0022 #define I8042_AUX_IRQ i8042_aux_irq
0023
0024 static void __iomem *kbd_iobase;
0025
0026 #define I8042_COMMAND_REG   (kbd_iobase + 0x64UL)
0027 #define I8042_DATA_REG      (kbd_iobase + 0x60UL)
0028
0029 static inline int i8042_read_data(void)
0030 {
0031     return readb(kbd_iobase + 0x60UL);
0032 }
0033
0034 static inline int i8042_read_status(void)
0035 {
0036     return readb(kbd_iobase + 0x64UL);
0037 }
0038
0039 static inline void i8042_write_data(int val)
0040 {
0041     writeb(val, kbd_iobase + 0x60UL);
0042 }
0043
0044 static inline void i8042_write_command(int val)
0045 {
0046     writeb(val, kbd_iobase + 0x64UL);
0047 }
0048 static inline int i8042_platform_init(void)
0049 {
0050     /* RM200 is strange ... */
0051     if (sni_brd_type == SNI_BRD_RM200) {
0052         kbd_iobase = ioremap(0x16000000, 4);
0053         i8042_kbd_irq = 33;
0054         i8042_aux_irq = 44;
0055     } else {
0056         kbd_iobase = ioremap(0x14000000, 4);
0057         i8042_kbd_irq = 1;
0058         i8042_aux_irq = 12;
0059     }
0060     if (!kbd_iobase)
0061         return -ENOMEM;
0062
0063     return 0;
0064 }
0065
0066 static inline void i8042_platform_exit(void)
0067 {
0068
0069 }
0070
0071 #endif /* _I8042_SNIRM_H */