0001
0002 #ifndef _I8042_IO_H
0003 #define _I8042_IO_H
0004
0005
0006
0007
0008
0009
0010 #define I8042_KBD_PHYS_DESC "isa0060/serio0"
0011 #define I8042_AUX_PHYS_DESC "isa0060/serio1"
0012 #define I8042_MUX_PHYS_DESC "isa0060/serio%d"
0013
0014
0015
0016
0017
0018 #ifdef __alpha__
0019 # define I8042_KBD_IRQ 1
0020 # define I8042_AUX_IRQ (RTC_PORT(0) == 0x170 ? 9 : 12)
0021 #elif defined(__arm__)
0022
0023 #include <asm/irq.h>
0024 #elif defined(CONFIG_PPC)
0025 extern int of_i8042_kbd_irq;
0026 extern int of_i8042_aux_irq;
0027 # define I8042_KBD_IRQ of_i8042_kbd_irq
0028 # define I8042_AUX_IRQ of_i8042_aux_irq
0029 #else
0030 # define I8042_KBD_IRQ 1
0031 # define I8042_AUX_IRQ 12
0032 #endif
0033
0034
0035
0036
0037
0038
0039 #define I8042_COMMAND_REG 0x64
0040 #define I8042_STATUS_REG 0x64
0041 #define I8042_DATA_REG 0x60
0042
0043 static inline int i8042_read_data(void)
0044 {
0045 return inb(I8042_DATA_REG);
0046 }
0047
0048 static inline int i8042_read_status(void)
0049 {
0050 return inb(I8042_STATUS_REG);
0051 }
0052
0053 static inline void i8042_write_data(int val)
0054 {
0055 outb(val, I8042_DATA_REG);
0056 }
0057
0058 static inline void i8042_write_command(int val)
0059 {
0060 outb(val, I8042_COMMAND_REG);
0061 }
0062
0063 static inline int i8042_platform_init(void)
0064 {
0065
0066
0067
0068
0069 #if defined(CONFIG_PPC)
0070 if (check_legacy_ioport(I8042_DATA_REG))
0071 return -ENODEV;
0072 #endif
0073 #if !defined(__sh__) && !defined(__alpha__)
0074 if (!request_region(I8042_DATA_REG, 16, "i8042"))
0075 return -EBUSY;
0076 #endif
0077
0078 i8042_reset = I8042_RESET_ALWAYS;
0079 return 0;
0080 }
0081
0082 static inline void i8042_platform_exit(void)
0083 {
0084 #if !defined(__sh__) && !defined(__alpha__)
0085 release_region(I8042_DATA_REG, 16);
0086 #endif
0087 }
0088
0089 #endif