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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2016, Zodiac Inflight Innovations
0004  * Copyright (c) 2007-2016, Synaptics Incorporated
0005  * Copyright (C) 2012 Alexandra Chin <alexandra.chin@tw.synaptics.com>
0006  * Copyright (C) 2012 Scott Lin <scott.lin@tw.synaptics.com>
0007  */
0008 
0009 #include <linux/bitops.h>
0010 #include <linux/kernel.h>
0011 #include <linux/rmi.h>
0012 #include <linux/firmware.h>
0013 #include <linux/delay.h>
0014 #include <linux/slab.h>
0015 #include <linux/jiffies.h>
0016 #include <asm/unaligned.h>
0017 
0018 #include "rmi_driver.h"
0019 #include "rmi_f34.h"
0020 
0021 static int rmi_f34v7_read_flash_status(struct f34_data *f34)
0022 {
0023     u8 status;
0024     u8 command;
0025     int ret;
0026 
0027     ret = rmi_read_block(f34->fn->rmi_dev,
0028             f34->fn->fd.data_base_addr + f34->v7.off.flash_status,
0029             &status,
0030             sizeof(status));
0031     if (ret < 0) {
0032         rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
0033             "%s: Error %d reading flash status\n", __func__, ret);
0034         return ret;
0035     }
0036 
0037     f34->v7.in_bl_mode = status >> 7;
0038     f34->v7.flash_status = status & 0x1f;
0039 
0040     if (f34->v7.flash_status != 0x00) {
0041         dev_err(&f34->fn->dev, "%s: status=%d, command=0x%02x\n",
0042             __func__, f34->v7.flash_status, f34->v7.command);
0043     }
0044 
0045     ret = rmi_read_block(f34->fn->rmi_dev,
0046             f34->fn->fd.data_base_addr + f34->v7.off.flash_cmd,
0047             &command,
0048             sizeof(command));
0049     if (ret < 0) {
0050         dev_err(&f34->fn->dev, "%s: Failed to read flash command\n",
0051             __func__);
0052         return ret;
0053     }
0054 
0055     f34->v7.command = command;
0056 
0057     return 0;
0058 }
0059 
0060 static int rmi_f34v7_wait_for_idle(struct f34_data *f34, int timeout_ms)
0061 {
0062     unsigned long timeout;
0063 
0064     timeout = msecs_to_jiffies(timeout_ms);
0065 
0066     if (!wait_for_completion_timeout(&f34->v7.cmd_done, timeout)) {
0067         dev_warn(&f34->fn->dev, "%s: Timed out waiting for idle status\n",
0068              __func__);
0069         return -ETIMEDOUT;
0070     }
0071 
0072     return 0;
0073 }
0074 
0075 static int rmi_f34v7_write_command_single_transaction(struct f34_data *f34,
0076                               u8 cmd)
0077 {
0078     int ret;
0079     u8 base;
0080     struct f34v7_data_1_5 data_1_5;
0081 
0082     base = f34->fn->fd.data_base_addr;
0083 
0084     memset(&data_1_5, 0, sizeof(data_1_5));
0085 
0086     switch (cmd) {
0087     case v7_CMD_ERASE_ALL:
0088         data_1_5.partition_id = CORE_CODE_PARTITION;
0089         data_1_5.command = CMD_V7_ERASE_AP;
0090         break;
0091     case v7_CMD_ERASE_UI_FIRMWARE:
0092         data_1_5.partition_id = CORE_CODE_PARTITION;
0093         data_1_5.command = CMD_V7_ERASE;
0094         break;
0095     case v7_CMD_ERASE_BL_CONFIG:
0096         data_1_5.partition_id = GLOBAL_PARAMETERS_PARTITION;
0097         data_1_5.command = CMD_V7_ERASE;
0098         break;
0099     case v7_CMD_ERASE_UI_CONFIG:
0100         data_1_5.partition_id = CORE_CONFIG_PARTITION;
0101         data_1_5.command = CMD_V7_ERASE;
0102         break;
0103     case v7_CMD_ERASE_DISP_CONFIG:
0104         data_1_5.partition_id = DISPLAY_CONFIG_PARTITION;
0105         data_1_5.command = CMD_V7_ERASE;
0106         break;
0107     case v7_CMD_ERASE_FLASH_CONFIG:
0108         data_1_5.partition_id = FLASH_CONFIG_PARTITION;
0109         data_1_5.command = CMD_V7_ERASE;
0110         break;
0111     case v7_CMD_ERASE_GUEST_CODE:
0112         data_1_5.partition_id = GUEST_CODE_PARTITION;
0113         data_1_5.command = CMD_V7_ERASE;
0114         break;
0115     case v7_CMD_ENABLE_FLASH_PROG:
0116         data_1_5.partition_id = BOOTLOADER_PARTITION;
0117         data_1_5.command = CMD_V7_ENTER_BL;
0118         break;
0119     }
0120 
0121     data_1_5.payload[0] = f34->bootloader_id[0];
0122     data_1_5.payload[1] = f34->bootloader_id[1];
0123 
0124     ret = rmi_write_block(f34->fn->rmi_dev,
0125             base + f34->v7.off.partition_id,
0126             &data_1_5, sizeof(data_1_5));
0127     if (ret < 0) {
0128         dev_err(&f34->fn->dev,
0129             "%s: Failed to write single transaction command\n",
0130             __func__);
0131         return ret;
0132     }
0133 
0134     return 0;
0135 }
0136 
0137 static int rmi_f34v7_write_command(struct f34_data *f34, u8 cmd)
0138 {
0139     int ret;
0140     u8 base;
0141     u8 command;
0142 
0143     base = f34->fn->fd.data_base_addr;
0144 
0145     switch (cmd) {
0146     case v7_CMD_WRITE_FW:
0147     case v7_CMD_WRITE_CONFIG:
0148     case v7_CMD_WRITE_GUEST_CODE:
0149         command = CMD_V7_WRITE;
0150         break;
0151     case v7_CMD_READ_CONFIG:
0152         command = CMD_V7_READ;
0153         break;
0154     case v7_CMD_ERASE_ALL:
0155         command = CMD_V7_ERASE_AP;
0156         break;
0157     case v7_CMD_ERASE_UI_FIRMWARE:
0158     case v7_CMD_ERASE_BL_CONFIG:
0159     case v7_CMD_ERASE_UI_CONFIG:
0160     case v7_CMD_ERASE_DISP_CONFIG:
0161     case v7_CMD_ERASE_FLASH_CONFIG:
0162     case v7_CMD_ERASE_GUEST_CODE:
0163         command = CMD_V7_ERASE;
0164         break;
0165     case v7_CMD_ENABLE_FLASH_PROG:
0166         command = CMD_V7_ENTER_BL;
0167         break;
0168     default:
0169         dev_err(&f34->fn->dev, "%s: Invalid command 0x%02x\n",
0170             __func__, cmd);
0171         return -EINVAL;
0172     }
0173 
0174     f34->v7.command = command;
0175 
0176     switch (cmd) {
0177     case v7_CMD_ERASE_ALL:
0178     case v7_CMD_ERASE_UI_FIRMWARE:
0179     case v7_CMD_ERASE_BL_CONFIG:
0180     case v7_CMD_ERASE_UI_CONFIG:
0181     case v7_CMD_ERASE_DISP_CONFIG:
0182     case v7_CMD_ERASE_FLASH_CONFIG:
0183     case v7_CMD_ERASE_GUEST_CODE:
0184     case v7_CMD_ENABLE_FLASH_PROG:
0185         ret = rmi_f34v7_write_command_single_transaction(f34, cmd);
0186         if (ret < 0)
0187             return ret;
0188         else
0189             return 0;
0190     default:
0191         break;
0192     }
0193 
0194     rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: writing cmd %02X\n",
0195         __func__, command);
0196 
0197     ret = rmi_write_block(f34->fn->rmi_dev,
0198             base + f34->v7.off.flash_cmd,
0199             &command, sizeof(command));
0200     if (ret < 0) {
0201         dev_err(&f34->fn->dev, "%s: Failed to write flash command\n",
0202             __func__);
0203         return ret;
0204     }
0205 
0206     return 0;
0207 }
0208 
0209 static int rmi_f34v7_write_partition_id(struct f34_data *f34, u8 cmd)
0210 {
0211     int ret;
0212     u8 base;
0213     u8 partition;
0214 
0215     base = f34->fn->fd.data_base_addr;
0216 
0217     switch (cmd) {
0218     case v7_CMD_WRITE_FW:
0219         partition = CORE_CODE_PARTITION;
0220         break;
0221     case v7_CMD_WRITE_CONFIG:
0222     case v7_CMD_READ_CONFIG:
0223         if (f34->v7.config_area == v7_UI_CONFIG_AREA)
0224             partition = CORE_CONFIG_PARTITION;
0225         else if (f34->v7.config_area == v7_DP_CONFIG_AREA)
0226             partition = DISPLAY_CONFIG_PARTITION;
0227         else if (f34->v7.config_area == v7_PM_CONFIG_AREA)
0228             partition = GUEST_SERIALIZATION_PARTITION;
0229         else if (f34->v7.config_area == v7_BL_CONFIG_AREA)
0230             partition = GLOBAL_PARAMETERS_PARTITION;
0231         else if (f34->v7.config_area == v7_FLASH_CONFIG_AREA)
0232             partition = FLASH_CONFIG_PARTITION;
0233         break;
0234     case v7_CMD_WRITE_GUEST_CODE:
0235         partition = GUEST_CODE_PARTITION;
0236         break;
0237     case v7_CMD_ERASE_ALL:
0238         partition = CORE_CODE_PARTITION;
0239         break;
0240     case v7_CMD_ERASE_BL_CONFIG:
0241         partition = GLOBAL_PARAMETERS_PARTITION;
0242         break;
0243     case v7_CMD_ERASE_UI_CONFIG:
0244         partition = CORE_CONFIG_PARTITION;
0245         break;
0246     case v7_CMD_ERASE_DISP_CONFIG:
0247         partition = DISPLAY_CONFIG_PARTITION;
0248         break;
0249     case v7_CMD_ERASE_FLASH_CONFIG:
0250         partition = FLASH_CONFIG_PARTITION;
0251         break;
0252     case v7_CMD_ERASE_GUEST_CODE:
0253         partition = GUEST_CODE_PARTITION;
0254         break;
0255     case v7_CMD_ENABLE_FLASH_PROG:
0256         partition = BOOTLOADER_PARTITION;
0257         break;
0258     default:
0259         dev_err(&f34->fn->dev, "%s: Invalid command 0x%02x\n",
0260             __func__, cmd);
0261         return -EINVAL;
0262     }
0263 
0264     ret = rmi_write_block(f34->fn->rmi_dev,
0265             base + f34->v7.off.partition_id,
0266             &partition, sizeof(partition));
0267     if (ret < 0) {
0268         dev_err(&f34->fn->dev, "%s: Failed to write partition ID\n",
0269             __func__);
0270         return ret;
0271     }
0272 
0273     return 0;
0274 }
0275 
0276 static int rmi_f34v7_read_partition_table(struct f34_data *f34)
0277 {
0278     int ret;
0279     unsigned long timeout;
0280     u8 base;
0281     __le16 length;
0282     u16 block_number = 0;
0283 
0284     base = f34->fn->fd.data_base_addr;
0285 
0286     f34->v7.config_area = v7_FLASH_CONFIG_AREA;
0287 
0288     ret = rmi_f34v7_write_partition_id(f34, v7_CMD_READ_CONFIG);
0289     if (ret < 0)
0290         return ret;
0291 
0292     ret = rmi_write_block(f34->fn->rmi_dev,
0293             base + f34->v7.off.block_number,
0294             &block_number, sizeof(block_number));
0295     if (ret < 0) {
0296         dev_err(&f34->fn->dev, "%s: Failed to write block number\n",
0297             __func__);
0298         return ret;
0299     }
0300 
0301     put_unaligned_le16(f34->v7.flash_config_length, &length);
0302 
0303     ret = rmi_write_block(f34->fn->rmi_dev,
0304             base + f34->v7.off.transfer_length,
0305             &length, sizeof(length));
0306     if (ret < 0) {
0307         dev_err(&f34->fn->dev, "%s: Failed to write transfer length\n",
0308             __func__);
0309         return ret;
0310     }
0311 
0312     init_completion(&f34->v7.cmd_done);
0313 
0314     ret = rmi_f34v7_write_command(f34, v7_CMD_READ_CONFIG);
0315     if (ret < 0) {
0316         dev_err(&f34->fn->dev, "%s: Failed to write command\n",
0317             __func__);
0318         return ret;
0319     }
0320 
0321     timeout = msecs_to_jiffies(F34_WRITE_WAIT_MS);
0322     while (time_before(jiffies, timeout)) {
0323         usleep_range(5000, 6000);
0324         rmi_f34v7_read_flash_status(f34);
0325 
0326         if (f34->v7.command == v7_CMD_IDLE &&
0327             f34->v7.flash_status == 0x00) {
0328             break;
0329         }
0330     }
0331 
0332     ret = rmi_read_block(f34->fn->rmi_dev,
0333             base + f34->v7.off.payload,
0334             f34->v7.read_config_buf,
0335             f34->v7.partition_table_bytes);
0336     if (ret < 0) {
0337         dev_err(&f34->fn->dev, "%s: Failed to read block data\n",
0338             __func__);
0339         return ret;
0340     }
0341 
0342     return 0;
0343 }
0344 
0345 static void rmi_f34v7_parse_partition_table(struct f34_data *f34,
0346                         const void *partition_table,
0347                         struct block_count *blkcount,
0348                         struct physical_address *phyaddr)
0349 {
0350     int i;
0351     int index;
0352     u16 partition_length;
0353     u16 physical_address;
0354     const struct partition_table *ptable;
0355 
0356     for (i = 0; i < f34->v7.partitions; i++) {
0357         index = i * 8 + 2;
0358         ptable = partition_table + index;
0359         partition_length = le16_to_cpu(ptable->partition_length);
0360         physical_address = le16_to_cpu(ptable->start_physical_address);
0361         rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
0362             "%s: Partition entry %d: %*ph\n",
0363             __func__, i, sizeof(struct partition_table), ptable);
0364         switch (ptable->partition_id & 0x1f) {
0365         case CORE_CODE_PARTITION:
0366             blkcount->ui_firmware = partition_length;
0367             phyaddr->ui_firmware = physical_address;
0368             rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
0369                 "%s: Core code block count: %d\n",
0370                 __func__, blkcount->ui_firmware);
0371             break;
0372         case CORE_CONFIG_PARTITION:
0373             blkcount->ui_config = partition_length;
0374             phyaddr->ui_config = physical_address;
0375             rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
0376                 "%s: Core config block count: %d\n",
0377                 __func__, blkcount->ui_config);
0378             break;
0379         case DISPLAY_CONFIG_PARTITION:
0380             blkcount->dp_config = partition_length;
0381             phyaddr->dp_config = physical_address;
0382             rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
0383                 "%s: Display config block count: %d\n",
0384                 __func__, blkcount->dp_config);
0385             break;
0386         case FLASH_CONFIG_PARTITION:
0387             blkcount->fl_config = partition_length;
0388             rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
0389                 "%s: Flash config block count: %d\n",
0390                 __func__, blkcount->fl_config);
0391             break;
0392         case GUEST_CODE_PARTITION:
0393             blkcount->guest_code = partition_length;
0394             phyaddr->guest_code = physical_address;
0395             rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
0396                 "%s: Guest code block count: %d\n",
0397                 __func__, blkcount->guest_code);
0398             break;
0399         case GUEST_SERIALIZATION_PARTITION:
0400             blkcount->pm_config = partition_length;
0401             rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
0402                 "%s: Guest serialization block count: %d\n",
0403                 __func__, blkcount->pm_config);
0404             break;
0405         case GLOBAL_PARAMETERS_PARTITION:
0406             blkcount->bl_config = partition_length;
0407             rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
0408                 "%s: Global parameters block count: %d\n",
0409                 __func__, blkcount->bl_config);
0410             break;
0411         case DEVICE_CONFIG_PARTITION:
0412             blkcount->lockdown = partition_length;
0413             rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
0414                 "%s: Device config block count: %d\n",
0415                 __func__, blkcount->lockdown);
0416             break;
0417         }
0418     }
0419 }
0420 
0421 static int rmi_f34v7_read_queries_bl_version(struct f34_data *f34)
0422 {
0423     int ret;
0424     u8 base;
0425     int offset;
0426     u8 query_0;
0427     struct f34v7_query_1_7 query_1_7;
0428 
0429     base = f34->fn->fd.query_base_addr;
0430 
0431     ret = rmi_read_block(f34->fn->rmi_dev,
0432             base,
0433             &query_0,
0434             sizeof(query_0));
0435     if (ret < 0) {
0436         dev_err(&f34->fn->dev,
0437             "%s: Failed to read query 0\n", __func__);
0438         return ret;
0439     }
0440 
0441     offset = (query_0 & 0x7) + 1;
0442 
0443     ret = rmi_read_block(f34->fn->rmi_dev,
0444             base + offset,
0445             &query_1_7,
0446             sizeof(query_1_7));
0447     if (ret < 0) {
0448         dev_err(&f34->fn->dev, "%s: Failed to read queries 1 to 7\n",
0449             __func__);
0450         return ret;
0451     }
0452 
0453     f34->bootloader_id[0] = query_1_7.bl_minor_revision;
0454     f34->bootloader_id[1] = query_1_7.bl_major_revision;
0455 
0456     rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "Bootloader V%d.%d\n",
0457         f34->bootloader_id[1], f34->bootloader_id[0]);
0458 
0459     return 0;
0460 }
0461 
0462 static int rmi_f34v7_read_queries(struct f34_data *f34)
0463 {
0464     int ret;
0465     int i;
0466     u8 base;
0467     int offset;
0468     u8 *ptable;
0469     u8 query_0;
0470     struct f34v7_query_1_7 query_1_7;
0471 
0472     base = f34->fn->fd.query_base_addr;
0473 
0474     ret = rmi_read_block(f34->fn->rmi_dev,
0475             base,
0476             &query_0,
0477             sizeof(query_0));
0478     if (ret < 0) {
0479         dev_err(&f34->fn->dev,
0480             "%s: Failed to read query 0\n", __func__);
0481         return ret;
0482     }
0483 
0484     offset = (query_0 & 0x07) + 1;
0485 
0486     ret = rmi_read_block(f34->fn->rmi_dev,
0487             base + offset,
0488             &query_1_7,
0489             sizeof(query_1_7));
0490     if (ret < 0) {
0491         dev_err(&f34->fn->dev, "%s: Failed to read queries 1 to 7\n",
0492             __func__);
0493         return ret;
0494     }
0495 
0496     f34->bootloader_id[0] = query_1_7.bl_minor_revision;
0497     f34->bootloader_id[1] = query_1_7.bl_major_revision;
0498 
0499     f34->v7.block_size = le16_to_cpu(query_1_7.block_size);
0500     f34->v7.flash_config_length =
0501             le16_to_cpu(query_1_7.flash_config_length);
0502     f34->v7.payload_length = le16_to_cpu(query_1_7.payload_length);
0503 
0504     rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: f34->v7.block_size = %d\n",
0505          __func__, f34->v7.block_size);
0506 
0507     f34->v7.off.flash_status = V7_FLASH_STATUS_OFFSET;
0508     f34->v7.off.partition_id = V7_PARTITION_ID_OFFSET;
0509     f34->v7.off.block_number = V7_BLOCK_NUMBER_OFFSET;
0510     f34->v7.off.transfer_length = V7_TRANSFER_LENGTH_OFFSET;
0511     f34->v7.off.flash_cmd = V7_COMMAND_OFFSET;
0512     f34->v7.off.payload = V7_PAYLOAD_OFFSET;
0513 
0514     f34->v7.has_display_cfg = query_1_7.partition_support[1] & HAS_DISP_CFG;
0515     f34->v7.has_guest_code =
0516             query_1_7.partition_support[1] & HAS_GUEST_CODE;
0517 
0518     if (query_0 & HAS_CONFIG_ID) {
0519         u8 f34_ctrl[CONFIG_ID_SIZE];
0520 
0521         ret = rmi_read_block(f34->fn->rmi_dev,
0522                 f34->fn->fd.control_base_addr,
0523                 f34_ctrl,
0524                 sizeof(f34_ctrl));
0525         if (ret)
0526             return ret;
0527 
0528         /* Eat leading zeros */
0529         for (i = 0; i < sizeof(f34_ctrl) - 1 && !f34_ctrl[i]; i++)
0530             /* Empty */;
0531 
0532         snprintf(f34->configuration_id, sizeof(f34->configuration_id),
0533              "%*phN", (int)sizeof(f34_ctrl) - i, f34_ctrl + i);
0534 
0535         rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "Configuration ID: %s\n",
0536             f34->configuration_id);
0537     }
0538 
0539     f34->v7.partitions = 0;
0540     for (i = 0; i < sizeof(query_1_7.partition_support); i++)
0541         f34->v7.partitions += hweight8(query_1_7.partition_support[i]);
0542 
0543     rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: Supported partitions: %*ph\n",
0544         __func__, sizeof(query_1_7.partition_support),
0545         query_1_7.partition_support);
0546 
0547 
0548     f34->v7.partition_table_bytes = f34->v7.partitions * 8 + 2;
0549 
0550     f34->v7.read_config_buf = devm_kzalloc(&f34->fn->dev,
0551             f34->v7.partition_table_bytes,
0552             GFP_KERNEL);
0553     if (!f34->v7.read_config_buf) {
0554         f34->v7.read_config_buf_size = 0;
0555         return -ENOMEM;
0556     }
0557 
0558     f34->v7.read_config_buf_size = f34->v7.partition_table_bytes;
0559     ptable = f34->v7.read_config_buf;
0560 
0561     ret = rmi_f34v7_read_partition_table(f34);
0562     if (ret < 0) {
0563         dev_err(&f34->fn->dev, "%s: Failed to read partition table\n",
0564                 __func__);
0565         return ret;
0566     }
0567 
0568     rmi_f34v7_parse_partition_table(f34, ptable,
0569                     &f34->v7.blkcount, &f34->v7.phyaddr);
0570 
0571     return 0;
0572 }
0573 
0574 static int rmi_f34v7_check_ui_firmware_size(struct f34_data *f34)
0575 {
0576     u16 block_count;
0577 
0578     block_count = f34->v7.img.ui_firmware.size / f34->v7.block_size;
0579     f34->update_size += block_count;
0580 
0581     if (block_count != f34->v7.blkcount.ui_firmware) {
0582         dev_err(&f34->fn->dev,
0583             "UI firmware size mismatch: %d != %d\n",
0584             block_count, f34->v7.blkcount.ui_firmware);
0585         return -EINVAL;
0586     }
0587 
0588     return 0;
0589 }
0590 
0591 static int rmi_f34v7_check_ui_config_size(struct f34_data *f34)
0592 {
0593     u16 block_count;
0594 
0595     block_count = f34->v7.img.ui_config.size / f34->v7.block_size;
0596     f34->update_size += block_count;
0597 
0598     if (block_count != f34->v7.blkcount.ui_config) {
0599         dev_err(&f34->fn->dev, "UI config size mismatch\n");
0600         return -EINVAL;
0601     }
0602 
0603     return 0;
0604 }
0605 
0606 static int rmi_f34v7_check_dp_config_size(struct f34_data *f34)
0607 {
0608     u16 block_count;
0609 
0610     block_count = f34->v7.img.dp_config.size / f34->v7.block_size;
0611     f34->update_size += block_count;
0612 
0613     if (block_count != f34->v7.blkcount.dp_config) {
0614         dev_err(&f34->fn->dev, "Display config size mismatch\n");
0615         return -EINVAL;
0616     }
0617 
0618     return 0;
0619 }
0620 
0621 static int rmi_f34v7_check_guest_code_size(struct f34_data *f34)
0622 {
0623     u16 block_count;
0624 
0625     block_count = f34->v7.img.guest_code.size / f34->v7.block_size;
0626     f34->update_size += block_count;
0627 
0628     if (block_count != f34->v7.blkcount.guest_code) {
0629         dev_err(&f34->fn->dev, "Guest code size mismatch\n");
0630         return -EINVAL;
0631     }
0632 
0633     return 0;
0634 }
0635 
0636 static int rmi_f34v7_check_bl_config_size(struct f34_data *f34)
0637 {
0638     u16 block_count;
0639 
0640     block_count = f34->v7.img.bl_config.size / f34->v7.block_size;
0641     f34->update_size += block_count;
0642 
0643     if (block_count != f34->v7.blkcount.bl_config) {
0644         dev_err(&f34->fn->dev, "Bootloader config size mismatch\n");
0645         return -EINVAL;
0646     }
0647 
0648     return 0;
0649 }
0650 
0651 static int rmi_f34v7_erase_config(struct f34_data *f34)
0652 {
0653     int ret;
0654 
0655     dev_info(&f34->fn->dev, "Erasing config...\n");
0656 
0657     init_completion(&f34->v7.cmd_done);
0658 
0659     switch (f34->v7.config_area) {
0660     case v7_UI_CONFIG_AREA:
0661         ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_UI_CONFIG);
0662         if (ret < 0)
0663             return ret;
0664         break;
0665     case v7_DP_CONFIG_AREA:
0666         ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_DISP_CONFIG);
0667         if (ret < 0)
0668             return ret;
0669         break;
0670     case v7_BL_CONFIG_AREA:
0671         ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_BL_CONFIG);
0672         if (ret < 0)
0673             return ret;
0674         break;
0675     }
0676 
0677     ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS);
0678     if (ret < 0)
0679         return ret;
0680 
0681     return 0;
0682 }
0683 
0684 static int rmi_f34v7_erase_guest_code(struct f34_data *f34)
0685 {
0686     int ret;
0687 
0688     dev_info(&f34->fn->dev, "Erasing guest code...\n");
0689 
0690     init_completion(&f34->v7.cmd_done);
0691 
0692     ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_GUEST_CODE);
0693     if (ret < 0)
0694         return ret;
0695 
0696     ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS);
0697     if (ret < 0)
0698         return ret;
0699 
0700     return 0;
0701 }
0702 
0703 static int rmi_f34v7_erase_all(struct f34_data *f34)
0704 {
0705     int ret;
0706 
0707     dev_info(&f34->fn->dev, "Erasing firmware...\n");
0708 
0709     init_completion(&f34->v7.cmd_done);
0710 
0711     ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_UI_FIRMWARE);
0712     if (ret < 0)
0713         return ret;
0714 
0715     ret = rmi_f34v7_wait_for_idle(f34, F34_ERASE_WAIT_MS);
0716     if (ret < 0)
0717         return ret;
0718 
0719     f34->v7.config_area = v7_UI_CONFIG_AREA;
0720     ret = rmi_f34v7_erase_config(f34);
0721     if (ret < 0)
0722         return ret;
0723 
0724     if (f34->v7.has_display_cfg) {
0725         f34->v7.config_area = v7_DP_CONFIG_AREA;
0726         ret = rmi_f34v7_erase_config(f34);
0727         if (ret < 0)
0728             return ret;
0729     }
0730 
0731     if (f34->v7.new_partition_table && f34->v7.has_guest_code) {
0732         ret = rmi_f34v7_erase_guest_code(f34);
0733         if (ret < 0)
0734             return ret;
0735     }
0736 
0737     return 0;
0738 }
0739 
0740 static int rmi_f34v7_read_blocks(struct f34_data *f34,
0741                  u16 block_cnt, u8 command)
0742 {
0743     int ret;
0744     u8 base;
0745     __le16 length;
0746     u16 transfer;
0747     u16 max_transfer;
0748     u16 remaining = block_cnt;
0749     u16 block_number = 0;
0750     u16 index = 0;
0751 
0752     base = f34->fn->fd.data_base_addr;
0753 
0754     ret = rmi_f34v7_write_partition_id(f34, command);
0755     if (ret < 0)
0756         return ret;
0757 
0758     ret = rmi_write_block(f34->fn->rmi_dev,
0759             base + f34->v7.off.block_number,
0760             &block_number, sizeof(block_number));
0761     if (ret < 0) {
0762         dev_err(&f34->fn->dev, "%s: Failed to write block number\n",
0763             __func__);
0764         return ret;
0765     }
0766 
0767     max_transfer = min(f34->v7.payload_length,
0768                (u16)(PAGE_SIZE / f34->v7.block_size));
0769 
0770     do {
0771         transfer = min(remaining, max_transfer);
0772         put_unaligned_le16(transfer, &length);
0773 
0774         ret = rmi_write_block(f34->fn->rmi_dev,
0775                 base + f34->v7.off.transfer_length,
0776                 &length, sizeof(length));
0777         if (ret < 0) {
0778             dev_err(&f34->fn->dev,
0779                 "%s: Write transfer length fail (%d remaining)\n",
0780                 __func__, remaining);
0781             return ret;
0782         }
0783 
0784         init_completion(&f34->v7.cmd_done);
0785 
0786         ret = rmi_f34v7_write_command(f34, command);
0787         if (ret < 0)
0788             return ret;
0789 
0790         ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS);
0791         if (ret < 0)
0792             return ret;
0793 
0794         ret = rmi_read_block(f34->fn->rmi_dev,
0795                 base + f34->v7.off.payload,
0796                 &f34->v7.read_config_buf[index],
0797                 transfer * f34->v7.block_size);
0798         if (ret < 0) {
0799             dev_err(&f34->fn->dev,
0800                 "%s: Read block failed (%d blks remaining)\n",
0801                 __func__, remaining);
0802             return ret;
0803         }
0804 
0805         index += (transfer * f34->v7.block_size);
0806         remaining -= transfer;
0807     } while (remaining);
0808 
0809     return 0;
0810 }
0811 
0812 static int rmi_f34v7_write_f34v7_blocks(struct f34_data *f34,
0813                     const void *block_ptr, u16 block_cnt,
0814                     u8 command)
0815 {
0816     int ret;
0817     u8 base;
0818     __le16 length;
0819     u16 transfer;
0820     u16 max_transfer;
0821     u16 remaining = block_cnt;
0822     u16 block_number = 0;
0823 
0824     base = f34->fn->fd.data_base_addr;
0825 
0826     ret = rmi_f34v7_write_partition_id(f34, command);
0827     if (ret < 0)
0828         return ret;
0829 
0830     ret = rmi_write_block(f34->fn->rmi_dev,
0831             base + f34->v7.off.block_number,
0832             &block_number, sizeof(block_number));
0833     if (ret < 0) {
0834         dev_err(&f34->fn->dev, "%s: Failed to write block number\n",
0835             __func__);
0836         return ret;
0837     }
0838 
0839     if (f34->v7.payload_length > (PAGE_SIZE / f34->v7.block_size))
0840         max_transfer = PAGE_SIZE / f34->v7.block_size;
0841     else
0842         max_transfer = f34->v7.payload_length;
0843 
0844     do {
0845         transfer = min(remaining, max_transfer);
0846         put_unaligned_le16(transfer, &length);
0847 
0848         init_completion(&f34->v7.cmd_done);
0849 
0850         ret = rmi_write_block(f34->fn->rmi_dev,
0851                 base + f34->v7.off.transfer_length,
0852                 &length, sizeof(length));
0853         if (ret < 0) {
0854             dev_err(&f34->fn->dev,
0855                 "%s: Write transfer length fail (%d remaining)\n",
0856                 __func__, remaining);
0857             return ret;
0858         }
0859 
0860         ret = rmi_f34v7_write_command(f34, command);
0861         if (ret < 0)
0862             return ret;
0863 
0864         ret = rmi_write_block(f34->fn->rmi_dev,
0865                 base + f34->v7.off.payload,
0866                 block_ptr, transfer * f34->v7.block_size);
0867         if (ret < 0) {
0868             dev_err(&f34->fn->dev,
0869                 "%s: Failed writing data (%d blks remaining)\n",
0870                 __func__, remaining);
0871             return ret;
0872         }
0873 
0874         ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS);
0875         if (ret < 0)
0876             return ret;
0877 
0878         block_ptr += (transfer * f34->v7.block_size);
0879         remaining -= transfer;
0880         f34->update_progress += transfer;
0881         f34->update_status = (f34->update_progress * 100) /
0882                      f34->update_size;
0883     } while (remaining);
0884 
0885     return 0;
0886 }
0887 
0888 static int rmi_f34v7_write_config(struct f34_data *f34)
0889 {
0890     return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.config_data,
0891                         f34->v7.config_block_count,
0892                         v7_CMD_WRITE_CONFIG);
0893 }
0894 
0895 static int rmi_f34v7_write_ui_config(struct f34_data *f34)
0896 {
0897     f34->v7.config_area = v7_UI_CONFIG_AREA;
0898     f34->v7.config_data = f34->v7.img.ui_config.data;
0899     f34->v7.config_size = f34->v7.img.ui_config.size;
0900     f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
0901 
0902     return rmi_f34v7_write_config(f34);
0903 }
0904 
0905 static int rmi_f34v7_write_dp_config(struct f34_data *f34)
0906 {
0907     f34->v7.config_area = v7_DP_CONFIG_AREA;
0908     f34->v7.config_data = f34->v7.img.dp_config.data;
0909     f34->v7.config_size = f34->v7.img.dp_config.size;
0910     f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
0911 
0912     return rmi_f34v7_write_config(f34);
0913 }
0914 
0915 static int rmi_f34v7_write_guest_code(struct f34_data *f34)
0916 {
0917     return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.img.guest_code.data,
0918                         f34->v7.img.guest_code.size /
0919                             f34->v7.block_size,
0920                         v7_CMD_WRITE_GUEST_CODE);
0921 }
0922 
0923 static int rmi_f34v7_write_flash_config(struct f34_data *f34)
0924 {
0925     int ret;
0926 
0927     f34->v7.config_area = v7_FLASH_CONFIG_AREA;
0928     f34->v7.config_data = f34->v7.img.fl_config.data;
0929     f34->v7.config_size = f34->v7.img.fl_config.size;
0930     f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
0931 
0932     if (f34->v7.config_block_count != f34->v7.blkcount.fl_config) {
0933         dev_err(&f34->fn->dev, "%s: Flash config size mismatch\n",
0934             __func__);
0935         return -EINVAL;
0936     }
0937 
0938     init_completion(&f34->v7.cmd_done);
0939 
0940     ret = rmi_f34v7_write_command(f34, v7_CMD_ERASE_FLASH_CONFIG);
0941     if (ret < 0)
0942         return ret;
0943 
0944     rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
0945         "%s: Erase flash config command written\n", __func__);
0946 
0947     ret = rmi_f34v7_wait_for_idle(f34, F34_WRITE_WAIT_MS);
0948     if (ret < 0)
0949         return ret;
0950 
0951     ret = rmi_f34v7_write_config(f34);
0952     if (ret < 0)
0953         return ret;
0954 
0955     return 0;
0956 }
0957 
0958 static int rmi_f34v7_write_partition_table(struct f34_data *f34)
0959 {
0960     u16 block_count;
0961     int ret;
0962 
0963     block_count = f34->v7.blkcount.bl_config;
0964     f34->v7.config_area = v7_BL_CONFIG_AREA;
0965     f34->v7.config_size = f34->v7.block_size * block_count;
0966     devm_kfree(&f34->fn->dev, f34->v7.read_config_buf);
0967     f34->v7.read_config_buf = devm_kzalloc(&f34->fn->dev,
0968                            f34->v7.config_size, GFP_KERNEL);
0969     if (!f34->v7.read_config_buf) {
0970         f34->v7.read_config_buf_size = 0;
0971         return -ENOMEM;
0972     }
0973 
0974     f34->v7.read_config_buf_size = f34->v7.config_size;
0975 
0976     ret = rmi_f34v7_read_blocks(f34, block_count, v7_CMD_READ_CONFIG);
0977     if (ret < 0)
0978         return ret;
0979 
0980     ret = rmi_f34v7_erase_config(f34);
0981     if (ret < 0)
0982         return ret;
0983 
0984     ret = rmi_f34v7_write_flash_config(f34);
0985     if (ret < 0)
0986         return ret;
0987 
0988     f34->v7.config_area = v7_BL_CONFIG_AREA;
0989     f34->v7.config_data = f34->v7.read_config_buf;
0990     f34->v7.config_size = f34->v7.img.bl_config.size;
0991     f34->v7.config_block_count = f34->v7.config_size / f34->v7.block_size;
0992 
0993     ret = rmi_f34v7_write_config(f34);
0994     if (ret < 0)
0995         return ret;
0996 
0997     return 0;
0998 }
0999 
1000 static int rmi_f34v7_write_firmware(struct f34_data *f34)
1001 {
1002     u16 blk_count;
1003 
1004     blk_count = f34->v7.img.ui_firmware.size / f34->v7.block_size;
1005 
1006     return rmi_f34v7_write_f34v7_blocks(f34, f34->v7.img.ui_firmware.data,
1007                         blk_count, v7_CMD_WRITE_FW);
1008 }
1009 
1010 static void rmi_f34v7_compare_partition_tables(struct f34_data *f34)
1011 {
1012     if (f34->v7.phyaddr.ui_firmware != f34->v7.img.phyaddr.ui_firmware) {
1013         f34->v7.new_partition_table = true;
1014         return;
1015     }
1016 
1017     if (f34->v7.phyaddr.ui_config != f34->v7.img.phyaddr.ui_config) {
1018         f34->v7.new_partition_table = true;
1019         return;
1020     }
1021 
1022     if (f34->v7.has_display_cfg &&
1023         f34->v7.phyaddr.dp_config != f34->v7.img.phyaddr.dp_config) {
1024         f34->v7.new_partition_table = true;
1025         return;
1026     }
1027 
1028     if (f34->v7.has_guest_code &&
1029         f34->v7.phyaddr.guest_code != f34->v7.img.phyaddr.guest_code) {
1030         f34->v7.new_partition_table = true;
1031         return;
1032     }
1033 
1034     f34->v7.new_partition_table = false;
1035 }
1036 
1037 static void rmi_f34v7_parse_img_header_10_bl_container(struct f34_data *f34,
1038                                const void *image)
1039 {
1040     int i;
1041     int num_of_containers;
1042     unsigned int addr;
1043     unsigned int container_id;
1044     unsigned int length;
1045     const void *content;
1046     const struct container_descriptor *descriptor;
1047 
1048     num_of_containers = f34->v7.img.bootloader.size / 4 - 1;
1049 
1050     for (i = 1; i <= num_of_containers; i++) {
1051         addr = get_unaligned_le32(f34->v7.img.bootloader.data + i * 4);
1052         descriptor = image + addr;
1053         container_id = le16_to_cpu(descriptor->container_id);
1054         content = image + le32_to_cpu(descriptor->content_address);
1055         length = le32_to_cpu(descriptor->content_length);
1056         switch (container_id) {
1057         case BL_CONFIG_CONTAINER:
1058         case GLOBAL_PARAMETERS_CONTAINER:
1059             f34->v7.img.bl_config.data = content;
1060             f34->v7.img.bl_config.size = length;
1061             break;
1062         case BL_LOCKDOWN_INFO_CONTAINER:
1063         case DEVICE_CONFIG_CONTAINER:
1064             f34->v7.img.lockdown.data = content;
1065             f34->v7.img.lockdown.size = length;
1066             break;
1067         default:
1068             break;
1069         }
1070     }
1071 }
1072 
1073 static void rmi_f34v7_parse_image_header_10(struct f34_data *f34)
1074 {
1075     unsigned int i;
1076     unsigned int num_of_containers;
1077     unsigned int addr;
1078     unsigned int offset;
1079     unsigned int container_id;
1080     unsigned int length;
1081     const void *image = f34->v7.image;
1082     const u8 *content;
1083     const struct container_descriptor *descriptor;
1084     const struct image_header_10 *header = image;
1085 
1086     f34->v7.img.checksum = le32_to_cpu(header->checksum);
1087 
1088     rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev, "%s: f34->v7.img.checksum=%X\n",
1089         __func__, f34->v7.img.checksum);
1090 
1091     /* address of top level container */
1092     offset = le32_to_cpu(header->top_level_container_start_addr);
1093     descriptor = image + offset;
1094 
1095     /* address of top level container content */
1096     offset = le32_to_cpu(descriptor->content_address);
1097     num_of_containers = le32_to_cpu(descriptor->content_length) / 4;
1098 
1099     for (i = 0; i < num_of_containers; i++) {
1100         addr = get_unaligned_le32(image + offset);
1101         offset += 4;
1102         descriptor = image + addr;
1103         container_id = le16_to_cpu(descriptor->container_id);
1104         content = image + le32_to_cpu(descriptor->content_address);
1105         length = le32_to_cpu(descriptor->content_length);
1106 
1107         rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
1108             "%s: container_id=%d, length=%d\n", __func__,
1109             container_id, length);
1110 
1111         switch (container_id) {
1112         case UI_CONTAINER:
1113         case CORE_CODE_CONTAINER:
1114             f34->v7.img.ui_firmware.data = content;
1115             f34->v7.img.ui_firmware.size = length;
1116             break;
1117         case UI_CONFIG_CONTAINER:
1118         case CORE_CONFIG_CONTAINER:
1119             f34->v7.img.ui_config.data = content;
1120             f34->v7.img.ui_config.size = length;
1121             break;
1122         case BL_CONTAINER:
1123             f34->v7.img.bl_version = *content;
1124             f34->v7.img.bootloader.data = content;
1125             f34->v7.img.bootloader.size = length;
1126             rmi_f34v7_parse_img_header_10_bl_container(f34, image);
1127             break;
1128         case GUEST_CODE_CONTAINER:
1129             f34->v7.img.contains_guest_code = true;
1130             f34->v7.img.guest_code.data = content;
1131             f34->v7.img.guest_code.size = length;
1132             break;
1133         case DISPLAY_CONFIG_CONTAINER:
1134             f34->v7.img.contains_display_cfg = true;
1135             f34->v7.img.dp_config.data = content;
1136             f34->v7.img.dp_config.size = length;
1137             break;
1138         case FLASH_CONFIG_CONTAINER:
1139             f34->v7.img.contains_flash_config = true;
1140             f34->v7.img.fl_config.data = content;
1141             f34->v7.img.fl_config.size = length;
1142             break;
1143         case GENERAL_INFORMATION_CONTAINER:
1144             f34->v7.img.contains_firmware_id = true;
1145             f34->v7.img.firmware_id =
1146                 get_unaligned_le32(content + 4);
1147             break;
1148         default:
1149             break;
1150         }
1151     }
1152 }
1153 
1154 static int rmi_f34v7_parse_image_info(struct f34_data *f34)
1155 {
1156     const struct image_header_10 *header = f34->v7.image;
1157 
1158     memset(&f34->v7.img, 0x00, sizeof(f34->v7.img));
1159 
1160     rmi_dbg(RMI_DEBUG_FN, &f34->fn->dev,
1161         "%s: header->major_header_version = %d\n",
1162         __func__, header->major_header_version);
1163 
1164     switch (header->major_header_version) {
1165     case IMAGE_HEADER_VERSION_10:
1166         rmi_f34v7_parse_image_header_10(f34);
1167         break;
1168     default:
1169         dev_err(&f34->fn->dev, "Unsupported image file format %02X\n",
1170             header->major_header_version);
1171         return -EINVAL;
1172     }
1173 
1174     if (!f34->v7.img.contains_flash_config) {
1175         dev_err(&f34->fn->dev, "%s: No flash config in fw image\n",
1176             __func__);
1177         return -EINVAL;
1178     }
1179 
1180     rmi_f34v7_parse_partition_table(f34, f34->v7.img.fl_config.data,
1181             &f34->v7.img.blkcount, &f34->v7.img.phyaddr);
1182 
1183     rmi_f34v7_compare_partition_tables(f34);
1184 
1185     return 0;
1186 }
1187 
1188 int rmi_f34v7_do_reflash(struct f34_data *f34, const struct firmware *fw)
1189 {
1190     int ret;
1191 
1192     f34->fn->rmi_dev->driver->set_irq_bits(f34->fn->rmi_dev,
1193                            f34->fn->irq_mask);
1194 
1195     rmi_f34v7_read_queries_bl_version(f34);
1196 
1197     f34->v7.image = fw->data;
1198     f34->update_progress = 0;
1199     f34->update_size = 0;
1200 
1201     ret = rmi_f34v7_parse_image_info(f34);
1202     if (ret < 0)
1203         goto fail;
1204 
1205     if (!f34->v7.new_partition_table) {
1206         ret = rmi_f34v7_check_ui_firmware_size(f34);
1207         if (ret < 0)
1208             goto fail;
1209 
1210         ret = rmi_f34v7_check_ui_config_size(f34);
1211         if (ret < 0)
1212             goto fail;
1213 
1214         if (f34->v7.has_display_cfg &&
1215             f34->v7.img.contains_display_cfg) {
1216             ret = rmi_f34v7_check_dp_config_size(f34);
1217             if (ret < 0)
1218                 goto fail;
1219         }
1220 
1221         if (f34->v7.has_guest_code && f34->v7.img.contains_guest_code) {
1222             ret = rmi_f34v7_check_guest_code_size(f34);
1223             if (ret < 0)
1224                 goto fail;
1225         }
1226     } else {
1227         ret = rmi_f34v7_check_bl_config_size(f34);
1228         if (ret < 0)
1229             goto fail;
1230     }
1231 
1232     ret = rmi_f34v7_erase_all(f34);
1233     if (ret < 0)
1234         goto fail;
1235 
1236     if (f34->v7.new_partition_table) {
1237         ret = rmi_f34v7_write_partition_table(f34);
1238         if (ret < 0)
1239             goto fail;
1240         dev_info(&f34->fn->dev, "%s: Partition table programmed\n",
1241              __func__);
1242     }
1243 
1244     dev_info(&f34->fn->dev, "Writing firmware (%d bytes)...\n",
1245          f34->v7.img.ui_firmware.size);
1246 
1247     ret = rmi_f34v7_write_firmware(f34);
1248     if (ret < 0)
1249         goto fail;
1250 
1251     dev_info(&f34->fn->dev, "Writing config (%d bytes)...\n",
1252          f34->v7.img.ui_config.size);
1253 
1254     f34->v7.config_area = v7_UI_CONFIG_AREA;
1255     ret = rmi_f34v7_write_ui_config(f34);
1256     if (ret < 0)
1257         goto fail;
1258 
1259     if (f34->v7.has_display_cfg && f34->v7.img.contains_display_cfg) {
1260         dev_info(&f34->fn->dev, "Writing display config...\n");
1261 
1262         ret = rmi_f34v7_write_dp_config(f34);
1263         if (ret < 0)
1264             goto fail;
1265     }
1266 
1267     if (f34->v7.new_partition_table) {
1268         if (f34->v7.has_guest_code && f34->v7.img.contains_guest_code) {
1269             dev_info(&f34->fn->dev, "Writing guest code...\n");
1270 
1271             ret = rmi_f34v7_write_guest_code(f34);
1272             if (ret < 0)
1273                 goto fail;
1274         }
1275     }
1276 
1277 fail:
1278     return ret;
1279 }
1280 
1281 static int rmi_f34v7_enter_flash_prog(struct f34_data *f34)
1282 {
1283     int ret;
1284 
1285     f34->fn->rmi_dev->driver->set_irq_bits(f34->fn->rmi_dev, f34->fn->irq_mask);
1286 
1287     ret = rmi_f34v7_read_flash_status(f34);
1288     if (ret < 0)
1289         return ret;
1290 
1291     if (f34->v7.in_bl_mode)
1292         return 0;
1293 
1294     init_completion(&f34->v7.cmd_done);
1295 
1296     ret = rmi_f34v7_write_command(f34, v7_CMD_ENABLE_FLASH_PROG);
1297     if (ret < 0)
1298         return ret;
1299 
1300     ret = rmi_f34v7_wait_for_idle(f34, F34_ENABLE_WAIT_MS);
1301     if (ret < 0)
1302         return ret;
1303 
1304     return 0;
1305 }
1306 
1307 int rmi_f34v7_start_reflash(struct f34_data *f34, const struct firmware *fw)
1308 {
1309     int ret = 0;
1310 
1311     f34->fn->rmi_dev->driver->set_irq_bits(f34->fn->rmi_dev, f34->fn->irq_mask);
1312 
1313     f34->v7.config_area = v7_UI_CONFIG_AREA;
1314     f34->v7.image = fw->data;
1315 
1316     ret = rmi_f34v7_parse_image_info(f34);
1317     if (ret < 0)
1318         goto exit;
1319 
1320     if (!f34->v7.force_update && f34->v7.new_partition_table) {
1321         dev_err(&f34->fn->dev, "%s: Partition table mismatch\n",
1322                 __func__);
1323         ret = -EINVAL;
1324         goto exit;
1325     }
1326 
1327     dev_info(&f34->fn->dev, "Firmware image OK\n");
1328 
1329     ret = rmi_f34v7_read_flash_status(f34);
1330     if (ret < 0)
1331         goto exit;
1332 
1333     if (f34->v7.in_bl_mode) {
1334         dev_info(&f34->fn->dev, "%s: Device in bootloader mode\n",
1335                 __func__);
1336     }
1337 
1338     rmi_f34v7_enter_flash_prog(f34);
1339 
1340     return 0;
1341 
1342 exit:
1343     return ret;
1344 }
1345 
1346 int rmi_f34v7_probe(struct f34_data *f34)
1347 {
1348     int ret;
1349 
1350     /* Read bootloader version */
1351     ret = rmi_read_block(f34->fn->rmi_dev,
1352             f34->fn->fd.query_base_addr + V7_BOOTLOADER_ID_OFFSET,
1353             f34->bootloader_id,
1354             sizeof(f34->bootloader_id));
1355     if (ret < 0) {
1356         dev_err(&f34->fn->dev, "%s: Failed to read bootloader ID\n",
1357             __func__);
1358         return ret;
1359     }
1360 
1361     if (f34->bootloader_id[1] == '5') {
1362         f34->bl_version = 5;
1363     } else if (f34->bootloader_id[1] == '6') {
1364         f34->bl_version = 6;
1365     } else if (f34->bootloader_id[1] == 7) {
1366         f34->bl_version = 7;
1367     } else if (f34->bootloader_id[1] == 8) {
1368         f34->bl_version = 8;
1369     } else {
1370         dev_err(&f34->fn->dev,
1371             "%s: Unrecognized bootloader version: %d (%c) %d (%c)\n",
1372             __func__,
1373             f34->bootloader_id[0], f34->bootloader_id[0],
1374             f34->bootloader_id[1], f34->bootloader_id[1]);
1375         return -EINVAL;
1376     }
1377 
1378     memset(&f34->v7.blkcount, 0x00, sizeof(f34->v7.blkcount));
1379     memset(&f34->v7.phyaddr, 0x00, sizeof(f34->v7.phyaddr));
1380 
1381     init_completion(&f34->v7.cmd_done);
1382 
1383     ret = rmi_f34v7_read_queries(f34);
1384     if (ret < 0)
1385         return ret;
1386 
1387     f34->v7.force_update = true;
1388     return 0;
1389 }
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