input/mouse/cyapa.h

0001 /*
0002  * Cypress APA trackpad with I2C interface
0003  *
0004  * Author: Dudley Du <dudl@cypress.com>
0005  *
0006  * Copyright (C) 2014-2015 Cypress Semiconductor, Inc.
0007  *
0008  * This file is subject to the terms and conditions of the GNU General Public
0009  * License.  See the file COPYING in the main directory of this archive for
0010  * more details.
0011  */
0012
0013 #ifndef _CYAPA_H
0014 #define _CYAPA_H
0015
0016 #include <linux/firmware.h>
0017
0018 /* APA trackpad firmware generation number. */
0019 #define CYAPA_GEN_UNKNOWN   0x00   /* unknown protocol. */
0020 #define CYAPA_GEN3   0x03   /* support MT-protocol B with tracking ID. */
0021 #define CYAPA_GEN5   0x05   /* support TrueTouch GEN5 trackpad device. */
0022 #define CYAPA_GEN6   0x06   /* support TrueTouch GEN6 trackpad device. */
0023
0024 #define CYAPA_NAME   "Cypress APA Trackpad (cyapa)"
0025
0026 /*
0027  * Macros for SMBus communication
0028  */
0029 #define SMBUS_READ  0x01
0030 #define SMBUS_WRITE 0x00
0031 #define SMBUS_ENCODE_IDX(cmd, idx) ((cmd) | (((idx) & 0x03) << 1))
0032 #define SMBUS_ENCODE_RW(cmd, rw) ((cmd) | ((rw) & 0x01))
0033 #define SMBUS_BYTE_BLOCK_CMD_MASK 0x80
0034 #define SMBUS_GROUP_BLOCK_CMD_MASK 0x40
0035
0036 /* Commands for read/write registers of Cypress trackpad */
0037 #define CYAPA_CMD_SOFT_RESET       0x00
0038 #define CYAPA_CMD_POWER_MODE       0x01
0039 #define CYAPA_CMD_DEV_STATUS       0x02
0040 #define CYAPA_CMD_GROUP_DATA       0x03
0041 #define CYAPA_CMD_GROUP_CMD        0x04
0042 #define CYAPA_CMD_GROUP_QUERY      0x05
0043 #define CYAPA_CMD_BL_STATUS        0x06
0044 #define CYAPA_CMD_BL_HEAD          0x07
0045 #define CYAPA_CMD_BL_CMD           0x08
0046 #define CYAPA_CMD_BL_DATA          0x09
0047 #define CYAPA_CMD_BL_ALL           0x0a
0048 #define CYAPA_CMD_BLK_PRODUCT_ID   0x0b
0049 #define CYAPA_CMD_BLK_HEAD         0x0c
0050 #define CYAPA_CMD_MAX_BASELINE     0x0d
0051 #define CYAPA_CMD_MIN_BASELINE     0x0e
0052
0053 #define BL_HEAD_OFFSET 0x00
0054 #define BL_DATA_OFFSET 0x10
0055
0056 #define BL_STATUS_SIZE  3  /* Length of gen3 bootloader status registers */
0057 #define CYAPA_REG_MAP_SIZE  256
0058
0059 /*
0060  * Gen3 Operational Device Status Register
0061  *
0062  * bit 7: Valid interrupt source
0063  * bit 6 - 4: Reserved
0064  * bit 3 - 2: Power status
0065  * bit 1 - 0: Device status
0066  */
0067 #define REG_OP_STATUS     0x00
0068 #define OP_STATUS_SRC     0x80
0069 #define OP_STATUS_POWER   0x0c
0070 #define OP_STATUS_DEV     0x03
0071 #define OP_STATUS_MASK (OP_STATUS_SRC | OP_STATUS_POWER | OP_STATUS_DEV)
0072
0073 /*
0074  * Operational Finger Count/Button Flags Register
0075  *
0076  * bit 7 - 4: Number of touched finger
0077  * bit 3: Valid data
0078  * bit 2: Middle Physical Button
0079  * bit 1: Right Physical Button
0080  * bit 0: Left physical Button
0081  */
0082 #define REG_OP_DATA1       0x01
0083 #define OP_DATA_VALID      0x08
0084 #define OP_DATA_MIDDLE_BTN 0x04
0085 #define OP_DATA_RIGHT_BTN  0x02
0086 #define OP_DATA_LEFT_BTN   0x01
0087 #define OP_DATA_BTN_MASK (OP_DATA_MIDDLE_BTN | OP_DATA_RIGHT_BTN | \
0088               OP_DATA_LEFT_BTN)
0089
0090 /*
0091  * Write-only command file register used to issue commands and
0092  * parameters to the bootloader.
0093  * The default value read from it is always 0x00.
0094  */
0095 #define REG_BL_FILE 0x00
0096 #define BL_FILE     0x00
0097
0098 /*
0099  * Bootloader Status Register
0100  *
0101  * bit 7: Busy
0102  * bit 6 - 5: Reserved
0103  * bit 4: Bootloader running
0104  * bit 3 - 2: Reserved
0105  * bit 1: Watchdog Reset
0106  * bit 0: Checksum valid
0107  */
0108 #define REG_BL_STATUS        0x01
0109 #define BL_STATUS_REV_6_5    0x60
0110 #define BL_STATUS_BUSY       0x80
0111 #define BL_STATUS_RUNNING    0x10
0112 #define BL_STATUS_REV_3_2    0x0c
0113 #define BL_STATUS_WATCHDOG   0x02
0114 #define BL_STATUS_CSUM_VALID 0x01
0115 #define BL_STATUS_REV_MASK (BL_STATUS_WATCHDOG | BL_STATUS_REV_3_2 | \
0116                 BL_STATUS_REV_6_5)
0117
0118 /*
0119  * Bootloader Error Register
0120  *
0121  * bit 7: Invalid
0122  * bit 6: Invalid security key
0123  * bit 5: Bootloading
0124  * bit 4: Command checksum
0125  * bit 3: Flash protection error
0126  * bit 2: Flash checksum error
0127  * bit 1 - 0: Reserved
0128  */
0129 #define REG_BL_ERROR         0x02
0130 #define BL_ERROR_INVALID     0x80
0131 #define BL_ERROR_INVALID_KEY 0x40
0132 #define BL_ERROR_BOOTLOADING 0x20
0133 #define BL_ERROR_CMD_CSUM    0x10
0134 #define BL_ERROR_FLASH_PROT  0x08
0135 #define BL_ERROR_FLASH_CSUM  0x04
0136 #define BL_ERROR_RESERVED    0x03
0137 #define BL_ERROR_NO_ERR_IDLE    0x00
0138 #define BL_ERROR_NO_ERR_ACTIVE  (BL_ERROR_BOOTLOADING)
0139
0140 #define CAPABILITY_BTN_SHIFT            3
0141 #define CAPABILITY_LEFT_BTN_MASK    (0x01 << 3)
0142 #define CAPABILITY_RIGHT_BTN_MASK   (0x01 << 4)
0143 #define CAPABILITY_MIDDLE_BTN_MASK  (0x01 << 5)
0144 #define CAPABILITY_BTN_MASK  (CAPABILITY_LEFT_BTN_MASK | \
0145                   CAPABILITY_RIGHT_BTN_MASK | \
0146                   CAPABILITY_MIDDLE_BTN_MASK)
0147
0148 #define PWR_MODE_MASK   0xfc
0149 #define PWR_MODE_FULL_ACTIVE (0x3f << 2)
0150 #define PWR_MODE_IDLE        (0x03 << 2) /* Default rt suspend scanrate: 30ms */
0151 #define PWR_MODE_SLEEP       (0x05 << 2) /* Default suspend scanrate: 50ms */
0152 #define PWR_MODE_BTN_ONLY    (0x01 << 2)
0153 #define PWR_MODE_OFF         (0x00 << 2)
0154
0155 #define PWR_STATUS_MASK      0x0c
0156 #define PWR_STATUS_ACTIVE    (0x03 << 2)
0157 #define PWR_STATUS_IDLE      (0x02 << 2)
0158 #define PWR_STATUS_BTN_ONLY  (0x01 << 2)
0159 #define PWR_STATUS_OFF       (0x00 << 2)
0160
0161 #define AUTOSUSPEND_DELAY   2000 /* unit : ms */
0162
0163 #define BTN_ONLY_MODE_NAME   "buttononly"
0164 #define OFF_MODE_NAME        "off"
0165
0166 /* Common macros for PIP interface. */
0167 #define PIP_HID_DESCRIPTOR_ADDR     0x0001
0168 #define PIP_REPORT_DESCRIPTOR_ADDR  0x0002
0169 #define PIP_INPUT_REPORT_ADDR       0x0003
0170 #define PIP_OUTPUT_REPORT_ADDR      0x0004
0171 #define PIP_CMD_DATA_ADDR       0x0006
0172
0173 #define PIP_RETRIEVE_DATA_STRUCTURE 0x24
0174 #define PIP_CMD_CALIBRATE       0x28
0175 #define PIP_BL_CMD_VERIFY_APP_INTEGRITY 0x31
0176 #define PIP_BL_CMD_GET_BL_INFO      0x38
0177 #define PIP_BL_CMD_PROGRAM_VERIFY_ROW   0x39
0178 #define PIP_BL_CMD_LAUNCH_APP       0x3b
0179 #define PIP_BL_CMD_INITIATE_BL      0x48
0180 #define PIP_INVALID_CMD         0xff
0181
0182 #define PIP_HID_DESCRIPTOR_SIZE     32
0183 #define PIP_HID_APP_REPORT_ID       0xf7
0184 #define PIP_HID_BL_REPORT_ID        0xff
0185
0186 #define PIP_BL_CMD_REPORT_ID        0x40
0187 #define PIP_BL_RESP_REPORT_ID       0x30
0188 #define PIP_APP_CMD_REPORT_ID       0x2f
0189 #define PIP_APP_RESP_REPORT_ID      0x1f
0190
0191 #define PIP_READ_SYS_INFO_CMD_LENGTH    7
0192 #define PIP_BL_READ_APP_INFO_CMD_LENGTH 13
0193 #define PIP_MIN_BL_CMD_LENGTH       13
0194 #define PIP_MIN_BL_RESP_LENGTH      11
0195 #define PIP_MIN_APP_CMD_LENGTH      7
0196 #define PIP_MIN_APP_RESP_LENGTH     5
0197 #define PIP_UNSUPPORTED_CMD_RESP_LENGTH 6
0198 #define PIP_READ_SYS_INFO_RESP_LENGTH   71
0199 #define PIP_BL_APP_INFO_RESP_LENGTH 30
0200 #define PIP_BL_GET_INFO_RESP_LENGTH 19
0201
0202 #define PIP_BL_PLATFORM_VER_SHIFT   4
0203 #define PIP_BL_PLATFORM_VER_MASK    0x0f
0204
0205 #define PIP_PRODUCT_FAMILY_MASK     0xf000
0206 #define PIP_PRODUCT_FAMILY_TRACKPAD 0x1000
0207
0208 #define PIP_DEEP_SLEEP_STATE_ON     0x00
0209 #define PIP_DEEP_SLEEP_STATE_OFF    0x01
0210 #define PIP_DEEP_SLEEP_STATE_MASK   0x03
0211 #define PIP_APP_DEEP_SLEEP_REPORT_ID    0xf0
0212 #define PIP_DEEP_SLEEP_RESP_LENGTH  5
0213 #define PIP_DEEP_SLEEP_OPCODE       0x08
0214 #define PIP_DEEP_SLEEP_OPCODE_MASK  0x0f
0215
0216 #define PIP_RESP_LENGTH_OFFSET      0
0217 #define     PIP_RESP_LENGTH_SIZE    2
0218 #define PIP_RESP_REPORT_ID_OFFSET   2
0219 #define PIP_RESP_RSVD_OFFSET        3
0220 #define     PIP_RESP_RSVD_KEY       0x00
0221 #define PIP_RESP_BL_SOP_OFFSET      4
0222 #define     PIP_SOP_KEY         0x01  /* Start of Packet */
0223 #define     PIP_EOP_KEY         0x17  /* End of Packet */
0224 #define PIP_RESP_APP_CMD_OFFSET     4
0225 #define     GET_PIP_CMD_CODE(reg)   ((reg) & 0x7f)
0226 #define PIP_RESP_STATUS_OFFSET      5
0227
0228 #define VALID_CMD_RESP_HEADER(resp, cmd)                  \
0229     (((resp)[PIP_RESP_REPORT_ID_OFFSET] == PIP_APP_RESP_REPORT_ID) && \
0230     ((resp)[PIP_RESP_RSVD_OFFSET] == PIP_RESP_RSVD_KEY) &&        \
0231     (GET_PIP_CMD_CODE((resp)[PIP_RESP_APP_CMD_OFFSET]) == (cmd)))
0232
0233 #define PIP_CMD_COMPLETE_SUCCESS(resp_data) \
0234     ((resp_data)[PIP_RESP_STATUS_OFFSET] == 0x00)
0235
0236 /* Variables to record latest gen5 trackpad power states. */
0237 #define UNINIT_SLEEP_TIME   0xffff
0238 #define UNINIT_PWR_MODE     0xff
0239 #define PIP_DEV_SET_PWR_STATE(cyapa, s)     ((cyapa)->dev_pwr_mode = (s))
0240 #define PIP_DEV_GET_PWR_STATE(cyapa)        ((cyapa)->dev_pwr_mode)
0241 #define PIP_DEV_SET_SLEEP_TIME(cyapa, t)    ((cyapa)->dev_sleep_time = (t))
0242 #define PIP_DEV_GET_SLEEP_TIME(cyapa)       ((cyapa)->dev_sleep_time)
0243 #define PIP_DEV_UNINIT_SLEEP_TIME(cyapa)    \
0244         (((cyapa)->dev_sleep_time) == UNINIT_SLEEP_TIME)
0245
0246 /* The touch.id is used as the MT slot id, thus max MT slot is 15 */
0247 #define CYAPA_MAX_MT_SLOTS  15
0248
0249 struct cyapa;
0250
0251 typedef bool (*cb_sort)(struct cyapa *, u8 *, int);
0252
0253 enum cyapa_pm_stage {
0254     CYAPA_PM_DEACTIVE,
0255     CYAPA_PM_ACTIVE,
0256     CYAPA_PM_SUSPEND,
0257     CYAPA_PM_RESUME,
0258     CYAPA_PM_RUNTIME_SUSPEND,
0259     CYAPA_PM_RUNTIME_RESUME,
0260 };
0261
0262 struct cyapa_dev_ops {
0263     int (*check_fw)(struct cyapa *, const struct firmware *);
0264     int (*bl_enter)(struct cyapa *);
0265     int (*bl_activate)(struct cyapa *);
0266     int (*bl_initiate)(struct cyapa *, const struct firmware *);
0267     int (*update_fw)(struct cyapa *, const struct firmware *);
0268     int (*bl_deactivate)(struct cyapa *);
0269
0270     ssize_t (*show_baseline)(struct device *,
0271             struct device_attribute *, char *);
0272     ssize_t (*calibrate_store)(struct device *,
0273             struct device_attribute *, const char *, size_t);
0274
0275     int (*initialize)(struct cyapa *cyapa);
0276
0277     int (*state_parse)(struct cyapa *cyapa, u8 *reg_status, int len);
0278     int (*operational_check)(struct cyapa *cyapa);
0279
0280     int (*irq_handler)(struct cyapa *);
0281     bool (*irq_cmd_handler)(struct cyapa *);
0282     int (*sort_empty_output_data)(struct cyapa *,
0283             u8 *, int *, cb_sort);
0284
0285     int (*set_power_mode)(struct cyapa *, u8, u16, enum cyapa_pm_stage);
0286
0287     int (*set_proximity)(struct cyapa *, bool);
0288 };
0289
0290 struct cyapa_pip_cmd_states {
0291     struct mutex cmd_lock;
0292     struct completion cmd_ready;
0293     atomic_t cmd_issued;
0294     u8 in_progress_cmd;
0295     bool is_irq_mode;
0296
0297     cb_sort resp_sort_func;
0298     u8 *resp_data;
0299     int *resp_len;
0300
0301     enum cyapa_pm_stage pm_stage;
0302     struct mutex pm_stage_lock;
0303
0304     u8 irq_cmd_buf[CYAPA_REG_MAP_SIZE];
0305     u8 empty_buf[CYAPA_REG_MAP_SIZE];
0306 };
0307
0308 union cyapa_cmd_states {
0309     struct cyapa_pip_cmd_states pip;
0310 };
0311
0312 enum cyapa_state {
0313     CYAPA_STATE_NO_DEVICE,
0314     CYAPA_STATE_BL_BUSY,
0315     CYAPA_STATE_BL_IDLE,
0316     CYAPA_STATE_BL_ACTIVE,
0317     CYAPA_STATE_OP,
0318     CYAPA_STATE_GEN5_BL,
0319     CYAPA_STATE_GEN5_APP,
0320     CYAPA_STATE_GEN6_BL,
0321     CYAPA_STATE_GEN6_APP,
0322 };
0323
0324 struct gen6_interval_setting {
0325     u16 active_interval;
0326     u16 lp1_interval;
0327     u16 lp2_interval;
0328 };
0329
0330 /* The main device structure */
0331 struct cyapa {
0332     enum cyapa_state state;
0333     u8 status[BL_STATUS_SIZE];
0334     bool operational; /* true: ready for data reporting; false: not. */
0335
0336     struct regulator *vcc;
0337     struct i2c_client *client;
0338     struct input_dev *input;
0339     char phys[32];  /* Device physical location */
0340     bool irq_wake;  /* Irq wake is enabled */
0341     bool smbus;
0342
0343     /* power mode settings */
0344     u8 suspend_power_mode;
0345     u16 suspend_sleep_time;
0346     u8 runtime_suspend_power_mode;
0347     u16 runtime_suspend_sleep_time;
0348     u8 dev_pwr_mode;
0349     u16 dev_sleep_time;
0350     struct gen6_interval_setting gen6_interval_setting;
0351
0352     /* Read from query data region. */
0353     char product_id[16];
0354     u8 platform_ver;  /* Platform version. */
0355     u8 fw_maj_ver;  /* Firmware major version. */
0356     u8 fw_min_ver;  /* Firmware minor version. */
0357     u8 btn_capability;
0358     u8 gen;
0359     int max_abs_x;
0360     int max_abs_y;
0361     int physical_size_x;
0362     int physical_size_y;
0363
0364     /* Used in ttsp and truetouch based trackpad devices. */
0365     u8 x_origin;  /* X Axis Origin: 0 = left side; 1 = right side. */
0366     u8 y_origin;  /* Y Axis Origin: 0 = top; 1 = bottom. */
0367     int electrodes_x;  /* Number of electrodes on the X Axis*/
0368     int electrodes_y;  /* Number of electrodes on the Y Axis*/
0369     int electrodes_rx;  /* Number of Rx electrodes */
0370     int aligned_electrodes_rx;  /* 4 aligned */
0371     int max_z;
0372
0373     /*
0374      * Used to synchronize the access or update the device state.
0375      * And since update firmware and read firmware image process will take
0376      * quite long time, maybe more than 10 seconds, so use mutex_lock
0377      * to sync and wait other interface and detecting are done or ready.
0378      */
0379     struct mutex state_sync_lock;
0380
0381     const struct cyapa_dev_ops *ops;
0382
0383     union cyapa_cmd_states cmd_states;
0384 };
0385
0386
0387 ssize_t cyapa_i2c_reg_read_block(struct cyapa *cyapa, u8 reg, size_t len,
0388                  u8 *values);
0389 ssize_t cyapa_smbus_read_block(struct cyapa *cyapa, u8 cmd, size_t len,
0390                    u8 *values);
0391
0392 ssize_t cyapa_read_block(struct cyapa *cyapa, u8 cmd_idx, u8 *values);
0393
0394 int cyapa_poll_state(struct cyapa *cyapa, unsigned int timeout);
0395
0396 u8 cyapa_sleep_time_to_pwr_cmd(u16 sleep_time);
0397 u16 cyapa_pwr_cmd_to_sleep_time(u8 pwr_mode);
0398
0399 ssize_t cyapa_i2c_pip_read(struct cyapa *cyapa, u8 *buf, size_t size);
0400 ssize_t cyapa_i2c_pip_write(struct cyapa *cyapa, u8 *buf, size_t size);
0401 int cyapa_empty_pip_output_data(struct cyapa *cyapa,
0402                 u8 *buf, int *len, cb_sort func);
0403 int cyapa_i2c_pip_cmd_irq_sync(struct cyapa *cyapa,
0404                    u8 *cmd, int cmd_len,
0405                    u8 *resp_data, int *resp_len,
0406                    unsigned long timeout,
0407                    cb_sort func,
0408                    bool irq_mode);
0409 int cyapa_pip_state_parse(struct cyapa *cyapa, u8 *reg_data, int len);
0410 bool cyapa_pip_sort_system_info_data(struct cyapa *cyapa, u8 *buf, int len);
0411 bool cyapa_sort_tsg_pip_bl_resp_data(struct cyapa *cyapa, u8 *data, int len);
0412 int cyapa_pip_deep_sleep(struct cyapa *cyapa, u8 state);
0413 bool cyapa_sort_tsg_pip_app_resp_data(struct cyapa *cyapa, u8 *data, int len);
0414 int cyapa_pip_bl_exit(struct cyapa *cyapa);
0415 int cyapa_pip_bl_enter(struct cyapa *cyapa);
0416
0417
0418 bool cyapa_is_pip_bl_mode(struct cyapa *cyapa);
0419 bool cyapa_is_pip_app_mode(struct cyapa *cyapa);
0420 int cyapa_pip_cmd_state_initialize(struct cyapa *cyapa);
0421
0422 int cyapa_pip_resume_scanning(struct cyapa *cyapa);
0423 int cyapa_pip_suspend_scanning(struct cyapa *cyapa);
0424
0425 int cyapa_pip_check_fw(struct cyapa *cyapa, const struct firmware *fw);
0426 int cyapa_pip_bl_initiate(struct cyapa *cyapa, const struct firmware *fw);
0427 int cyapa_pip_do_fw_update(struct cyapa *cyapa, const struct firmware *fw);
0428 int cyapa_pip_bl_activate(struct cyapa *cyapa);
0429 int cyapa_pip_bl_deactivate(struct cyapa *cyapa);
0430 ssize_t cyapa_pip_do_calibrate(struct device *dev,
0431                    struct device_attribute *attr,
0432                    const char *buf, size_t count);
0433 int cyapa_pip_set_proximity(struct cyapa *cyapa, bool enable);
0434
0435 bool cyapa_pip_irq_cmd_handler(struct cyapa *cyapa);
0436 int cyapa_pip_irq_handler(struct cyapa *cyapa);
0437
0438
0439 extern u8 pip_read_sys_info[];
0440 extern u8 pip_bl_read_app_info[];
0441 extern const char product_id[];
0442 extern const struct cyapa_dev_ops cyapa_gen3_ops;
0443 extern const struct cyapa_dev_ops cyapa_gen5_ops;
0444 extern const struct cyapa_dev_ops cyapa_gen6_ops;
0445
0446 #endif