input/misc/iqs7222.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Azoteq IQS7222A/B/C Capacitive Touch Controller
0004  *
0005  * Copyright (C) 2022 Jeff LaBundy <jeff@labundy.com>
0006  */
0007
0008 #include <linux/bits.h>
0009 #include <linux/delay.h>
0010 #include <linux/device.h>
0011 #include <linux/err.h>
0012 #include <linux/gpio/consumer.h>
0013 #include <linux/i2c.h>
0014 #include <linux/input.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/kernel.h>
0017 #include <linux/ktime.h>
0018 #include <linux/module.h>
0019 #include <linux/of_device.h>
0020 #include <linux/property.h>
0021 #include <linux/slab.h>
0022 #include <asm/unaligned.h>
0023
0024 #define IQS7222_PROD_NUM            0x00
0025 #define IQS7222_PROD_NUM_A          840
0026 #define IQS7222_PROD_NUM_B          698
0027 #define IQS7222_PROD_NUM_C          863
0028
0029 #define IQS7222_SYS_STATUS          0x10
0030 #define IQS7222_SYS_STATUS_RESET        BIT(3)
0031 #define IQS7222_SYS_STATUS_ATI_ERROR        BIT(1)
0032 #define IQS7222_SYS_STATUS_ATI_ACTIVE       BIT(0)
0033
0034 #define IQS7222_CHAN_SETUP_0_REF_MODE_MASK  GENMASK(15, 14)
0035 #define IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW    BIT(15)
0036 #define IQS7222_CHAN_SETUP_0_REF_MODE_REF   BIT(14)
0037 #define IQS7222_CHAN_SETUP_0_CHAN_EN        BIT(8)
0038
0039 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK  GENMASK(2, 0)
0040 #define IQS7222_SLDR_SETUP_2_RES_MASK       GENMASK(15, 8)
0041 #define IQS7222_SLDR_SETUP_2_RES_SHIFT      8
0042 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0)
0043
0044 #define IQS7222_GPIO_SETUP_0_GPIO_EN        BIT(0)
0045
0046 #define IQS7222_SYS_SETUP           0xD0
0047 #define IQS7222_SYS_SETUP_INTF_MODE_MASK    GENMASK(7, 6)
0048 #define IQS7222_SYS_SETUP_INTF_MODE_TOUCH   BIT(7)
0049 #define IQS7222_SYS_SETUP_INTF_MODE_EVENT   BIT(6)
0050 #define IQS7222_SYS_SETUP_PWR_MODE_MASK     GENMASK(5, 4)
0051 #define IQS7222_SYS_SETUP_PWR_MODE_AUTO     IQS7222_SYS_SETUP_PWR_MODE_MASK
0052 #define IQS7222_SYS_SETUP_REDO_ATI      BIT(2)
0053 #define IQS7222_SYS_SETUP_ACK_RESET     BIT(0)
0054
0055 #define IQS7222_EVENT_MASK_ATI          BIT(12)
0056 #define IQS7222_EVENT_MASK_SLDR         BIT(10)
0057 #define IQS7222_EVENT_MASK_TOUCH        BIT(1)
0058 #define IQS7222_EVENT_MASK_PROX         BIT(0)
0059
0060 #define IQS7222_COMMS_HOLD          BIT(0)
0061 #define IQS7222_COMMS_ERROR         0xEEEE
0062 #define IQS7222_COMMS_RETRY_MS          50
0063 #define IQS7222_COMMS_TIMEOUT_MS        100
0064 #define IQS7222_RESET_TIMEOUT_MS        250
0065 #define IQS7222_ATI_TIMEOUT_MS          2000
0066
0067 #define IQS7222_MAX_COLS_STAT           8
0068 #define IQS7222_MAX_COLS_CYCLE          3
0069 #define IQS7222_MAX_COLS_GLBL           3
0070 #define IQS7222_MAX_COLS_BTN            3
0071 #define IQS7222_MAX_COLS_CHAN           6
0072 #define IQS7222_MAX_COLS_FILT           2
0073 #define IQS7222_MAX_COLS_SLDR           11
0074 #define IQS7222_MAX_COLS_GPIO           3
0075 #define IQS7222_MAX_COLS_SYS            13
0076
0077 #define IQS7222_MAX_CHAN            20
0078 #define IQS7222_MAX_SLDR            2
0079
0080 #define IQS7222_NUM_RETRIES         5
0081 #define IQS7222_REG_OFFSET          0x100
0082
0083 enum iqs7222_reg_key_id {
0084     IQS7222_REG_KEY_NONE,
0085     IQS7222_REG_KEY_PROX,
0086     IQS7222_REG_KEY_TOUCH,
0087     IQS7222_REG_KEY_DEBOUNCE,
0088     IQS7222_REG_KEY_TAP,
0089     IQS7222_REG_KEY_AXIAL,
0090     IQS7222_REG_KEY_WHEEL,
0091     IQS7222_REG_KEY_NO_WHEEL,
0092     IQS7222_REG_KEY_RESERVED
0093 };
0094
0095 enum iqs7222_reg_grp_id {
0096     IQS7222_REG_GRP_STAT,
0097     IQS7222_REG_GRP_FILT,
0098     IQS7222_REG_GRP_CYCLE,
0099     IQS7222_REG_GRP_GLBL,
0100     IQS7222_REG_GRP_BTN,
0101     IQS7222_REG_GRP_CHAN,
0102     IQS7222_REG_GRP_SLDR,
0103     IQS7222_REG_GRP_GPIO,
0104     IQS7222_REG_GRP_SYS,
0105     IQS7222_NUM_REG_GRPS
0106 };
0107
0108 static const char * const iqs7222_reg_grp_names[] = {
0109     [IQS7222_REG_GRP_CYCLE] = "cycle",
0110     [IQS7222_REG_GRP_CHAN] = "channel",
0111     [IQS7222_REG_GRP_SLDR] = "slider",
0112     [IQS7222_REG_GRP_GPIO] = "gpio",
0113 };
0114
0115 static const unsigned int iqs7222_max_cols[] = {
0116     [IQS7222_REG_GRP_STAT] = IQS7222_MAX_COLS_STAT,
0117     [IQS7222_REG_GRP_CYCLE] = IQS7222_MAX_COLS_CYCLE,
0118     [IQS7222_REG_GRP_GLBL] = IQS7222_MAX_COLS_GLBL,
0119     [IQS7222_REG_GRP_BTN] = IQS7222_MAX_COLS_BTN,
0120     [IQS7222_REG_GRP_CHAN] = IQS7222_MAX_COLS_CHAN,
0121     [IQS7222_REG_GRP_FILT] = IQS7222_MAX_COLS_FILT,
0122     [IQS7222_REG_GRP_SLDR] = IQS7222_MAX_COLS_SLDR,
0123     [IQS7222_REG_GRP_GPIO] = IQS7222_MAX_COLS_GPIO,
0124     [IQS7222_REG_GRP_SYS] = IQS7222_MAX_COLS_SYS,
0125 };
0126
0127 static const unsigned int iqs7222_gpio_links[] = { 2, 5, 6, };
0128
0129 struct iqs7222_event_desc {
0130     const char *name;
0131     u16 mask;
0132     u16 val;
0133     u16 enable;
0134     enum iqs7222_reg_key_id reg_key;
0135 };
0136
0137 static const struct iqs7222_event_desc iqs7222_kp_events[] = {
0138     {
0139         .name = "event-prox",
0140         .enable = IQS7222_EVENT_MASK_PROX,
0141         .reg_key = IQS7222_REG_KEY_PROX,
0142     },
0143     {
0144         .name = "event-touch",
0145         .enable = IQS7222_EVENT_MASK_TOUCH,
0146         .reg_key = IQS7222_REG_KEY_TOUCH,
0147     },
0148 };
0149
0150 static const struct iqs7222_event_desc iqs7222_sl_events[] = {
0151     { .name = "event-press", },
0152     {
0153         .name = "event-tap",
0154         .mask = BIT(0),
0155         .val = BIT(0),
0156         .enable = BIT(0),
0157         .reg_key = IQS7222_REG_KEY_TAP,
0158     },
0159     {
0160         .name = "event-swipe-pos",
0161         .mask = BIT(5) | BIT(1),
0162         .val = BIT(1),
0163         .enable = BIT(1),
0164         .reg_key = IQS7222_REG_KEY_AXIAL,
0165     },
0166     {
0167         .name = "event-swipe-neg",
0168         .mask = BIT(5) | BIT(1),
0169         .val = BIT(5) | BIT(1),
0170         .enable = BIT(1),
0171         .reg_key = IQS7222_REG_KEY_AXIAL,
0172     },
0173     {
0174         .name = "event-flick-pos",
0175         .mask = BIT(5) | BIT(2),
0176         .val = BIT(2),
0177         .enable = BIT(2),
0178         .reg_key = IQS7222_REG_KEY_AXIAL,
0179     },
0180     {
0181         .name = "event-flick-neg",
0182         .mask = BIT(5) | BIT(2),
0183         .val = BIT(5) | BIT(2),
0184         .enable = BIT(2),
0185         .reg_key = IQS7222_REG_KEY_AXIAL,
0186     },
0187 };
0188
0189 struct iqs7222_reg_grp_desc {
0190     u16 base;
0191     int num_row;
0192     int num_col;
0193 };
0194
0195 struct iqs7222_dev_desc {
0196     u16 prod_num;
0197     u16 fw_major;
0198     u16 fw_minor;
0199     u16 sldr_res;
0200     u16 touch_link;
0201     u16 wheel_enable;
0202     int allow_offset;
0203     int event_offset;
0204     int comms_offset;
0205     struct iqs7222_reg_grp_desc reg_grps[IQS7222_NUM_REG_GRPS];
0206 };
0207
0208 static const struct iqs7222_dev_desc iqs7222_devs[] = {
0209     {
0210         .prod_num = IQS7222_PROD_NUM_A,
0211         .fw_major = 1,
0212         .fw_minor = 12,
0213         .sldr_res = U8_MAX * 16,
0214         .touch_link = 1768,
0215         .allow_offset = 9,
0216         .event_offset = 10,
0217         .comms_offset = 12,
0218         .reg_grps = {
0219             [IQS7222_REG_GRP_STAT] = {
0220                 .base = IQS7222_SYS_STATUS,
0221                 .num_row = 1,
0222                 .num_col = 8,
0223             },
0224             [IQS7222_REG_GRP_CYCLE] = {
0225                 .base = 0x8000,
0226                 .num_row = 7,
0227                 .num_col = 3,
0228             },
0229             [IQS7222_REG_GRP_GLBL] = {
0230                 .base = 0x8700,
0231                 .num_row = 1,
0232                 .num_col = 3,
0233             },
0234             [IQS7222_REG_GRP_BTN] = {
0235                 .base = 0x9000,
0236                 .num_row = 12,
0237                 .num_col = 3,
0238             },
0239             [IQS7222_REG_GRP_CHAN] = {
0240                 .base = 0xA000,
0241                 .num_row = 12,
0242                 .num_col = 6,
0243             },
0244             [IQS7222_REG_GRP_FILT] = {
0245                 .base = 0xAC00,
0246                 .num_row = 1,
0247                 .num_col = 2,
0248             },
0249             [IQS7222_REG_GRP_SLDR] = {
0250                 .base = 0xB000,
0251                 .num_row = 2,
0252                 .num_col = 11,
0253             },
0254             [IQS7222_REG_GRP_GPIO] = {
0255                 .base = 0xC000,
0256                 .num_row = 1,
0257                 .num_col = 3,
0258             },
0259             [IQS7222_REG_GRP_SYS] = {
0260                 .base = IQS7222_SYS_SETUP,
0261                 .num_row = 1,
0262                 .num_col = 13,
0263             },
0264         },
0265     },
0266     {
0267         .prod_num = IQS7222_PROD_NUM_B,
0268         .fw_major = 1,
0269         .fw_minor = 43,
0270         .event_offset = 10,
0271         .comms_offset = 11,
0272         .reg_grps = {
0273             [IQS7222_REG_GRP_STAT] = {
0274                 .base = IQS7222_SYS_STATUS,
0275                 .num_row = 1,
0276                 .num_col = 6,
0277             },
0278             [IQS7222_REG_GRP_CYCLE] = {
0279                 .base = 0x8000,
0280                 .num_row = 10,
0281                 .num_col = 2,
0282             },
0283             [IQS7222_REG_GRP_GLBL] = {
0284                 .base = 0x8A00,
0285                 .num_row = 1,
0286                 .num_col = 3,
0287             },
0288             [IQS7222_REG_GRP_BTN] = {
0289                 .base = 0x9000,
0290                 .num_row = 20,
0291                 .num_col = 2,
0292             },
0293             [IQS7222_REG_GRP_CHAN] = {
0294                 .base = 0xB000,
0295                 .num_row = 20,
0296                 .num_col = 4,
0297             },
0298             [IQS7222_REG_GRP_FILT] = {
0299                 .base = 0xC400,
0300                 .num_row = 1,
0301                 .num_col = 2,
0302             },
0303             [IQS7222_REG_GRP_SYS] = {
0304                 .base = IQS7222_SYS_SETUP,
0305                 .num_row = 1,
0306                 .num_col = 13,
0307             },
0308         },
0309     },
0310     {
0311         .prod_num = IQS7222_PROD_NUM_B,
0312         .fw_major = 1,
0313         .fw_minor = 27,
0314         .reg_grps = {
0315             [IQS7222_REG_GRP_STAT] = {
0316                 .base = IQS7222_SYS_STATUS,
0317                 .num_row = 1,
0318                 .num_col = 6,
0319             },
0320             [IQS7222_REG_GRP_CYCLE] = {
0321                 .base = 0x8000,
0322                 .num_row = 10,
0323                 .num_col = 2,
0324             },
0325             [IQS7222_REG_GRP_GLBL] = {
0326                 .base = 0x8A00,
0327                 .num_row = 1,
0328                 .num_col = 3,
0329             },
0330             [IQS7222_REG_GRP_BTN] = {
0331                 .base = 0x9000,
0332                 .num_row = 20,
0333                 .num_col = 2,
0334             },
0335             [IQS7222_REG_GRP_CHAN] = {
0336                 .base = 0xB000,
0337                 .num_row = 20,
0338                 .num_col = 4,
0339             },
0340             [IQS7222_REG_GRP_FILT] = {
0341                 .base = 0xC400,
0342                 .num_row = 1,
0343                 .num_col = 2,
0344             },
0345             [IQS7222_REG_GRP_SYS] = {
0346                 .base = IQS7222_SYS_SETUP,
0347                 .num_row = 1,
0348                 .num_col = 10,
0349             },
0350         },
0351     },
0352     {
0353         .prod_num = IQS7222_PROD_NUM_C,
0354         .fw_major = 2,
0355         .fw_minor = 6,
0356         .sldr_res = U16_MAX,
0357         .touch_link = 1686,
0358         .wheel_enable = BIT(3),
0359         .event_offset = 9,
0360         .comms_offset = 10,
0361         .reg_grps = {
0362             [IQS7222_REG_GRP_STAT] = {
0363                 .base = IQS7222_SYS_STATUS,
0364                 .num_row = 1,
0365                 .num_col = 6,
0366             },
0367             [IQS7222_REG_GRP_CYCLE] = {
0368                 .base = 0x8000,
0369                 .num_row = 5,
0370                 .num_col = 3,
0371             },
0372             [IQS7222_REG_GRP_GLBL] = {
0373                 .base = 0x8500,
0374                 .num_row = 1,
0375                 .num_col = 3,
0376             },
0377             [IQS7222_REG_GRP_BTN] = {
0378                 .base = 0x9000,
0379                 .num_row = 10,
0380                 .num_col = 3,
0381             },
0382             [IQS7222_REG_GRP_CHAN] = {
0383                 .base = 0xA000,
0384                 .num_row = 10,
0385                 .num_col = 6,
0386             },
0387             [IQS7222_REG_GRP_FILT] = {
0388                 .base = 0xAA00,
0389                 .num_row = 1,
0390                 .num_col = 2,
0391             },
0392             [IQS7222_REG_GRP_SLDR] = {
0393                 .base = 0xB000,
0394                 .num_row = 2,
0395                 .num_col = 10,
0396             },
0397             [IQS7222_REG_GRP_GPIO] = {
0398                 .base = 0xC000,
0399                 .num_row = 3,
0400                 .num_col = 3,
0401             },
0402             [IQS7222_REG_GRP_SYS] = {
0403                 .base = IQS7222_SYS_SETUP,
0404                 .num_row = 1,
0405                 .num_col = 12,
0406             },
0407         },
0408     },
0409     {
0410         .prod_num = IQS7222_PROD_NUM_C,
0411         .fw_major = 1,
0412         .fw_minor = 13,
0413         .sldr_res = U16_MAX,
0414         .touch_link = 1674,
0415         .wheel_enable = BIT(3),
0416         .event_offset = 9,
0417         .comms_offset = 10,
0418         .reg_grps = {
0419             [IQS7222_REG_GRP_STAT] = {
0420                 .base = IQS7222_SYS_STATUS,
0421                 .num_row = 1,
0422                 .num_col = 6,
0423             },
0424             [IQS7222_REG_GRP_CYCLE] = {
0425                 .base = 0x8000,
0426                 .num_row = 5,
0427                 .num_col = 3,
0428             },
0429             [IQS7222_REG_GRP_GLBL] = {
0430                 .base = 0x8500,
0431                 .num_row = 1,
0432                 .num_col = 3,
0433             },
0434             [IQS7222_REG_GRP_BTN] = {
0435                 .base = 0x9000,
0436                 .num_row = 10,
0437                 .num_col = 3,
0438             },
0439             [IQS7222_REG_GRP_CHAN] = {
0440                 .base = 0xA000,
0441                 .num_row = 10,
0442                 .num_col = 6,
0443             },
0444             [IQS7222_REG_GRP_FILT] = {
0445                 .base = 0xAA00,
0446                 .num_row = 1,
0447                 .num_col = 2,
0448             },
0449             [IQS7222_REG_GRP_SLDR] = {
0450                 .base = 0xB000,
0451                 .num_row = 2,
0452                 .num_col = 10,
0453             },
0454             [IQS7222_REG_GRP_GPIO] = {
0455                 .base = 0xC000,
0456                 .num_row = 1,
0457                 .num_col = 3,
0458             },
0459             [IQS7222_REG_GRP_SYS] = {
0460                 .base = IQS7222_SYS_SETUP,
0461                 .num_row = 1,
0462                 .num_col = 11,
0463             },
0464         },
0465     },
0466 };
0467
0468 struct iqs7222_prop_desc {
0469     const char *name;
0470     enum iqs7222_reg_grp_id reg_grp;
0471     enum iqs7222_reg_key_id reg_key;
0472     int reg_offset;
0473     int reg_shift;
0474     int reg_width;
0475     int val_pitch;
0476     int val_min;
0477     int val_max;
0478     bool invert;
0479     const char *label;
0480 };
0481
0482 static const struct iqs7222_prop_desc iqs7222_props[] = {
0483     {
0484         .name = "azoteq,conv-period",
0485         .reg_grp = IQS7222_REG_GRP_CYCLE,
0486         .reg_offset = 0,
0487         .reg_shift = 8,
0488         .reg_width = 8,
0489         .label = "conversion period",
0490     },
0491     {
0492         .name = "azoteq,conv-frac",
0493         .reg_grp = IQS7222_REG_GRP_CYCLE,
0494         .reg_offset = 0,
0495         .reg_shift = 0,
0496         .reg_width = 8,
0497         .label = "conversion frequency fractional divider",
0498     },
0499     {
0500         .name = "azoteq,rx-float-inactive",
0501         .reg_grp = IQS7222_REG_GRP_CYCLE,
0502         .reg_offset = 1,
0503         .reg_shift = 6,
0504         .reg_width = 1,
0505         .invert = true,
0506     },
0507     {
0508         .name = "azoteq,dead-time-enable",
0509         .reg_grp = IQS7222_REG_GRP_CYCLE,
0510         .reg_offset = 1,
0511         .reg_shift = 5,
0512         .reg_width = 1,
0513     },
0514     {
0515         .name = "azoteq,tx-freq-fosc",
0516         .reg_grp = IQS7222_REG_GRP_CYCLE,
0517         .reg_offset = 1,
0518         .reg_shift = 4,
0519         .reg_width = 1,
0520     },
0521     {
0522         .name = "azoteq,vbias-enable",
0523         .reg_grp = IQS7222_REG_GRP_CYCLE,
0524         .reg_offset = 1,
0525         .reg_shift = 3,
0526         .reg_width = 1,
0527     },
0528     {
0529         .name = "azoteq,sense-mode",
0530         .reg_grp = IQS7222_REG_GRP_CYCLE,
0531         .reg_offset = 1,
0532         .reg_shift = 0,
0533         .reg_width = 3,
0534         .val_max = 3,
0535         .label = "sensing mode",
0536     },
0537     {
0538         .name = "azoteq,iref-enable",
0539         .reg_grp = IQS7222_REG_GRP_CYCLE,
0540         .reg_offset = 2,
0541         .reg_shift = 10,
0542         .reg_width = 1,
0543     },
0544     {
0545         .name = "azoteq,iref-level",
0546         .reg_grp = IQS7222_REG_GRP_CYCLE,
0547         .reg_offset = 2,
0548         .reg_shift = 4,
0549         .reg_width = 4,
0550         .label = "current reference level",
0551     },
0552     {
0553         .name = "azoteq,iref-trim",
0554         .reg_grp = IQS7222_REG_GRP_CYCLE,
0555         .reg_offset = 2,
0556         .reg_shift = 0,
0557         .reg_width = 4,
0558         .label = "current reference trim",
0559     },
0560     {
0561         .name = "azoteq,max-counts",
0562         .reg_grp = IQS7222_REG_GRP_GLBL,
0563         .reg_offset = 0,
0564         .reg_shift = 13,
0565         .reg_width = 2,
0566         .label = "maximum counts",
0567     },
0568     {
0569         .name = "azoteq,auto-mode",
0570         .reg_grp = IQS7222_REG_GRP_GLBL,
0571         .reg_offset = 0,
0572         .reg_shift = 2,
0573         .reg_width = 2,
0574         .label = "number of conversions",
0575     },
0576     {
0577         .name = "azoteq,ati-frac-div-fine",
0578         .reg_grp = IQS7222_REG_GRP_GLBL,
0579         .reg_offset = 1,
0580         .reg_shift = 9,
0581         .reg_width = 5,
0582         .label = "ATI fine fractional divider",
0583     },
0584     {
0585         .name = "azoteq,ati-frac-div-coarse",
0586         .reg_grp = IQS7222_REG_GRP_GLBL,
0587         .reg_offset = 1,
0588         .reg_shift = 0,
0589         .reg_width = 5,
0590         .label = "ATI coarse fractional divider",
0591     },
0592     {
0593         .name = "azoteq,ati-comp-select",
0594         .reg_grp = IQS7222_REG_GRP_GLBL,
0595         .reg_offset = 2,
0596         .reg_shift = 0,
0597         .reg_width = 10,
0598         .label = "ATI compensation selection",
0599     },
0600     {
0601         .name = "azoteq,ati-band",
0602         .reg_grp = IQS7222_REG_GRP_CHAN,
0603         .reg_offset = 0,
0604         .reg_shift = 12,
0605         .reg_width = 2,
0606         .label = "ATI band",
0607     },
0608     {
0609         .name = "azoteq,global-halt",
0610         .reg_grp = IQS7222_REG_GRP_CHAN,
0611         .reg_offset = 0,
0612         .reg_shift = 11,
0613         .reg_width = 1,
0614     },
0615     {
0616         .name = "azoteq,invert-enable",
0617         .reg_grp = IQS7222_REG_GRP_CHAN,
0618         .reg_offset = 0,
0619         .reg_shift = 10,
0620         .reg_width = 1,
0621     },
0622     {
0623         .name = "azoteq,dual-direction",
0624         .reg_grp = IQS7222_REG_GRP_CHAN,
0625         .reg_offset = 0,
0626         .reg_shift = 9,
0627         .reg_width = 1,
0628     },
0629     {
0630         .name = "azoteq,samp-cap-double",
0631         .reg_grp = IQS7222_REG_GRP_CHAN,
0632         .reg_offset = 0,
0633         .reg_shift = 3,
0634         .reg_width = 1,
0635     },
0636     {
0637         .name = "azoteq,vref-half",
0638         .reg_grp = IQS7222_REG_GRP_CHAN,
0639         .reg_offset = 0,
0640         .reg_shift = 2,
0641         .reg_width = 1,
0642     },
0643     {
0644         .name = "azoteq,proj-bias",
0645         .reg_grp = IQS7222_REG_GRP_CHAN,
0646         .reg_offset = 0,
0647         .reg_shift = 0,
0648         .reg_width = 2,
0649         .label = "projected bias current",
0650     },
0651     {
0652         .name = "azoteq,ati-target",
0653         .reg_grp = IQS7222_REG_GRP_CHAN,
0654         .reg_offset = 1,
0655         .reg_shift = 8,
0656         .reg_width = 8,
0657         .val_pitch = 8,
0658         .label = "ATI target",
0659     },
0660     {
0661         .name = "azoteq,ati-base",
0662         .reg_grp = IQS7222_REG_GRP_CHAN,
0663         .reg_offset = 1,
0664         .reg_shift = 3,
0665         .reg_width = 5,
0666         .val_pitch = 16,
0667         .label = "ATI base",
0668     },
0669     {
0670         .name = "azoteq,ati-mode",
0671         .reg_grp = IQS7222_REG_GRP_CHAN,
0672         .reg_offset = 1,
0673         .reg_shift = 0,
0674         .reg_width = 3,
0675         .val_max = 5,
0676         .label = "ATI mode",
0677     },
0678     {
0679         .name = "azoteq,ati-frac-div-fine",
0680         .reg_grp = IQS7222_REG_GRP_CHAN,
0681         .reg_offset = 2,
0682         .reg_shift = 9,
0683         .reg_width = 5,
0684         .label = "ATI fine fractional divider",
0685     },
0686     {
0687         .name = "azoteq,ati-frac-mult-coarse",
0688         .reg_grp = IQS7222_REG_GRP_CHAN,
0689         .reg_offset = 2,
0690         .reg_shift = 5,
0691         .reg_width = 4,
0692         .label = "ATI coarse fractional multiplier",
0693     },
0694     {
0695         .name = "azoteq,ati-frac-div-coarse",
0696         .reg_grp = IQS7222_REG_GRP_CHAN,
0697         .reg_offset = 2,
0698         .reg_shift = 0,
0699         .reg_width = 5,
0700         .label = "ATI coarse fractional divider",
0701     },
0702     {
0703         .name = "azoteq,ati-comp-div",
0704         .reg_grp = IQS7222_REG_GRP_CHAN,
0705         .reg_offset = 3,
0706         .reg_shift = 11,
0707         .reg_width = 5,
0708         .label = "ATI compensation divider",
0709     },
0710     {
0711         .name = "azoteq,ati-comp-select",
0712         .reg_grp = IQS7222_REG_GRP_CHAN,
0713         .reg_offset = 3,
0714         .reg_shift = 0,
0715         .reg_width = 10,
0716         .label = "ATI compensation selection",
0717     },
0718     {
0719         .name = "azoteq,debounce-exit",
0720         .reg_grp = IQS7222_REG_GRP_BTN,
0721         .reg_key = IQS7222_REG_KEY_DEBOUNCE,
0722         .reg_offset = 0,
0723         .reg_shift = 12,
0724         .reg_width = 4,
0725         .label = "debounce exit factor",
0726     },
0727     {
0728         .name = "azoteq,debounce-enter",
0729         .reg_grp = IQS7222_REG_GRP_BTN,
0730         .reg_key = IQS7222_REG_KEY_DEBOUNCE,
0731         .reg_offset = 0,
0732         .reg_shift = 8,
0733         .reg_width = 4,
0734         .label = "debounce entrance factor",
0735     },
0736     {
0737         .name = "azoteq,thresh",
0738         .reg_grp = IQS7222_REG_GRP_BTN,
0739         .reg_key = IQS7222_REG_KEY_PROX,
0740         .reg_offset = 0,
0741         .reg_shift = 0,
0742         .reg_width = 8,
0743         .val_max = 127,
0744         .label = "threshold",
0745     },
0746     {
0747         .name = "azoteq,thresh",
0748         .reg_grp = IQS7222_REG_GRP_BTN,
0749         .reg_key = IQS7222_REG_KEY_TOUCH,
0750         .reg_offset = 1,
0751         .reg_shift = 0,
0752         .reg_width = 8,
0753         .label = "threshold",
0754     },
0755     {
0756         .name = "azoteq,hyst",
0757         .reg_grp = IQS7222_REG_GRP_BTN,
0758         .reg_key = IQS7222_REG_KEY_TOUCH,
0759         .reg_offset = 1,
0760         .reg_shift = 8,
0761         .reg_width = 8,
0762         .label = "hysteresis",
0763     },
0764     {
0765         .name = "azoteq,lta-beta-lp",
0766         .reg_grp = IQS7222_REG_GRP_FILT,
0767         .reg_offset = 0,
0768         .reg_shift = 12,
0769         .reg_width = 4,
0770         .label = "low-power mode long-term average beta",
0771     },
0772     {
0773         .name = "azoteq,lta-beta-np",
0774         .reg_grp = IQS7222_REG_GRP_FILT,
0775         .reg_offset = 0,
0776         .reg_shift = 8,
0777         .reg_width = 4,
0778         .label = "normal-power mode long-term average beta",
0779     },
0780     {
0781         .name = "azoteq,counts-beta-lp",
0782         .reg_grp = IQS7222_REG_GRP_FILT,
0783         .reg_offset = 0,
0784         .reg_shift = 4,
0785         .reg_width = 4,
0786         .label = "low-power mode counts beta",
0787     },
0788     {
0789         .name = "azoteq,counts-beta-np",
0790         .reg_grp = IQS7222_REG_GRP_FILT,
0791         .reg_offset = 0,
0792         .reg_shift = 0,
0793         .reg_width = 4,
0794         .label = "normal-power mode counts beta",
0795     },
0796     {
0797         .name = "azoteq,lta-fast-beta-lp",
0798         .reg_grp = IQS7222_REG_GRP_FILT,
0799         .reg_offset = 1,
0800         .reg_shift = 4,
0801         .reg_width = 4,
0802         .label = "low-power mode long-term average fast beta",
0803     },
0804     {
0805         .name = "azoteq,lta-fast-beta-np",
0806         .reg_grp = IQS7222_REG_GRP_FILT,
0807         .reg_offset = 1,
0808         .reg_shift = 0,
0809         .reg_width = 4,
0810         .label = "normal-power mode long-term average fast beta",
0811     },
0812     {
0813         .name = "azoteq,lower-cal",
0814         .reg_grp = IQS7222_REG_GRP_SLDR,
0815         .reg_offset = 0,
0816         .reg_shift = 8,
0817         .reg_width = 8,
0818         .label = "lower calibration",
0819     },
0820     {
0821         .name = "azoteq,static-beta",
0822         .reg_grp = IQS7222_REG_GRP_SLDR,
0823         .reg_key = IQS7222_REG_KEY_NO_WHEEL,
0824         .reg_offset = 0,
0825         .reg_shift = 6,
0826         .reg_width = 1,
0827     },
0828     {
0829         .name = "azoteq,bottom-beta",
0830         .reg_grp = IQS7222_REG_GRP_SLDR,
0831         .reg_key = IQS7222_REG_KEY_NO_WHEEL,
0832         .reg_offset = 0,
0833         .reg_shift = 3,
0834         .reg_width = 3,
0835         .label = "bottom beta",
0836     },
0837     {
0838         .name = "azoteq,static-beta",
0839         .reg_grp = IQS7222_REG_GRP_SLDR,
0840         .reg_key = IQS7222_REG_KEY_WHEEL,
0841         .reg_offset = 0,
0842         .reg_shift = 7,
0843         .reg_width = 1,
0844     },
0845     {
0846         .name = "azoteq,bottom-beta",
0847         .reg_grp = IQS7222_REG_GRP_SLDR,
0848         .reg_key = IQS7222_REG_KEY_WHEEL,
0849         .reg_offset = 0,
0850         .reg_shift = 4,
0851         .reg_width = 3,
0852         .label = "bottom beta",
0853     },
0854     {
0855         .name = "azoteq,bottom-speed",
0856         .reg_grp = IQS7222_REG_GRP_SLDR,
0857         .reg_offset = 1,
0858         .reg_shift = 8,
0859         .reg_width = 8,
0860         .label = "bottom speed",
0861     },
0862     {
0863         .name = "azoteq,upper-cal",
0864         .reg_grp = IQS7222_REG_GRP_SLDR,
0865         .reg_offset = 1,
0866         .reg_shift = 0,
0867         .reg_width = 8,
0868         .label = "upper calibration",
0869     },
0870     {
0871         .name = "azoteq,gesture-max-ms",
0872         .reg_grp = IQS7222_REG_GRP_SLDR,
0873         .reg_key = IQS7222_REG_KEY_TAP,
0874         .reg_offset = 9,
0875         .reg_shift = 8,
0876         .reg_width = 8,
0877         .val_pitch = 4,
0878         .label = "maximum gesture time",
0879     },
0880     {
0881         .name = "azoteq,gesture-min-ms",
0882         .reg_grp = IQS7222_REG_GRP_SLDR,
0883         .reg_key = IQS7222_REG_KEY_TAP,
0884         .reg_offset = 9,
0885         .reg_shift = 3,
0886         .reg_width = 5,
0887         .val_pitch = 4,
0888         .label = "minimum gesture time",
0889     },
0890     {
0891         .name = "azoteq,gesture-dist",
0892         .reg_grp = IQS7222_REG_GRP_SLDR,
0893         .reg_key = IQS7222_REG_KEY_AXIAL,
0894         .reg_offset = 10,
0895         .reg_shift = 8,
0896         .reg_width = 8,
0897         .val_pitch = 16,
0898         .label = "gesture distance",
0899     },
0900     {
0901         .name = "azoteq,gesture-max-ms",
0902         .reg_grp = IQS7222_REG_GRP_SLDR,
0903         .reg_key = IQS7222_REG_KEY_AXIAL,
0904         .reg_offset = 10,
0905         .reg_shift = 0,
0906         .reg_width = 8,
0907         .val_pitch = 4,
0908         .label = "maximum gesture time",
0909     },
0910     {
0911         .name = "drive-open-drain",
0912         .reg_grp = IQS7222_REG_GRP_GPIO,
0913         .reg_offset = 0,
0914         .reg_shift = 1,
0915         .reg_width = 1,
0916     },
0917     {
0918         .name = "azoteq,timeout-ati-ms",
0919         .reg_grp = IQS7222_REG_GRP_SYS,
0920         .reg_offset = 1,
0921         .reg_shift = 0,
0922         .reg_width = 16,
0923         .val_pitch = 500,
0924         .label = "ATI error timeout",
0925     },
0926     {
0927         .name = "azoteq,rate-ati-ms",
0928         .reg_grp = IQS7222_REG_GRP_SYS,
0929         .reg_offset = 2,
0930         .reg_shift = 0,
0931         .reg_width = 16,
0932         .label = "ATI report rate",
0933     },
0934     {
0935         .name = "azoteq,timeout-np-ms",
0936         .reg_grp = IQS7222_REG_GRP_SYS,
0937         .reg_offset = 3,
0938         .reg_shift = 0,
0939         .reg_width = 16,
0940         .label = "normal-power mode timeout",
0941     },
0942     {
0943         .name = "azoteq,rate-np-ms",
0944         .reg_grp = IQS7222_REG_GRP_SYS,
0945         .reg_offset = 4,
0946         .reg_shift = 0,
0947         .reg_width = 16,
0948         .val_max = 3000,
0949         .label = "normal-power mode report rate",
0950     },
0951     {
0952         .name = "azoteq,timeout-lp-ms",
0953         .reg_grp = IQS7222_REG_GRP_SYS,
0954         .reg_offset = 5,
0955         .reg_shift = 0,
0956         .reg_width = 16,
0957         .label = "low-power mode timeout",
0958     },
0959     {
0960         .name = "azoteq,rate-lp-ms",
0961         .reg_grp = IQS7222_REG_GRP_SYS,
0962         .reg_offset = 6,
0963         .reg_shift = 0,
0964         .reg_width = 16,
0965         .val_max = 3000,
0966         .label = "low-power mode report rate",
0967     },
0968     {
0969         .name = "azoteq,timeout-ulp-ms",
0970         .reg_grp = IQS7222_REG_GRP_SYS,
0971         .reg_offset = 7,
0972         .reg_shift = 0,
0973         .reg_width = 16,
0974         .label = "ultra-low-power mode timeout",
0975     },
0976     {
0977         .name = "azoteq,rate-ulp-ms",
0978         .reg_grp = IQS7222_REG_GRP_SYS,
0979         .reg_offset = 8,
0980         .reg_shift = 0,
0981         .reg_width = 16,
0982         .val_max = 3000,
0983         .label = "ultra-low-power mode report rate",
0984     },
0985 };
0986
0987 struct iqs7222_private {
0988     const struct iqs7222_dev_desc *dev_desc;
0989     struct gpio_desc *reset_gpio;
0990     struct gpio_desc *irq_gpio;
0991     struct i2c_client *client;
0992     struct input_dev *keypad;
0993     unsigned int kp_type[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)];
0994     unsigned int kp_code[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)];
0995     unsigned int sl_code[IQS7222_MAX_SLDR][ARRAY_SIZE(iqs7222_sl_events)];
0996     unsigned int sl_axis[IQS7222_MAX_SLDR];
0997     u16 cycle_setup[IQS7222_MAX_CHAN / 2][IQS7222_MAX_COLS_CYCLE];
0998     u16 glbl_setup[IQS7222_MAX_COLS_GLBL];
0999     u16 btn_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_BTN];
1000     u16 chan_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_CHAN];
1001     u16 filt_setup[IQS7222_MAX_COLS_FILT];
1002     u16 sldr_setup[IQS7222_MAX_SLDR][IQS7222_MAX_COLS_SLDR];
1003     u16 gpio_setup[ARRAY_SIZE(iqs7222_gpio_links)][IQS7222_MAX_COLS_GPIO];
1004     u16 sys_setup[IQS7222_MAX_COLS_SYS];
1005 };
1006
1007 static u16 *iqs7222_setup(struct iqs7222_private *iqs7222,
1008               enum iqs7222_reg_grp_id reg_grp, int row)
1009 {
1010     switch (reg_grp) {
1011     case IQS7222_REG_GRP_CYCLE:
1012         return iqs7222->cycle_setup[row];
1013
1014     case IQS7222_REG_GRP_GLBL:
1015         return iqs7222->glbl_setup;
1016
1017     case IQS7222_REG_GRP_BTN:
1018         return iqs7222->btn_setup[row];
1019
1020     case IQS7222_REG_GRP_CHAN:
1021         return iqs7222->chan_setup[row];
1022
1023     case IQS7222_REG_GRP_FILT:
1024         return iqs7222->filt_setup;
1025
1026     case IQS7222_REG_GRP_SLDR:
1027         return iqs7222->sldr_setup[row];
1028
1029     case IQS7222_REG_GRP_GPIO:
1030         return iqs7222->gpio_setup[row];
1031
1032     case IQS7222_REG_GRP_SYS:
1033         return iqs7222->sys_setup;
1034
1035     default:
1036         return NULL;
1037     }
1038 }
1039
1040 static int iqs7222_irq_poll(struct iqs7222_private *iqs7222, u16 timeout_ms)
1041 {
1042     ktime_t irq_timeout = ktime_add_ms(ktime_get(), timeout_ms);
1043     int ret;
1044
1045     do {
1046         usleep_range(1000, 1100);
1047
1048         ret = gpiod_get_value_cansleep(iqs7222->irq_gpio);
1049         if (ret < 0)
1050             return ret;
1051         else if (ret > 0)
1052             return 0;
1053     } while (ktime_compare(ktime_get(), irq_timeout) < 0);
1054
1055     return -EBUSY;
1056 }
1057
1058 static int iqs7222_hard_reset(struct iqs7222_private *iqs7222)
1059 {
1060     struct i2c_client *client = iqs7222->client;
1061     int error;
1062
1063     if (!iqs7222->reset_gpio)
1064         return 0;
1065
1066     gpiod_set_value_cansleep(iqs7222->reset_gpio, 1);
1067     usleep_range(1000, 1100);
1068
1069     gpiod_set_value_cansleep(iqs7222->reset_gpio, 0);
1070
1071     error = iqs7222_irq_poll(iqs7222, IQS7222_RESET_TIMEOUT_MS);
1072     if (error)
1073         dev_err(&client->dev, "Failed to reset device: %d\n", error);
1074
1075     return error;
1076 }
1077
1078 static int iqs7222_force_comms(struct iqs7222_private *iqs7222)
1079 {
1080     u8 msg_buf[] = { 0xFF, 0x00, };
1081     int ret;
1082
1083     /*
1084      * The device cannot communicate until it asserts its interrupt (RDY)
1085      * pin. Attempts to do so while RDY is deasserted return an ACK; how-
1086      * ever all write data is ignored, and all read data returns 0xEE.
1087      *
1088      * Unsolicited communication must be preceded by a special force com-
1089      * munication command, after which the device eventually asserts its
1090      * RDY pin and agrees to communicate.
1091      *
1092      * Regardless of whether communication is forced or the result of an
1093      * interrupt, the device automatically deasserts its RDY pin once it
1094      * detects an I2C stop condition, or a timeout expires.
1095      */
1096     ret = gpiod_get_value_cansleep(iqs7222->irq_gpio);
1097     if (ret < 0)
1098         return ret;
1099     else if (ret > 0)
1100         return 0;
1101
1102     ret = i2c_master_send(iqs7222->client, msg_buf, sizeof(msg_buf));
1103     if (ret < (int)sizeof(msg_buf)) {
1104         if (ret >= 0)
1105             ret = -EIO;
1106
1107         /*
1108          * The datasheet states that the host must wait to retry any
1109          * failed attempt to communicate over I2C.
1110          */
1111         msleep(IQS7222_COMMS_RETRY_MS);
1112         return ret;
1113     }
1114
1115     return iqs7222_irq_poll(iqs7222, IQS7222_COMMS_TIMEOUT_MS);
1116 }
1117
1118 static int iqs7222_read_burst(struct iqs7222_private *iqs7222,
1119                   u16 reg, void *val, u16 num_val)
1120 {
1121     u8 reg_buf[sizeof(__be16)];
1122     int ret, i;
1123     struct i2c_client *client = iqs7222->client;
1124     struct i2c_msg msg[] = {
1125         {
1126             .addr = client->addr,
1127             .flags = 0,
1128             .len = reg > U8_MAX ? sizeof(reg) : sizeof(u8),
1129             .buf = reg_buf,
1130         },
1131         {
1132             .addr = client->addr,
1133             .flags = I2C_M_RD,
1134             .len = num_val * sizeof(__le16),
1135             .buf = (u8 *)val,
1136         },
1137     };
1138
1139     if (reg > U8_MAX)
1140         put_unaligned_be16(reg, reg_buf);
1141     else
1142         *reg_buf = (u8)reg;
1143
1144     /*
1145      * The following loop protects against an edge case in which the RDY
1146      * pin is automatically deasserted just as the read is initiated. In
1147      * that case, the read must be retried using forced communication.
1148      */
1149     for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1150         ret = iqs7222_force_comms(iqs7222);
1151         if (ret < 0)
1152             continue;
1153
1154         ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
1155         if (ret < (int)ARRAY_SIZE(msg)) {
1156             if (ret >= 0)
1157                 ret = -EIO;
1158
1159             msleep(IQS7222_COMMS_RETRY_MS);
1160             continue;
1161         }
1162
1163         if (get_unaligned_le16(msg[1].buf) == IQS7222_COMMS_ERROR) {
1164             ret = -ENODATA;
1165             continue;
1166         }
1167
1168         ret = 0;
1169         break;
1170     }
1171
1172     /*
1173      * The following delay ensures the device has deasserted the RDY pin
1174      * following the I2C stop condition.
1175      */
1176     usleep_range(50, 100);
1177
1178     if (ret < 0)
1179         dev_err(&client->dev,
1180             "Failed to read from address 0x%04X: %d\n", reg, ret);
1181
1182     return ret;
1183 }
1184
1185 static int iqs7222_read_word(struct iqs7222_private *iqs7222, u16 reg, u16 *val)
1186 {
1187     __le16 val_buf;
1188     int error;
1189
1190     error = iqs7222_read_burst(iqs7222, reg, &val_buf, 1);
1191     if (error)
1192         return error;
1193
1194     *val = le16_to_cpu(val_buf);
1195
1196     return 0;
1197 }
1198
1199 static int iqs7222_write_burst(struct iqs7222_private *iqs7222,
1200                    u16 reg, const void *val, u16 num_val)
1201 {
1202     int reg_len = reg > U8_MAX ? sizeof(reg) : sizeof(u8);
1203     int val_len = num_val * sizeof(__le16);
1204     int msg_len = reg_len + val_len;
1205     int ret, i;
1206     struct i2c_client *client = iqs7222->client;
1207     u8 *msg_buf;
1208
1209     msg_buf = kzalloc(msg_len, GFP_KERNEL);
1210     if (!msg_buf)
1211         return -ENOMEM;
1212
1213     if (reg > U8_MAX)
1214         put_unaligned_be16(reg, msg_buf);
1215     else
1216         *msg_buf = (u8)reg;
1217
1218     memcpy(msg_buf + reg_len, val, val_len);
1219
1220     /*
1221      * The following loop protects against an edge case in which the RDY
1222      * pin is automatically asserted just before the force communication
1223      * command is sent.
1224      *
1225      * In that case, the subsequent I2C stop condition tricks the device
1226      * into preemptively deasserting the RDY pin and the command must be
1227      * sent again.
1228      */
1229     for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1230         ret = iqs7222_force_comms(iqs7222);
1231         if (ret < 0)
1232             continue;
1233
1234         ret = i2c_master_send(client, msg_buf, msg_len);
1235         if (ret < msg_len) {
1236             if (ret >= 0)
1237                 ret = -EIO;
1238
1239             msleep(IQS7222_COMMS_RETRY_MS);
1240             continue;
1241         }
1242
1243         ret = 0;
1244         break;
1245     }
1246
1247     kfree(msg_buf);
1248
1249     usleep_range(50, 100);
1250
1251     if (ret < 0)
1252         dev_err(&client->dev,
1253             "Failed to write to address 0x%04X: %d\n", reg, ret);
1254
1255     return ret;
1256 }
1257
1258 static int iqs7222_write_word(struct iqs7222_private *iqs7222, u16 reg, u16 val)
1259 {
1260     __le16 val_buf = cpu_to_le16(val);
1261
1262     return iqs7222_write_burst(iqs7222, reg, &val_buf, 1);
1263 }
1264
1265 static int iqs7222_ati_trigger(struct iqs7222_private *iqs7222)
1266 {
1267     struct i2c_client *client = iqs7222->client;
1268     ktime_t ati_timeout;
1269     u16 sys_status = 0;
1270     u16 sys_setup;
1271     int error, i;
1272
1273     /*
1274      * The reserved fields of the system setup register may have changed
1275      * as a result of other registers having been written. As such, read
1276      * the register's latest value to avoid unexpected behavior when the
1277      * register is written in the loop that follows.
1278      */
1279     error = iqs7222_read_word(iqs7222, IQS7222_SYS_SETUP, &sys_setup);
1280     if (error)
1281         return error;
1282
1283     sys_setup &= ~IQS7222_SYS_SETUP_INTF_MODE_MASK;
1284     sys_setup &= ~IQS7222_SYS_SETUP_PWR_MODE_MASK;
1285
1286     for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1287         /*
1288          * Trigger ATI from streaming and normal-power modes so that
1289          * the RDY pin continues to be asserted during ATI.
1290          */
1291         error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1292                        sys_setup |
1293                        IQS7222_SYS_SETUP_REDO_ATI);
1294         if (error)
1295             return error;
1296
1297         ati_timeout = ktime_add_ms(ktime_get(), IQS7222_ATI_TIMEOUT_MS);
1298
1299         do {
1300             error = iqs7222_irq_poll(iqs7222,
1301                          IQS7222_COMMS_TIMEOUT_MS);
1302             if (error)
1303                 continue;
1304
1305             error = iqs7222_read_word(iqs7222, IQS7222_SYS_STATUS,
1306                           &sys_status);
1307             if (error)
1308                 return error;
1309
1310             if (sys_status & IQS7222_SYS_STATUS_RESET)
1311                 return 0;
1312
1313             if (sys_status & IQS7222_SYS_STATUS_ATI_ERROR)
1314                 break;
1315
1316             if (sys_status & IQS7222_SYS_STATUS_ATI_ACTIVE)
1317                 continue;
1318
1319             /*
1320              * Use stream-in-touch mode if either slider reports
1321              * absolute position.
1322              */
1323             sys_setup |= test_bit(EV_ABS, iqs7222->keypad->evbit)
1324                    ? IQS7222_SYS_SETUP_INTF_MODE_TOUCH
1325                    : IQS7222_SYS_SETUP_INTF_MODE_EVENT;
1326             sys_setup |= IQS7222_SYS_SETUP_PWR_MODE_AUTO;
1327
1328             return iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1329                           sys_setup);
1330         } while (ktime_compare(ktime_get(), ati_timeout) < 0);
1331
1332         dev_err(&client->dev,
1333             "ATI attempt %d of %d failed with status 0x%02X, %s\n",
1334             i + 1, IQS7222_NUM_RETRIES, (u8)sys_status,
1335             i + 1 < IQS7222_NUM_RETRIES ? "retrying" : "stopping");
1336     }
1337
1338     return -ETIMEDOUT;
1339 }
1340
1341 static int iqs7222_dev_init(struct iqs7222_private *iqs7222, int dir)
1342 {
1343     const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1344     int comms_offset = dev_desc->comms_offset;
1345     int error, i, j, k;
1346
1347     /*
1348      * Acknowledge reset before writing any registers in case the device
1349      * suffers a spurious reset during initialization. Because this step
1350      * may change the reserved fields of the second filter beta register,
1351      * its cache must be updated.
1352      *
1353      * Writing the second filter beta register, in turn, may clobber the
1354      * system status register. As such, the filter beta register pair is
1355      * written first to protect against this hazard.
1356      */
1357     if (dir == WRITE) {
1358         u16 reg = dev_desc->reg_grps[IQS7222_REG_GRP_FILT].base + 1;
1359         u16 filt_setup;
1360
1361         error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1362                        iqs7222->sys_setup[0] |
1363                        IQS7222_SYS_SETUP_ACK_RESET);
1364         if (error)
1365             return error;
1366
1367         error = iqs7222_read_word(iqs7222, reg, &filt_setup);
1368         if (error)
1369             return error;
1370
1371         iqs7222->filt_setup[1] &= GENMASK(7, 0);
1372         iqs7222->filt_setup[1] |= (filt_setup & ~GENMASK(7, 0));
1373     }
1374
1375     /*
1376      * Take advantage of the stop-bit disable function, if available, to
1377      * save the trouble of having to reopen a communication window after
1378      * each burst read or write.
1379      */
1380     if (comms_offset) {
1381         u16 comms_setup;
1382
1383         error = iqs7222_read_word(iqs7222,
1384                       IQS7222_SYS_SETUP + comms_offset,
1385                       &comms_setup);
1386         if (error)
1387             return error;
1388
1389         error = iqs7222_write_word(iqs7222,
1390                        IQS7222_SYS_SETUP + comms_offset,
1391                        comms_setup | IQS7222_COMMS_HOLD);
1392         if (error)
1393             return error;
1394     }
1395
1396     for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) {
1397         int num_row = dev_desc->reg_grps[i].num_row;
1398         int num_col = dev_desc->reg_grps[i].num_col;
1399         u16 reg = dev_desc->reg_grps[i].base;
1400         __le16 *val_buf;
1401         u16 *val;
1402
1403         if (!num_col)
1404             continue;
1405
1406         val = iqs7222_setup(iqs7222, i, 0);
1407         if (!val)
1408             continue;
1409
1410         val_buf = kcalloc(num_col, sizeof(__le16), GFP_KERNEL);
1411         if (!val_buf)
1412             return -ENOMEM;
1413
1414         for (j = 0; j < num_row; j++) {
1415             switch (dir) {
1416             case READ:
1417                 error = iqs7222_read_burst(iqs7222, reg,
1418                                val_buf, num_col);
1419                 for (k = 0; k < num_col; k++)
1420                     val[k] = le16_to_cpu(val_buf[k]);
1421                 break;
1422
1423             case WRITE:
1424                 for (k = 0; k < num_col; k++)
1425                     val_buf[k] = cpu_to_le16(val[k]);
1426                 error = iqs7222_write_burst(iqs7222, reg,
1427                                 val_buf, num_col);
1428                 break;
1429
1430             default:
1431                 error = -EINVAL;
1432             }
1433
1434             if (error)
1435                 break;
1436
1437             reg += IQS7222_REG_OFFSET;
1438             val += iqs7222_max_cols[i];
1439         }
1440
1441         kfree(val_buf);
1442
1443         if (error)
1444             return error;
1445     }
1446
1447     if (comms_offset) {
1448         u16 comms_setup;
1449
1450         error = iqs7222_read_word(iqs7222,
1451                       IQS7222_SYS_SETUP + comms_offset,
1452                       &comms_setup);
1453         if (error)
1454             return error;
1455
1456         error = iqs7222_write_word(iqs7222,
1457                        IQS7222_SYS_SETUP + comms_offset,
1458                        comms_setup & ~IQS7222_COMMS_HOLD);
1459         if (error)
1460             return error;
1461     }
1462
1463     if (dir == READ)
1464         return 0;
1465
1466     return iqs7222_ati_trigger(iqs7222);
1467 }
1468
1469 static int iqs7222_dev_info(struct iqs7222_private *iqs7222)
1470 {
1471     struct i2c_client *client = iqs7222->client;
1472     bool prod_num_valid = false;
1473     __le16 dev_id[3];
1474     int error, i;
1475
1476     error = iqs7222_read_burst(iqs7222, IQS7222_PROD_NUM, dev_id,
1477                    ARRAY_SIZE(dev_id));
1478     if (error)
1479         return error;
1480
1481     for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) {
1482         if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num)
1483             continue;
1484
1485         prod_num_valid = true;
1486
1487         if (le16_to_cpu(dev_id[1]) < iqs7222_devs[i].fw_major)
1488             continue;
1489
1490         if (le16_to_cpu(dev_id[2]) < iqs7222_devs[i].fw_minor)
1491             continue;
1492
1493         iqs7222->dev_desc = &iqs7222_devs[i];
1494         return 0;
1495     }
1496
1497     if (prod_num_valid)
1498         dev_err(&client->dev, "Unsupported firmware revision: %u.%u\n",
1499             le16_to_cpu(dev_id[1]), le16_to_cpu(dev_id[2]));
1500     else
1501         dev_err(&client->dev, "Unrecognized product number: %u\n",
1502             le16_to_cpu(dev_id[0]));
1503
1504     return -EINVAL;
1505 }
1506
1507 static int iqs7222_gpio_select(struct iqs7222_private *iqs7222,
1508                    struct fwnode_handle *child_node,
1509                    int child_enable, u16 child_link)
1510 {
1511     const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1512     struct i2c_client *client = iqs7222->client;
1513     int num_gpio = dev_desc->reg_grps[IQS7222_REG_GRP_GPIO].num_row;
1514     int error, count, i;
1515     unsigned int gpio_sel[ARRAY_SIZE(iqs7222_gpio_links)];
1516
1517     if (!num_gpio)
1518         return 0;
1519
1520     if (!fwnode_property_present(child_node, "azoteq,gpio-select"))
1521         return 0;
1522
1523     count = fwnode_property_count_u32(child_node, "azoteq,gpio-select");
1524     if (count > num_gpio) {
1525         dev_err(&client->dev, "Invalid number of %s GPIOs\n",
1526             fwnode_get_name(child_node));
1527         return -EINVAL;
1528     } else if (count < 0) {
1529         dev_err(&client->dev, "Failed to count %s GPIOs: %d\n",
1530             fwnode_get_name(child_node), count);
1531         return count;
1532     }
1533
1534     error = fwnode_property_read_u32_array(child_node,
1535                            "azoteq,gpio-select",
1536                            gpio_sel, count);
1537     if (error) {
1538         dev_err(&client->dev, "Failed to read %s GPIOs: %d\n",
1539             fwnode_get_name(child_node), error);
1540         return error;
1541     }
1542
1543     for (i = 0; i < count; i++) {
1544         u16 *gpio_setup;
1545
1546         if (gpio_sel[i] >= num_gpio) {
1547             dev_err(&client->dev, "Invalid %s GPIO: %u\n",
1548                 fwnode_get_name(child_node), gpio_sel[i]);
1549             return -EINVAL;
1550         }
1551
1552         gpio_setup = iqs7222->gpio_setup[gpio_sel[i]];
1553
1554         if (gpio_setup[2] && child_link != gpio_setup[2]) {
1555             dev_err(&client->dev,
1556                 "Conflicting GPIO %u event types\n",
1557                 gpio_sel[i]);
1558             return -EINVAL;
1559         }
1560
1561         gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN;
1562         gpio_setup[1] |= child_enable;
1563         gpio_setup[2] = child_link;
1564     }
1565
1566     return 0;
1567 }
1568
1569 static int iqs7222_parse_props(struct iqs7222_private *iqs7222,
1570                    struct fwnode_handle **child_node,
1571                    int child_index,
1572                    enum iqs7222_reg_grp_id reg_grp,
1573                    enum iqs7222_reg_key_id reg_key)
1574 {
1575     u16 *setup = iqs7222_setup(iqs7222, reg_grp, child_index);
1576     struct i2c_client *client = iqs7222->client;
1577     struct fwnode_handle *reg_grp_node;
1578     char reg_grp_name[16];
1579     int i;
1580
1581     switch (reg_grp) {
1582     case IQS7222_REG_GRP_CYCLE:
1583     case IQS7222_REG_GRP_CHAN:
1584     case IQS7222_REG_GRP_SLDR:
1585     case IQS7222_REG_GRP_GPIO:
1586     case IQS7222_REG_GRP_BTN:
1587         /*
1588          * These groups derive a child node and return it to the caller
1589          * for additional group-specific processing. In some cases, the
1590          * child node may have already been derived.
1591          */
1592         reg_grp_node = *child_node;
1593         if (reg_grp_node)
1594             break;
1595
1596         snprintf(reg_grp_name, sizeof(reg_grp_name), "%s-%d",
1597              iqs7222_reg_grp_names[reg_grp], child_index);
1598
1599         reg_grp_node = device_get_named_child_node(&client->dev,
1600                                reg_grp_name);
1601         if (!reg_grp_node)
1602             return 0;
1603
1604         *child_node = reg_grp_node;
1605         break;
1606
1607     case IQS7222_REG_GRP_GLBL:
1608     case IQS7222_REG_GRP_FILT:
1609     case IQS7222_REG_GRP_SYS:
1610         /*
1611          * These groups are not organized beneath a child node, nor are
1612          * they subject to any additional processing by the caller.
1613          */
1614         reg_grp_node = dev_fwnode(&client->dev);
1615         break;
1616
1617     default:
1618         return -EINVAL;
1619     }
1620
1621     for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) {
1622         const char *name = iqs7222_props[i].name;
1623         int reg_offset = iqs7222_props[i].reg_offset;
1624         int reg_shift = iqs7222_props[i].reg_shift;
1625         int reg_width = iqs7222_props[i].reg_width;
1626         int val_pitch = iqs7222_props[i].val_pitch ? : 1;
1627         int val_min = iqs7222_props[i].val_min;
1628         int val_max = iqs7222_props[i].val_max;
1629         bool invert = iqs7222_props[i].invert;
1630         const char *label = iqs7222_props[i].label ? : name;
1631         unsigned int val;
1632         int error;
1633
1634         if (iqs7222_props[i].reg_grp != reg_grp ||
1635             iqs7222_props[i].reg_key != reg_key)
1636             continue;
1637
1638         /*
1639          * Boolean register fields are one bit wide; they are forcibly
1640          * reset to provide a means to undo changes by a bootloader if
1641          * necessary.
1642          *
1643          * Scalar fields, on the other hand, are left untouched unless
1644          * their corresponding properties are present.
1645          */
1646         if (reg_width == 1) {
1647             if (invert)
1648                 setup[reg_offset] |= BIT(reg_shift);
1649             else
1650                 setup[reg_offset] &= ~BIT(reg_shift);
1651         }
1652
1653         if (!fwnode_property_present(reg_grp_node, name))
1654             continue;
1655
1656         if (reg_width == 1) {
1657             if (invert)
1658                 setup[reg_offset] &= ~BIT(reg_shift);
1659             else
1660                 setup[reg_offset] |= BIT(reg_shift);
1661
1662             continue;
1663         }
1664
1665         error = fwnode_property_read_u32(reg_grp_node, name, &val);
1666         if (error) {
1667             dev_err(&client->dev, "Failed to read %s %s: %d\n",
1668                 fwnode_get_name(reg_grp_node), label, error);
1669             return error;
1670         }
1671
1672         if (!val_max)
1673             val_max = GENMASK(reg_width - 1, 0) * val_pitch;
1674
1675         if (val < val_min || val > val_max) {
1676             dev_err(&client->dev, "Invalid %s %s: %u\n",
1677                 fwnode_get_name(reg_grp_node), label, val);
1678             return -EINVAL;
1679         }
1680
1681         setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1,
1682                           reg_shift);
1683         setup[reg_offset] |= (val / val_pitch << reg_shift);
1684     }
1685
1686     return 0;
1687 }
1688
1689 static int iqs7222_parse_cycle(struct iqs7222_private *iqs7222, int cycle_index)
1690 {
1691     u16 *cycle_setup = iqs7222->cycle_setup[cycle_index];
1692     struct i2c_client *client = iqs7222->client;
1693     struct fwnode_handle *cycle_node = NULL;
1694     unsigned int pins[9];
1695     int error, count, i;
1696
1697     /*
1698      * Each channel shares a cycle with one other channel; the mapping of
1699      * channels to cycles is fixed. Properties defined for a cycle impact
1700      * both channels tied to the cycle.
1701      */
1702     error = iqs7222_parse_props(iqs7222, &cycle_node, cycle_index,
1703                     IQS7222_REG_GRP_CYCLE,
1704                     IQS7222_REG_KEY_NONE);
1705     if (error)
1706         return error;
1707
1708     if (!cycle_node)
1709         return 0;
1710
1711     /*
1712      * Unlike channels which are restricted to a select range of CRx pins
1713      * based on channel number, any cycle can claim any of the device's 9
1714      * CTx pins (CTx0-8).
1715      */
1716     if (!fwnode_property_present(cycle_node, "azoteq,tx-enable"))
1717         return 0;
1718
1719     count = fwnode_property_count_u32(cycle_node, "azoteq,tx-enable");
1720     if (count < 0) {
1721         dev_err(&client->dev, "Failed to count %s CTx pins: %d\n",
1722             fwnode_get_name(cycle_node), count);
1723         return count;
1724     } else if (count > ARRAY_SIZE(pins)) {
1725         dev_err(&client->dev, "Invalid number of %s CTx pins\n",
1726             fwnode_get_name(cycle_node));
1727         return -EINVAL;
1728     }
1729
1730     error = fwnode_property_read_u32_array(cycle_node, "azoteq,tx-enable",
1731                            pins, count);
1732     if (error) {
1733         dev_err(&client->dev, "Failed to read %s CTx pins: %d\n",
1734             fwnode_get_name(cycle_node), error);
1735         return error;
1736     }
1737
1738     cycle_setup[1] &= ~GENMASK(7 + ARRAY_SIZE(pins) - 1, 7);
1739
1740     for (i = 0; i < count; i++) {
1741         if (pins[i] > 8) {
1742             dev_err(&client->dev, "Invalid %s CTx pin: %u\n",
1743                 fwnode_get_name(cycle_node), pins[i]);
1744             return -EINVAL;
1745         }
1746
1747         cycle_setup[1] |= BIT(pins[i] + 7);
1748     }
1749
1750     return 0;
1751 }
1752
1753 static int iqs7222_parse_chan(struct iqs7222_private *iqs7222, int chan_index)
1754 {
1755     const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1756     struct i2c_client *client = iqs7222->client;
1757     struct fwnode_handle *chan_node = NULL;
1758     int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
1759     int ext_chan = rounddown(num_chan, 10);
1760     int error, i;
1761     u16 *chan_setup = iqs7222->chan_setup[chan_index];
1762     u16 *sys_setup = iqs7222->sys_setup;
1763     unsigned int val;
1764
1765     error = iqs7222_parse_props(iqs7222, &chan_node, chan_index,
1766                     IQS7222_REG_GRP_CHAN,
1767                     IQS7222_REG_KEY_NONE);
1768     if (error)
1769         return error;
1770
1771     if (!chan_node)
1772         return 0;
1773
1774     if (dev_desc->allow_offset) {
1775         sys_setup[dev_desc->allow_offset] |= BIT(chan_index);
1776         if (fwnode_property_present(chan_node, "azoteq,ulp-allow"))
1777             sys_setup[dev_desc->allow_offset] &= ~BIT(chan_index);
1778     }
1779
1780     chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN;
1781
1782     /*
1783      * The reference channel function allows for differential measurements
1784      * and is only available in the case of IQS7222A or IQS7222C.
1785      */
1786     if (dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_col > 4 &&
1787         fwnode_property_present(chan_node, "azoteq,ref-select")) {
1788         u16 *ref_setup;
1789
1790         error = fwnode_property_read_u32(chan_node, "azoteq,ref-select",
1791                          &val);
1792         if (error) {
1793             dev_err(&client->dev,
1794                 "Failed to read %s reference channel: %d\n",
1795                 fwnode_get_name(chan_node), error);
1796             return error;
1797         }
1798
1799         if (val >= ext_chan) {
1800             dev_err(&client->dev,
1801                 "Invalid %s reference channel: %u\n",
1802                 fwnode_get_name(chan_node), val);
1803             return -EINVAL;
1804         }
1805
1806         ref_setup = iqs7222->chan_setup[val];
1807
1808         /*
1809          * Configure the current channel as a follower of the selected
1810          * reference channel.
1811          */
1812         chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW;
1813         chan_setup[4] = val * 42 + 1048;
1814
1815         if (!fwnode_property_read_u32(chan_node, "azoteq,ref-weight",
1816                           &val)) {
1817             if (val > U16_MAX) {
1818                 dev_err(&client->dev,
1819                     "Invalid %s reference weight: %u\n",
1820                     fwnode_get_name(chan_node), val);
1821                 return -EINVAL;
1822             }
1823
1824             chan_setup[5] = val;
1825         }
1826
1827         /*
1828          * Configure the selected channel as a reference channel which
1829          * serves the current channel.
1830          */
1831         ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF;
1832         ref_setup[5] |= BIT(chan_index);
1833
1834         ref_setup[4] = dev_desc->touch_link;
1835         if (fwnode_property_present(chan_node, "azoteq,use-prox"))
1836             ref_setup[4] -= 2;
1837     }
1838
1839     if (fwnode_property_present(chan_node, "azoteq,rx-enable")) {
1840         /*
1841          * Each channel can claim up to 4 CRx pins. The first half of
1842          * the channels can use CRx0-3, while the second half can use
1843          * CRx4-7.
1844          */
1845         unsigned int pins[4];
1846         int count;
1847
1848         count = fwnode_property_count_u32(chan_node,
1849                           "azoteq,rx-enable");
1850         if (count < 0) {
1851             dev_err(&client->dev,
1852                 "Failed to count %s CRx pins: %d\n",
1853                 fwnode_get_name(chan_node), count);
1854             return count;
1855         } else if (count > ARRAY_SIZE(pins)) {
1856             dev_err(&client->dev,
1857                 "Invalid number of %s CRx pins\n",
1858                 fwnode_get_name(chan_node));
1859             return -EINVAL;
1860         }
1861
1862         error = fwnode_property_read_u32_array(chan_node,
1863                                "azoteq,rx-enable",
1864                                pins, count);
1865         if (error) {
1866             dev_err(&client->dev,
1867                 "Failed to read %s CRx pins: %d\n",
1868                 fwnode_get_name(chan_node), error);
1869             return error;
1870         }
1871
1872         chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4);
1873
1874         for (i = 0; i < count; i++) {
1875             int min_crx = chan_index < ext_chan / 2 ? 0 : 4;
1876
1877             if (pins[i] < min_crx || pins[i] > min_crx + 3) {
1878                 dev_err(&client->dev,
1879                     "Invalid %s CRx pin: %u\n",
1880                     fwnode_get_name(chan_node), pins[i]);
1881                 return -EINVAL;
1882             }
1883
1884             chan_setup[0] |= BIT(pins[i] + 4 - min_crx);
1885         }
1886     }
1887
1888     for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) {
1889         const char *event_name = iqs7222_kp_events[i].name;
1890         u16 event_enable = iqs7222_kp_events[i].enable;
1891         struct fwnode_handle *event_node;
1892
1893         event_node = fwnode_get_named_child_node(chan_node, event_name);
1894         if (!event_node)
1895             continue;
1896
1897         error = iqs7222_parse_props(iqs7222, &event_node, chan_index,
1898                         IQS7222_REG_GRP_BTN,
1899                         iqs7222_kp_events[i].reg_key);
1900         if (error)
1901             return error;
1902
1903         error = iqs7222_gpio_select(iqs7222, event_node,
1904                         BIT(chan_index),
1905                         dev_desc->touch_link - (i ? 0 : 2));
1906         if (error)
1907             return error;
1908
1909         if (!fwnode_property_read_u32(event_node,
1910                           "azoteq,timeout-press-ms",
1911                           &val)) {
1912             /*
1913              * The IQS7222B employs a global pair of press timeout
1914              * registers as opposed to channel-specific registers.
1915              */
1916             u16 *setup = dev_desc->reg_grps
1917                      [IQS7222_REG_GRP_BTN].num_col > 2 ?
1918                      &iqs7222->btn_setup[chan_index][2] :
1919                      &sys_setup[9];
1920
1921             if (val > U8_MAX * 500) {
1922                 dev_err(&client->dev,
1923                     "Invalid %s press timeout: %u\n",
1924                     fwnode_get_name(chan_node), val);
1925                 return -EINVAL;
1926             }
1927
1928             *setup &= ~(U8_MAX << i * 8);
1929             *setup |= (val / 500 << i * 8);
1930         }
1931
1932         error = fwnode_property_read_u32(event_node, "linux,code",
1933                          &val);
1934         if (error) {
1935             dev_err(&client->dev, "Failed to read %s code: %d\n",
1936                 fwnode_get_name(chan_node), error);
1937             return error;
1938         }
1939
1940         iqs7222->kp_code[chan_index][i] = val;
1941         iqs7222->kp_type[chan_index][i] = EV_KEY;
1942
1943         if (fwnode_property_present(event_node, "linux,input-type")) {
1944             error = fwnode_property_read_u32(event_node,
1945                              "linux,input-type",
1946                              &val);
1947             if (error) {
1948                 dev_err(&client->dev,
1949                     "Failed to read %s input type: %d\n",
1950                     fwnode_get_name(chan_node), error);
1951                 return error;
1952             }
1953
1954             if (val != EV_KEY && val != EV_SW) {
1955                 dev_err(&client->dev,
1956                     "Invalid %s input type: %u\n",
1957                     fwnode_get_name(chan_node), val);
1958                 return -EINVAL;
1959             }
1960
1961             iqs7222->kp_type[chan_index][i] = val;
1962         }
1963
1964         /*
1965          * Reference channels can opt out of event reporting by using
1966          * KEY_RESERVED in place of a true key or switch code.
1967          */
1968         if (iqs7222->kp_type[chan_index][i] == EV_KEY &&
1969             iqs7222->kp_code[chan_index][i] == KEY_RESERVED)
1970             continue;
1971
1972         input_set_capability(iqs7222->keypad,
1973                      iqs7222->kp_type[chan_index][i],
1974                      iqs7222->kp_code[chan_index][i]);
1975
1976         if (!dev_desc->event_offset)
1977             continue;
1978
1979         sys_setup[dev_desc->event_offset] |= event_enable;
1980     }
1981
1982     /*
1983      * The following call handles a special pair of properties that apply
1984      * to a channel node, but reside within the button (event) group.
1985      */
1986     return iqs7222_parse_props(iqs7222, &chan_node, chan_index,
1987                    IQS7222_REG_GRP_BTN,
1988                    IQS7222_REG_KEY_DEBOUNCE);
1989 }
1990
1991 static int iqs7222_parse_sldr(struct iqs7222_private *iqs7222, int sldr_index)
1992 {
1993     const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1994     struct i2c_client *client = iqs7222->client;
1995     struct fwnode_handle *sldr_node = NULL;
1996     int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
1997     int ext_chan = rounddown(num_chan, 10);
1998     int count, error, reg_offset, i;
1999     u16 *event_mask = &iqs7222->sys_setup[dev_desc->event_offset];
2000     u16 *sldr_setup = iqs7222->sldr_setup[sldr_index];
2001     unsigned int chan_sel[4], val;
2002
2003     error = iqs7222_parse_props(iqs7222, &sldr_node, sldr_index,
2004                     IQS7222_REG_GRP_SLDR,
2005                     IQS7222_REG_KEY_NONE);
2006     if (error)
2007         return error;
2008
2009     if (!sldr_node)
2010         return 0;
2011
2012     /*
2013      * Each slider can be spread across 3 to 4 channels. It is possible to
2014      * select only 2 channels, but doing so prevents the slider from using
2015      * the specified resolution.
2016      */
2017     count = fwnode_property_count_u32(sldr_node, "azoteq,channel-select");
2018     if (count < 0) {
2019         dev_err(&client->dev, "Failed to count %s channels: %d\n",
2020             fwnode_get_name(sldr_node), count);
2021         return count;
2022     } else if (count < 3 || count > ARRAY_SIZE(chan_sel)) {
2023         dev_err(&client->dev, "Invalid number of %s channels\n",
2024             fwnode_get_name(sldr_node));
2025         return -EINVAL;
2026     }
2027
2028     error = fwnode_property_read_u32_array(sldr_node,
2029                            "azoteq,channel-select",
2030                            chan_sel, count);
2031     if (error) {
2032         dev_err(&client->dev, "Failed to read %s channels: %d\n",
2033             fwnode_get_name(sldr_node), error);
2034         return error;
2035     }
2036
2037     /*
2038      * Resolution and top speed, if small enough, are packed into a single
2039      * register. Otherwise, each occupies its own register and the rest of
2040      * the slider-related register addresses are offset by one.
2041      */
2042     reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1;
2043
2044     sldr_setup[0] |= count;
2045     sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0);
2046
2047     for (i = 0; i < ARRAY_SIZE(chan_sel); i++) {
2048         sldr_setup[5 + reg_offset + i] = 0;
2049         if (i >= count)
2050             continue;
2051
2052         if (chan_sel[i] >= ext_chan) {
2053             dev_err(&client->dev, "Invalid %s channel: %u\n",
2054                 fwnode_get_name(sldr_node), chan_sel[i]);
2055             return -EINVAL;
2056         }
2057
2058         /*
2059          * The following fields indicate which channels participate in
2060          * the slider, as well as each channel's relative placement.
2061          */
2062         sldr_setup[3 + reg_offset] |= BIT(chan_sel[i]);
2063         sldr_setup[5 + reg_offset + i] = chan_sel[i] * 42 + 1080;
2064     }
2065
2066     sldr_setup[4 + reg_offset] = dev_desc->touch_link;
2067     if (fwnode_property_present(sldr_node, "azoteq,use-prox"))
2068         sldr_setup[4 + reg_offset] -= 2;
2069
2070     if (!fwnode_property_read_u32(sldr_node, "azoteq,slider-size", &val)) {
2071         if (!val || val > dev_desc->sldr_res) {
2072             dev_err(&client->dev, "Invalid %s size: %u\n",
2073                 fwnode_get_name(sldr_node), val);
2074             return -EINVAL;
2075         }
2076
2077         if (reg_offset) {
2078             sldr_setup[3] = val;
2079         } else {
2080             sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_RES_MASK;
2081             sldr_setup[2] |= (val / 16 <<
2082                       IQS7222_SLDR_SETUP_2_RES_SHIFT);
2083         }
2084     }
2085
2086     if (!fwnode_property_read_u32(sldr_node, "azoteq,top-speed", &val)) {
2087         if (val > (reg_offset ? U16_MAX : U8_MAX * 4)) {
2088             dev_err(&client->dev, "Invalid %s top speed: %u\n",
2089                 fwnode_get_name(sldr_node), val);
2090             return -EINVAL;
2091         }
2092
2093         if (reg_offset) {
2094             sldr_setup[2] = val;
2095         } else {
2096             sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK;
2097             sldr_setup[2] |= (val / 4);
2098         }
2099     }
2100
2101     if (!fwnode_property_read_u32(sldr_node, "linux,axis", &val)) {
2102         u16 sldr_max = sldr_setup[3] - 1;
2103
2104         if (!reg_offset) {
2105             sldr_max = sldr_setup[2];
2106
2107             sldr_max &= IQS7222_SLDR_SETUP_2_RES_MASK;
2108             sldr_max >>= IQS7222_SLDR_SETUP_2_RES_SHIFT;
2109
2110             sldr_max = sldr_max * 16 - 1;
2111         }
2112
2113         input_set_abs_params(iqs7222->keypad, val, 0, sldr_max, 0, 0);
2114         iqs7222->sl_axis[sldr_index] = val;
2115     }
2116
2117     if (dev_desc->wheel_enable) {
2118         sldr_setup[0] &= ~dev_desc->wheel_enable;
2119         if (iqs7222->sl_axis[sldr_index] == ABS_WHEEL)
2120             sldr_setup[0] |= dev_desc->wheel_enable;
2121     }
2122
2123     /*
2124      * The absence of a register offset makes it safe to assume the device
2125      * supports gestures, each of which is first disabled until explicitly
2126      * enabled.
2127      */
2128     if (!reg_offset)
2129         for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++)
2130             sldr_setup[9] &= ~iqs7222_sl_events[i].enable;
2131
2132     for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) {
2133         const char *event_name = iqs7222_sl_events[i].name;
2134         struct fwnode_handle *event_node;
2135
2136         event_node = fwnode_get_named_child_node(sldr_node, event_name);
2137         if (!event_node)
2138             continue;
2139
2140         error = iqs7222_parse_props(iqs7222, &event_node, sldr_index,
2141                         IQS7222_REG_GRP_SLDR,
2142                         reg_offset ?
2143                         IQS7222_REG_KEY_RESERVED :
2144                         iqs7222_sl_events[i].reg_key);
2145         if (error)
2146             return error;
2147
2148         /*
2149          * The press/release event does not expose a direct GPIO link,
2150          * but one can be emulated by tying each of the participating
2151          * channels to the same GPIO.
2152          */
2153         error = iqs7222_gpio_select(iqs7222, event_node,
2154                         i ? iqs7222_sl_events[i].enable
2155                           : sldr_setup[3 + reg_offset],
2156                         i ? 1568 + sldr_index * 30
2157                           : sldr_setup[4 + reg_offset]);
2158         if (error)
2159             return error;
2160
2161         if (!reg_offset)
2162             sldr_setup[9] |= iqs7222_sl_events[i].enable;
2163
2164         error = fwnode_property_read_u32(event_node, "linux,code",
2165                          &val);
2166         if (error) {
2167             dev_err(&client->dev, "Failed to read %s code: %d\n",
2168                 fwnode_get_name(sldr_node), error);
2169             return error;
2170         }
2171
2172         iqs7222->sl_code[sldr_index][i] = val;
2173         input_set_capability(iqs7222->keypad, EV_KEY, val);
2174
2175         if (!dev_desc->event_offset)
2176             continue;
2177
2178         /*
2179          * The press/release event is determined based on whether the
2180          * coordinate field reports 0xFFFF and solely relies on touch
2181          * or proximity interrupts to be unmasked.
2182          */
2183         if (i && !reg_offset)
2184             *event_mask |= (IQS7222_EVENT_MASK_SLDR << sldr_index);
2185         else if (sldr_setup[4 + reg_offset] == dev_desc->touch_link)
2186             *event_mask |= IQS7222_EVENT_MASK_TOUCH;
2187         else
2188             *event_mask |= IQS7222_EVENT_MASK_PROX;
2189     }
2190
2191     /*
2192      * The following call handles a special pair of properties that shift
2193      * to make room for a wheel enable control in the case of IQS7222C.
2194      */
2195     return iqs7222_parse_props(iqs7222, &sldr_node, sldr_index,
2196                    IQS7222_REG_GRP_SLDR,
2197                    dev_desc->wheel_enable ?
2198                    IQS7222_REG_KEY_WHEEL :
2199                    IQS7222_REG_KEY_NO_WHEEL);
2200 }
2201
2202 static int iqs7222_parse_all(struct iqs7222_private *iqs7222)
2203 {
2204     const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2205     const struct iqs7222_reg_grp_desc *reg_grps = dev_desc->reg_grps;
2206     u16 *sys_setup = iqs7222->sys_setup;
2207     int error, i;
2208
2209     if (dev_desc->event_offset)
2210         sys_setup[dev_desc->event_offset] = IQS7222_EVENT_MASK_ATI;
2211
2212     for (i = 0; i < reg_grps[IQS7222_REG_GRP_CYCLE].num_row; i++) {
2213         error = iqs7222_parse_cycle(iqs7222, i);
2214         if (error)
2215             return error;
2216     }
2217
2218     error = iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_GLBL,
2219                     IQS7222_REG_KEY_NONE);
2220     if (error)
2221         return error;
2222
2223     for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) {
2224         struct fwnode_handle *gpio_node = NULL;
2225         u16 *gpio_setup = iqs7222->gpio_setup[i];
2226         int j;
2227
2228         gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN;
2229         gpio_setup[1] = 0;
2230         gpio_setup[2] = 0;
2231
2232         error = iqs7222_parse_props(iqs7222, &gpio_node, i,
2233                         IQS7222_REG_GRP_GPIO,
2234                         IQS7222_REG_KEY_NONE);
2235         if (error)
2236             return error;
2237
2238         if (reg_grps[IQS7222_REG_GRP_GPIO].num_row == 1)
2239             continue;
2240
2241         /*
2242          * The IQS7222C exposes multiple GPIO and must be informed
2243          * as to which GPIO this group represents.
2244          */
2245         for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++)
2246             gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]);
2247
2248         gpio_setup[0] |= BIT(iqs7222_gpio_links[i]);
2249     }
2250
2251     for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) {
2252         u16 *chan_setup = iqs7222->chan_setup[i];
2253
2254         chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK;
2255         chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN;
2256
2257         chan_setup[5] = 0;
2258     }
2259
2260     for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) {
2261         error = iqs7222_parse_chan(iqs7222, i);
2262         if (error)
2263             return error;
2264     }
2265
2266     error = iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_FILT,
2267                     IQS7222_REG_KEY_NONE);
2268     if (error)
2269         return error;
2270
2271     for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {
2272         u16 *sldr_setup = iqs7222->sldr_setup[i];
2273
2274         sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK;
2275
2276         error = iqs7222_parse_sldr(iqs7222, i);
2277         if (error)
2278             return error;
2279     }
2280
2281     return iqs7222_parse_props(iqs7222, NULL, 0, IQS7222_REG_GRP_SYS,
2282                    IQS7222_REG_KEY_NONE);
2283 }
2284
2285 static int iqs7222_report(struct iqs7222_private *iqs7222)
2286 {
2287     const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2288     struct i2c_client *client = iqs7222->client;
2289     int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2290     int num_stat = dev_desc->reg_grps[IQS7222_REG_GRP_STAT].num_col;
2291     int error, i, j;
2292     __le16 status[IQS7222_MAX_COLS_STAT];
2293
2294     error = iqs7222_read_burst(iqs7222, IQS7222_SYS_STATUS, status,
2295                    num_stat);
2296     if (error)
2297         return error;
2298
2299     if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) {
2300         dev_err(&client->dev, "Unexpected device reset\n");
2301         return iqs7222_dev_init(iqs7222, WRITE);
2302     }
2303
2304     if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) {
2305         dev_err(&client->dev, "Unexpected ATI error\n");
2306         return iqs7222_ati_trigger(iqs7222);
2307     }
2308
2309     if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE)
2310         return 0;
2311
2312     for (i = 0; i < num_chan; i++) {
2313         u16 *chan_setup = iqs7222->chan_setup[i];
2314
2315         if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN))
2316             continue;
2317
2318         for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) {
2319             /*
2320              * Proximity state begins at offset 2 and spills into
2321              * offset 3 for devices with more than 16 channels.
2322              *
2323              * Touch state begins at the first offset immediately
2324              * following proximity state.
2325              */
2326             int k = 2 + j * (num_chan > 16 ? 2 : 1);
2327             u16 state = le16_to_cpu(status[k + i / 16]);
2328
2329             input_event(iqs7222->keypad,
2330                     iqs7222->kp_type[i][j],
2331                     iqs7222->kp_code[i][j],
2332                     !!(state & BIT(i % 16)));
2333         }
2334     }
2335
2336     for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {
2337         u16 *sldr_setup = iqs7222->sldr_setup[i];
2338         u16 sldr_pos = le16_to_cpu(status[4 + i]);
2339         u16 state = le16_to_cpu(status[6 + i]);
2340
2341         if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK))
2342             continue;
2343
2344         if (sldr_pos < dev_desc->sldr_res)
2345             input_report_abs(iqs7222->keypad, iqs7222->sl_axis[i],
2346                      sldr_pos);
2347
2348         input_report_key(iqs7222->keypad, iqs7222->sl_code[i][0],
2349                  sldr_pos < dev_desc->sldr_res);
2350
2351         /*
2352          * A maximum resolution indicates the device does not support
2353          * gestures, in which case the remaining fields are ignored.
2354          */
2355         if (dev_desc->sldr_res == U16_MAX)
2356             continue;
2357
2358         if (!(le16_to_cpu(status[1]) & IQS7222_EVENT_MASK_SLDR << i))
2359             continue;
2360
2361         /*
2362          * Skip the press/release event, as it does not have separate
2363          * status fields and is handled separately.
2364          */
2365         for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++) {
2366             u16 mask = iqs7222_sl_events[j].mask;
2367             u16 val = iqs7222_sl_events[j].val;
2368
2369             input_report_key(iqs7222->keypad,
2370                      iqs7222->sl_code[i][j],
2371                      (state & mask) == val);
2372         }
2373
2374         input_sync(iqs7222->keypad);
2375
2376         for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++)
2377             input_report_key(iqs7222->keypad,
2378                      iqs7222->sl_code[i][j], 0);
2379     }
2380
2381     input_sync(iqs7222->keypad);
2382
2383     return 0;
2384 }
2385
2386 static irqreturn_t iqs7222_irq(int irq, void *context)
2387 {
2388     struct iqs7222_private *iqs7222 = context;
2389
2390     return iqs7222_report(iqs7222) ? IRQ_NONE : IRQ_HANDLED;
2391 }
2392
2393 static int iqs7222_probe(struct i2c_client *client)
2394 {
2395     struct iqs7222_private *iqs7222;
2396     unsigned long irq_flags;
2397     int error, irq;
2398
2399     iqs7222 = devm_kzalloc(&client->dev, sizeof(*iqs7222), GFP_KERNEL);
2400     if (!iqs7222)
2401         return -ENOMEM;
2402
2403     i2c_set_clientdata(client, iqs7222);
2404     iqs7222->client = client;
2405
2406     iqs7222->keypad = devm_input_allocate_device(&client->dev);
2407     if (!iqs7222->keypad)
2408         return -ENOMEM;
2409
2410     iqs7222->keypad->name = client->name;
2411     iqs7222->keypad->id.bustype = BUS_I2C;
2412
2413     /*
2414      * The RDY pin behaves as an interrupt, but must also be polled ahead
2415      * of unsolicited I2C communication. As such, it is first opened as a
2416      * GPIO and then passed to gpiod_to_irq() to register the interrupt.
2417      */
2418     iqs7222->irq_gpio = devm_gpiod_get(&client->dev, "irq", GPIOD_IN);
2419     if (IS_ERR(iqs7222->irq_gpio)) {
2420         error = PTR_ERR(iqs7222->irq_gpio);
2421         dev_err(&client->dev, "Failed to request IRQ GPIO: %d\n",
2422             error);
2423         return error;
2424     }
2425
2426     iqs7222->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
2427                               GPIOD_OUT_HIGH);
2428     if (IS_ERR(iqs7222->reset_gpio)) {
2429         error = PTR_ERR(iqs7222->reset_gpio);
2430         dev_err(&client->dev, "Failed to request reset GPIO: %d\n",
2431             error);
2432         return error;
2433     }
2434
2435     error = iqs7222_hard_reset(iqs7222);
2436     if (error)
2437         return error;
2438
2439     error = iqs7222_dev_info(iqs7222);
2440     if (error)
2441         return error;
2442
2443     error = iqs7222_dev_init(iqs7222, READ);
2444     if (error)
2445         return error;
2446
2447     error = iqs7222_parse_all(iqs7222);
2448     if (error)
2449         return error;
2450
2451     error = iqs7222_dev_init(iqs7222, WRITE);
2452     if (error)
2453         return error;
2454
2455     error = iqs7222_report(iqs7222);
2456     if (error)
2457         return error;
2458
2459     error = input_register_device(iqs7222->keypad);
2460     if (error) {
2461         dev_err(&client->dev, "Failed to register device: %d\n", error);
2462         return error;
2463     }
2464
2465     irq = gpiod_to_irq(iqs7222->irq_gpio);
2466     if (irq < 0)
2467         return irq;
2468
2469     irq_flags = gpiod_is_active_low(iqs7222->irq_gpio) ? IRQF_TRIGGER_LOW
2470                                : IRQF_TRIGGER_HIGH;
2471     irq_flags |= IRQF_ONESHOT;
2472
2473     error = devm_request_threaded_irq(&client->dev, irq, NULL, iqs7222_irq,
2474                       irq_flags, client->name, iqs7222);
2475     if (error)
2476         dev_err(&client->dev, "Failed to request IRQ: %d\n", error);
2477
2478     return error;
2479 }
2480
2481 static const struct of_device_id iqs7222_of_match[] = {
2482     { .compatible = "azoteq,iqs7222a" },
2483     { .compatible = "azoteq,iqs7222b" },
2484     { .compatible = "azoteq,iqs7222c" },
2485     { }
2486 };
2487 MODULE_DEVICE_TABLE(of, iqs7222_of_match);
2488
2489 static struct i2c_driver iqs7222_i2c_driver = {
2490     .driver = {
2491         .name = "iqs7222",
2492         .of_match_table = iqs7222_of_match,
2493     },
2494     .probe_new = iqs7222_probe,
2495 };
2496 module_i2c_driver(iqs7222_i2c_driver);
2497
2498 MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>");
2499 MODULE_DESCRIPTION("Azoteq IQS7222A/B/C Capacitive Touch Controller");
2500 MODULE_LICENSE("GPL");