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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
0004  * keyboard controller
0005  *
0006  * Copyright (c) 2009-2011, NVIDIA Corporation.
0007  */
0008 
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/input.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/delay.h>
0014 #include <linux/io.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/of.h>
0017 #include <linux/of_device.h>
0018 #include <linux/clk.h>
0019 #include <linux/slab.h>
0020 #include <linux/input/matrix_keypad.h>
0021 #include <linux/reset.h>
0022 #include <linux/err.h>
0023 
0024 #define KBC_MAX_KPENT   8
0025 
0026 /* Maximum row/column supported by Tegra KBC yet  is 16x8 */
0027 #define KBC_MAX_GPIO    24
0028 /* Maximum keys supported by Tegra KBC yet is 16 x 8*/
0029 #define KBC_MAX_KEY (16 * 8)
0030 
0031 #define KBC_MAX_DEBOUNCE_CNT    0x3ffu
0032 
0033 /* KBC row scan time and delay for beginning the row scan. */
0034 #define KBC_ROW_SCAN_TIME   16
0035 #define KBC_ROW_SCAN_DLY    5
0036 
0037 /* KBC uses a 32KHz clock so a cycle = 1/32Khz */
0038 #define KBC_CYCLE_MS    32
0039 
0040 /* KBC Registers */
0041 
0042 /* KBC Control Register */
0043 #define KBC_CONTROL_0   0x0
0044 #define KBC_FIFO_TH_CNT_SHIFT(cnt)  (cnt << 14)
0045 #define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
0046 #define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
0047 #define KBC_CONTROL_KEYPRESS_INT_EN (1 << 1)
0048 #define KBC_CONTROL_KBC_EN      (1 << 0)
0049 
0050 /* KBC Interrupt Register */
0051 #define KBC_INT_0   0x4
0052 #define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
0053 #define KBC_INT_KEYPRESS_INT_STATUS (1 << 0)
0054 
0055 #define KBC_ROW_CFG0_0  0x8
0056 #define KBC_COL_CFG0_0  0x18
0057 #define KBC_TO_CNT_0    0x24
0058 #define KBC_INIT_DLY_0  0x28
0059 #define KBC_RPT_DLY_0   0x2c
0060 #define KBC_KP_ENT0_0   0x30
0061 #define KBC_KP_ENT1_0   0x34
0062 #define KBC_ROW0_MASK_0 0x38
0063 
0064 #define KBC_ROW_SHIFT   3
0065 
0066 enum tegra_pin_type {
0067     PIN_CFG_IGNORE,
0068     PIN_CFG_COL,
0069     PIN_CFG_ROW,
0070 };
0071 
0072 /* Tegra KBC hw support */
0073 struct tegra_kbc_hw_support {
0074     int max_rows;
0075     int max_columns;
0076 };
0077 
0078 struct tegra_kbc_pin_cfg {
0079     enum tegra_pin_type type;
0080     unsigned char num;
0081 };
0082 
0083 struct tegra_kbc {
0084     struct device *dev;
0085     unsigned int debounce_cnt;
0086     unsigned int repeat_cnt;
0087     struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
0088     const struct matrix_keymap_data *keymap_data;
0089     bool wakeup;
0090     void __iomem *mmio;
0091     struct input_dev *idev;
0092     int irq;
0093     spinlock_t lock;
0094     unsigned int repoll_dly;
0095     unsigned long cp_dly_jiffies;
0096     unsigned int cp_to_wkup_dly;
0097     bool use_fn_map;
0098     bool use_ghost_filter;
0099     bool keypress_caused_wake;
0100     unsigned short keycode[KBC_MAX_KEY * 2];
0101     unsigned short current_keys[KBC_MAX_KPENT];
0102     unsigned int num_pressed_keys;
0103     u32 wakeup_key;
0104     struct timer_list timer;
0105     struct clk *clk;
0106     struct reset_control *rst;
0107     const struct tegra_kbc_hw_support *hw_support;
0108     int max_keys;
0109     int num_rows_and_columns;
0110 };
0111 
0112 static void tegra_kbc_report_released_keys(struct input_dev *input,
0113                        unsigned short old_keycodes[],
0114                        unsigned int old_num_keys,
0115                        unsigned short new_keycodes[],
0116                        unsigned int new_num_keys)
0117 {
0118     unsigned int i, j;
0119 
0120     for (i = 0; i < old_num_keys; i++) {
0121         for (j = 0; j < new_num_keys; j++)
0122             if (old_keycodes[i] == new_keycodes[j])
0123                 break;
0124 
0125         if (j == new_num_keys)
0126             input_report_key(input, old_keycodes[i], 0);
0127     }
0128 }
0129 
0130 static void tegra_kbc_report_pressed_keys(struct input_dev *input,
0131                       unsigned char scancodes[],
0132                       unsigned short keycodes[],
0133                       unsigned int num_pressed_keys)
0134 {
0135     unsigned int i;
0136 
0137     for (i = 0; i < num_pressed_keys; i++) {
0138         input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
0139         input_report_key(input, keycodes[i], 1);
0140     }
0141 }
0142 
0143 static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
0144 {
0145     unsigned char scancodes[KBC_MAX_KPENT];
0146     unsigned short keycodes[KBC_MAX_KPENT];
0147     u32 val = 0;
0148     unsigned int i;
0149     unsigned int num_down = 0;
0150     bool fn_keypress = false;
0151     bool key_in_same_row = false;
0152     bool key_in_same_col = false;
0153 
0154     for (i = 0; i < KBC_MAX_KPENT; i++) {
0155         if ((i % 4) == 0)
0156             val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
0157 
0158         if (val & 0x80) {
0159             unsigned int col = val & 0x07;
0160             unsigned int row = (val >> 3) & 0x0f;
0161             unsigned char scancode =
0162                 MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
0163 
0164             scancodes[num_down] = scancode;
0165             keycodes[num_down] = kbc->keycode[scancode];
0166             /* If driver uses Fn map, do not report the Fn key. */
0167             if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map)
0168                 fn_keypress = true;
0169             else
0170                 num_down++;
0171         }
0172 
0173         val >>= 8;
0174     }
0175 
0176     /*
0177      * Matrix keyboard designs are prone to keyboard ghosting.
0178      * Ghosting occurs if there are 3 keys such that -
0179      * any 2 of the 3 keys share a row, and any 2 of them share a column.
0180      * If so ignore the key presses for this iteration.
0181      */
0182     if (kbc->use_ghost_filter && num_down >= 3) {
0183         for (i = 0; i < num_down; i++) {
0184             unsigned int j;
0185             u8 curr_col = scancodes[i] & 0x07;
0186             u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT;
0187 
0188             /*
0189              * Find 2 keys such that one key is in the same row
0190              * and the other is in the same column as the i-th key.
0191              */
0192             for (j = i + 1; j < num_down; j++) {
0193                 u8 col = scancodes[j] & 0x07;
0194                 u8 row = scancodes[j] >> KBC_ROW_SHIFT;
0195 
0196                 if (col == curr_col)
0197                     key_in_same_col = true;
0198                 if (row == curr_row)
0199                     key_in_same_row = true;
0200             }
0201         }
0202     }
0203 
0204     /*
0205      * If the platform uses Fn keymaps, translate keys on a Fn keypress.
0206      * Function keycodes are max_keys apart from the plain keycodes.
0207      */
0208     if (fn_keypress) {
0209         for (i = 0; i < num_down; i++) {
0210             scancodes[i] += kbc->max_keys;
0211             keycodes[i] = kbc->keycode[scancodes[i]];
0212         }
0213     }
0214 
0215     /* Ignore the key presses for this iteration? */
0216     if (key_in_same_col && key_in_same_row)
0217         return;
0218 
0219     tegra_kbc_report_released_keys(kbc->idev,
0220                        kbc->current_keys, kbc->num_pressed_keys,
0221                        keycodes, num_down);
0222     tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
0223     input_sync(kbc->idev);
0224 
0225     memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
0226     kbc->num_pressed_keys = num_down;
0227 }
0228 
0229 static void tegra_kbc_set_fifo_interrupt(struct tegra_kbc *kbc, bool enable)
0230 {
0231     u32 val;
0232 
0233     val = readl(kbc->mmio + KBC_CONTROL_0);
0234     if (enable)
0235         val |= KBC_CONTROL_FIFO_CNT_INT_EN;
0236     else
0237         val &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
0238     writel(val, kbc->mmio + KBC_CONTROL_0);
0239 }
0240 
0241 static void tegra_kbc_keypress_timer(struct timer_list *t)
0242 {
0243     struct tegra_kbc *kbc = from_timer(kbc, t, timer);
0244     unsigned long flags;
0245     u32 val;
0246     unsigned int i;
0247 
0248     spin_lock_irqsave(&kbc->lock, flags);
0249 
0250     val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
0251     if (val) {
0252         unsigned long dly;
0253 
0254         tegra_kbc_report_keys(kbc);
0255 
0256         /*
0257          * If more than one keys are pressed we need not wait
0258          * for the repoll delay.
0259          */
0260         dly = (val == 1) ? kbc->repoll_dly : 1;
0261         mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
0262     } else {
0263         /* Release any pressed keys and exit the polling loop */
0264         for (i = 0; i < kbc->num_pressed_keys; i++)
0265             input_report_key(kbc->idev, kbc->current_keys[i], 0);
0266         input_sync(kbc->idev);
0267 
0268         kbc->num_pressed_keys = 0;
0269 
0270         /* All keys are released so enable the keypress interrupt */
0271         tegra_kbc_set_fifo_interrupt(kbc, true);
0272     }
0273 
0274     spin_unlock_irqrestore(&kbc->lock, flags);
0275 }
0276 
0277 static irqreturn_t tegra_kbc_isr(int irq, void *args)
0278 {
0279     struct tegra_kbc *kbc = args;
0280     unsigned long flags;
0281     u32 val;
0282 
0283     spin_lock_irqsave(&kbc->lock, flags);
0284 
0285     /*
0286      * Quickly bail out & reenable interrupts if the fifo threshold
0287      * count interrupt wasn't the interrupt source
0288      */
0289     val = readl(kbc->mmio + KBC_INT_0);
0290     writel(val, kbc->mmio + KBC_INT_0);
0291 
0292     if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
0293         /*
0294          * Until all keys are released, defer further processing to
0295          * the polling loop in tegra_kbc_keypress_timer.
0296          */
0297         tegra_kbc_set_fifo_interrupt(kbc, false);
0298         mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
0299     } else if (val & KBC_INT_KEYPRESS_INT_STATUS) {
0300         /* We can be here only through system resume path */
0301         kbc->keypress_caused_wake = true;
0302     }
0303 
0304     spin_unlock_irqrestore(&kbc->lock, flags);
0305 
0306     return IRQ_HANDLED;
0307 }
0308 
0309 static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
0310 {
0311     int i;
0312     unsigned int rst_val;
0313 
0314     /* Either mask all keys or none. */
0315     rst_val = (filter && !kbc->wakeup) ? ~0 : 0;
0316 
0317     for (i = 0; i < kbc->hw_support->max_rows; i++)
0318         writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
0319 }
0320 
0321 static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
0322 {
0323     int i;
0324 
0325     for (i = 0; i < KBC_MAX_GPIO; i++) {
0326         u32 r_shft = 5 * (i % 6);
0327         u32 c_shft = 4 * (i % 8);
0328         u32 r_mask = 0x1f << r_shft;
0329         u32 c_mask = 0x0f << c_shft;
0330         u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
0331         u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
0332         u32 row_cfg = readl(kbc->mmio + r_offs);
0333         u32 col_cfg = readl(kbc->mmio + c_offs);
0334 
0335         row_cfg &= ~r_mask;
0336         col_cfg &= ~c_mask;
0337 
0338         switch (kbc->pin_cfg[i].type) {
0339         case PIN_CFG_ROW:
0340             row_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << r_shft;
0341             break;
0342 
0343         case PIN_CFG_COL:
0344             col_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << c_shft;
0345             break;
0346 
0347         case PIN_CFG_IGNORE:
0348             break;
0349         }
0350 
0351         writel(row_cfg, kbc->mmio + r_offs);
0352         writel(col_cfg, kbc->mmio + c_offs);
0353     }
0354 }
0355 
0356 static int tegra_kbc_start(struct tegra_kbc *kbc)
0357 {
0358     unsigned int debounce_cnt;
0359     u32 val = 0;
0360     int ret;
0361 
0362     ret = clk_prepare_enable(kbc->clk);
0363     if (ret)
0364         return ret;
0365 
0366     /* Reset the KBC controller to clear all previous status.*/
0367     reset_control_assert(kbc->rst);
0368     udelay(100);
0369     reset_control_deassert(kbc->rst);
0370     udelay(100);
0371 
0372     tegra_kbc_config_pins(kbc);
0373     tegra_kbc_setup_wakekeys(kbc, false);
0374 
0375     writel(kbc->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
0376 
0377     /* Keyboard debounce count is maximum of 12 bits. */
0378     debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
0379     val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
0380     val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
0381     val |= KBC_CONTROL_FIFO_CNT_INT_EN;  /* interrupt on FIFO threshold */
0382     val |= KBC_CONTROL_KBC_EN;     /* enable */
0383     writel(val, kbc->mmio + KBC_CONTROL_0);
0384 
0385     /*
0386      * Compute the delay(ns) from interrupt mode to continuous polling
0387      * mode so the timer routine is scheduled appropriately.
0388      */
0389     val = readl(kbc->mmio + KBC_INIT_DLY_0);
0390     kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);
0391 
0392     kbc->num_pressed_keys = 0;
0393 
0394     /*
0395      * Atomically clear out any remaining entries in the key FIFO
0396      * and enable keyboard interrupts.
0397      */
0398     while (1) {
0399         val = readl(kbc->mmio + KBC_INT_0);
0400         val >>= 4;
0401         if (!val)
0402             break;
0403 
0404         val = readl(kbc->mmio + KBC_KP_ENT0_0);
0405         val = readl(kbc->mmio + KBC_KP_ENT1_0);
0406     }
0407     writel(0x7, kbc->mmio + KBC_INT_0);
0408 
0409     enable_irq(kbc->irq);
0410 
0411     return 0;
0412 }
0413 
0414 static void tegra_kbc_stop(struct tegra_kbc *kbc)
0415 {
0416     unsigned long flags;
0417     u32 val;
0418 
0419     spin_lock_irqsave(&kbc->lock, flags);
0420     val = readl(kbc->mmio + KBC_CONTROL_0);
0421     val &= ~1;
0422     writel(val, kbc->mmio + KBC_CONTROL_0);
0423     spin_unlock_irqrestore(&kbc->lock, flags);
0424 
0425     disable_irq(kbc->irq);
0426     del_timer_sync(&kbc->timer);
0427 
0428     clk_disable_unprepare(kbc->clk);
0429 }
0430 
0431 static int tegra_kbc_open(struct input_dev *dev)
0432 {
0433     struct tegra_kbc *kbc = input_get_drvdata(dev);
0434 
0435     return tegra_kbc_start(kbc);
0436 }
0437 
0438 static void tegra_kbc_close(struct input_dev *dev)
0439 {
0440     struct tegra_kbc *kbc = input_get_drvdata(dev);
0441 
0442     return tegra_kbc_stop(kbc);
0443 }
0444 
0445 static bool tegra_kbc_check_pin_cfg(const struct tegra_kbc *kbc,
0446                     unsigned int *num_rows)
0447 {
0448     int i;
0449 
0450     *num_rows = 0;
0451 
0452     for (i = 0; i < KBC_MAX_GPIO; i++) {
0453         const struct tegra_kbc_pin_cfg *pin_cfg = &kbc->pin_cfg[i];
0454 
0455         switch (pin_cfg->type) {
0456         case PIN_CFG_ROW:
0457             if (pin_cfg->num >= kbc->hw_support->max_rows) {
0458                 dev_err(kbc->dev,
0459                     "pin_cfg[%d]: invalid row number %d\n",
0460                     i, pin_cfg->num);
0461                 return false;
0462             }
0463             (*num_rows)++;
0464             break;
0465 
0466         case PIN_CFG_COL:
0467             if (pin_cfg->num >= kbc->hw_support->max_columns) {
0468                 dev_err(kbc->dev,
0469                     "pin_cfg[%d]: invalid column number %d\n",
0470                     i, pin_cfg->num);
0471                 return false;
0472             }
0473             break;
0474 
0475         case PIN_CFG_IGNORE:
0476             break;
0477 
0478         default:
0479             dev_err(kbc->dev,
0480                 "pin_cfg[%d]: invalid entry type %d\n",
0481                 pin_cfg->type, pin_cfg->num);
0482             return false;
0483         }
0484     }
0485 
0486     return true;
0487 }
0488 
0489 static int tegra_kbc_parse_dt(struct tegra_kbc *kbc)
0490 {
0491     struct device_node *np = kbc->dev->of_node;
0492     u32 prop;
0493     int i;
0494     u32 num_rows = 0;
0495     u32 num_cols = 0;
0496     u32 cols_cfg[KBC_MAX_GPIO];
0497     u32 rows_cfg[KBC_MAX_GPIO];
0498     int proplen;
0499     int ret;
0500 
0501     if (!of_property_read_u32(np, "nvidia,debounce-delay-ms", &prop))
0502         kbc->debounce_cnt = prop;
0503 
0504     if (!of_property_read_u32(np, "nvidia,repeat-delay-ms", &prop))
0505         kbc->repeat_cnt = prop;
0506 
0507     if (of_find_property(np, "nvidia,needs-ghost-filter", NULL))
0508         kbc->use_ghost_filter = true;
0509 
0510     if (of_property_read_bool(np, "wakeup-source") ||
0511         of_property_read_bool(np, "nvidia,wakeup-source")) /* legacy */
0512         kbc->wakeup = true;
0513 
0514     if (!of_get_property(np, "nvidia,kbc-row-pins", &proplen)) {
0515         dev_err(kbc->dev, "property nvidia,kbc-row-pins not found\n");
0516         return -ENOENT;
0517     }
0518     num_rows = proplen / sizeof(u32);
0519 
0520     if (!of_get_property(np, "nvidia,kbc-col-pins", &proplen)) {
0521         dev_err(kbc->dev, "property nvidia,kbc-col-pins not found\n");
0522         return -ENOENT;
0523     }
0524     num_cols = proplen / sizeof(u32);
0525 
0526     if (num_rows > kbc->hw_support->max_rows) {
0527         dev_err(kbc->dev,
0528             "Number of rows is more than supported by hardware\n");
0529         return -EINVAL;
0530     }
0531 
0532     if (num_cols > kbc->hw_support->max_columns) {
0533         dev_err(kbc->dev,
0534             "Number of cols is more than supported by hardware\n");
0535         return -EINVAL;
0536     }
0537 
0538     if (!of_get_property(np, "linux,keymap", &proplen)) {
0539         dev_err(kbc->dev, "property linux,keymap not found\n");
0540         return -ENOENT;
0541     }
0542 
0543     if (!num_rows || !num_cols || ((num_rows + num_cols) > KBC_MAX_GPIO)) {
0544         dev_err(kbc->dev,
0545             "keypad rows/columns not properly specified\n");
0546         return -EINVAL;
0547     }
0548 
0549     /* Set all pins as non-configured */
0550     for (i = 0; i < kbc->num_rows_and_columns; i++)
0551         kbc->pin_cfg[i].type = PIN_CFG_IGNORE;
0552 
0553     ret = of_property_read_u32_array(np, "nvidia,kbc-row-pins",
0554                 rows_cfg, num_rows);
0555     if (ret < 0) {
0556         dev_err(kbc->dev, "Rows configurations are not proper\n");
0557         return -EINVAL;
0558     }
0559 
0560     ret = of_property_read_u32_array(np, "nvidia,kbc-col-pins",
0561                 cols_cfg, num_cols);
0562     if (ret < 0) {
0563         dev_err(kbc->dev, "Cols configurations are not proper\n");
0564         return -EINVAL;
0565     }
0566 
0567     for (i = 0; i < num_rows; i++) {
0568         kbc->pin_cfg[rows_cfg[i]].type = PIN_CFG_ROW;
0569         kbc->pin_cfg[rows_cfg[i]].num = i;
0570     }
0571 
0572     for (i = 0; i < num_cols; i++) {
0573         kbc->pin_cfg[cols_cfg[i]].type = PIN_CFG_COL;
0574         kbc->pin_cfg[cols_cfg[i]].num = i;
0575     }
0576 
0577     return 0;
0578 }
0579 
0580 static const struct tegra_kbc_hw_support tegra20_kbc_hw_support = {
0581     .max_rows   = 16,
0582     .max_columns    = 8,
0583 };
0584 
0585 static const struct tegra_kbc_hw_support tegra11_kbc_hw_support = {
0586     .max_rows   = 11,
0587     .max_columns    = 8,
0588 };
0589 
0590 static const struct of_device_id tegra_kbc_of_match[] = {
0591     { .compatible = "nvidia,tegra114-kbc", .data = &tegra11_kbc_hw_support},
0592     { .compatible = "nvidia,tegra30-kbc", .data = &tegra20_kbc_hw_support},
0593     { .compatible = "nvidia,tegra20-kbc", .data = &tegra20_kbc_hw_support},
0594     { },
0595 };
0596 MODULE_DEVICE_TABLE(of, tegra_kbc_of_match);
0597 
0598 static int tegra_kbc_probe(struct platform_device *pdev)
0599 {
0600     struct tegra_kbc *kbc;
0601     struct resource *res;
0602     int err;
0603     int num_rows = 0;
0604     unsigned int debounce_cnt;
0605     unsigned int scan_time_rows;
0606     unsigned int keymap_rows;
0607     const struct of_device_id *match;
0608 
0609     match = of_match_device(tegra_kbc_of_match, &pdev->dev);
0610 
0611     kbc = devm_kzalloc(&pdev->dev, sizeof(*kbc), GFP_KERNEL);
0612     if (!kbc) {
0613         dev_err(&pdev->dev, "failed to alloc memory for kbc\n");
0614         return -ENOMEM;
0615     }
0616 
0617     kbc->dev = &pdev->dev;
0618     kbc->hw_support = match->data;
0619     kbc->max_keys = kbc->hw_support->max_rows *
0620                 kbc->hw_support->max_columns;
0621     kbc->num_rows_and_columns = kbc->hw_support->max_rows +
0622                     kbc->hw_support->max_columns;
0623     keymap_rows = kbc->max_keys;
0624     spin_lock_init(&kbc->lock);
0625 
0626     err = tegra_kbc_parse_dt(kbc);
0627     if (err)
0628         return err;
0629 
0630     if (!tegra_kbc_check_pin_cfg(kbc, &num_rows))
0631         return -EINVAL;
0632 
0633     kbc->irq = platform_get_irq(pdev, 0);
0634     if (kbc->irq < 0)
0635         return -ENXIO;
0636 
0637     kbc->idev = devm_input_allocate_device(&pdev->dev);
0638     if (!kbc->idev) {
0639         dev_err(&pdev->dev, "failed to allocate input device\n");
0640         return -ENOMEM;
0641     }
0642 
0643     timer_setup(&kbc->timer, tegra_kbc_keypress_timer, 0);
0644 
0645     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0646     kbc->mmio = devm_ioremap_resource(&pdev->dev, res);
0647     if (IS_ERR(kbc->mmio))
0648         return PTR_ERR(kbc->mmio);
0649 
0650     kbc->clk = devm_clk_get(&pdev->dev, NULL);
0651     if (IS_ERR(kbc->clk)) {
0652         dev_err(&pdev->dev, "failed to get keyboard clock\n");
0653         return PTR_ERR(kbc->clk);
0654     }
0655 
0656     kbc->rst = devm_reset_control_get(&pdev->dev, "kbc");
0657     if (IS_ERR(kbc->rst)) {
0658         dev_err(&pdev->dev, "failed to get keyboard reset\n");
0659         return PTR_ERR(kbc->rst);
0660     }
0661 
0662     /*
0663      * The time delay between two consecutive reads of the FIFO is
0664      * the sum of the repeat time and the time taken for scanning
0665      * the rows. There is an additional delay before the row scanning
0666      * starts. The repoll delay is computed in milliseconds.
0667      */
0668     debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
0669     scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
0670     kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + kbc->repeat_cnt;
0671     kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS);
0672 
0673     kbc->idev->name = pdev->name;
0674     kbc->idev->id.bustype = BUS_HOST;
0675     kbc->idev->dev.parent = &pdev->dev;
0676     kbc->idev->open = tegra_kbc_open;
0677     kbc->idev->close = tegra_kbc_close;
0678 
0679     if (kbc->keymap_data && kbc->use_fn_map)
0680         keymap_rows *= 2;
0681 
0682     err = matrix_keypad_build_keymap(kbc->keymap_data, NULL,
0683                      keymap_rows,
0684                      kbc->hw_support->max_columns,
0685                      kbc->keycode, kbc->idev);
0686     if (err) {
0687         dev_err(&pdev->dev, "failed to setup keymap\n");
0688         return err;
0689     }
0690 
0691     __set_bit(EV_REP, kbc->idev->evbit);
0692     input_set_capability(kbc->idev, EV_MSC, MSC_SCAN);
0693 
0694     input_set_drvdata(kbc->idev, kbc);
0695 
0696     err = devm_request_irq(&pdev->dev, kbc->irq, tegra_kbc_isr,
0697                    IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN,
0698                    pdev->name, kbc);
0699     if (err) {
0700         dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
0701         return err;
0702     }
0703 
0704     err = input_register_device(kbc->idev);
0705     if (err) {
0706         dev_err(&pdev->dev, "failed to register input device\n");
0707         return err;
0708     }
0709 
0710     platform_set_drvdata(pdev, kbc);
0711     device_init_wakeup(&pdev->dev, kbc->wakeup);
0712 
0713     return 0;
0714 }
0715 
0716 #ifdef CONFIG_PM_SLEEP
0717 static void tegra_kbc_set_keypress_interrupt(struct tegra_kbc *kbc, bool enable)
0718 {
0719     u32 val;
0720 
0721     val = readl(kbc->mmio + KBC_CONTROL_0);
0722     if (enable)
0723         val |= KBC_CONTROL_KEYPRESS_INT_EN;
0724     else
0725         val &= ~KBC_CONTROL_KEYPRESS_INT_EN;
0726     writel(val, kbc->mmio + KBC_CONTROL_0);
0727 }
0728 
0729 static int tegra_kbc_suspend(struct device *dev)
0730 {
0731     struct platform_device *pdev = to_platform_device(dev);
0732     struct tegra_kbc *kbc = platform_get_drvdata(pdev);
0733 
0734     mutex_lock(&kbc->idev->mutex);
0735     if (device_may_wakeup(&pdev->dev)) {
0736         disable_irq(kbc->irq);
0737         del_timer_sync(&kbc->timer);
0738         tegra_kbc_set_fifo_interrupt(kbc, false);
0739 
0740         /* Forcefully clear the interrupt status */
0741         writel(0x7, kbc->mmio + KBC_INT_0);
0742         /*
0743          * Store the previous resident time of continuous polling mode.
0744          * Force the keyboard into interrupt mode.
0745          */
0746         kbc->cp_to_wkup_dly = readl(kbc->mmio + KBC_TO_CNT_0);
0747         writel(0, kbc->mmio + KBC_TO_CNT_0);
0748 
0749         tegra_kbc_setup_wakekeys(kbc, true);
0750         msleep(30);
0751 
0752         kbc->keypress_caused_wake = false;
0753         /* Enable keypress interrupt before going into suspend. */
0754         tegra_kbc_set_keypress_interrupt(kbc, true);
0755         enable_irq(kbc->irq);
0756         enable_irq_wake(kbc->irq);
0757     } else {
0758         if (input_device_enabled(kbc->idev))
0759             tegra_kbc_stop(kbc);
0760     }
0761     mutex_unlock(&kbc->idev->mutex);
0762 
0763     return 0;
0764 }
0765 
0766 static int tegra_kbc_resume(struct device *dev)
0767 {
0768     struct platform_device *pdev = to_platform_device(dev);
0769     struct tegra_kbc *kbc = platform_get_drvdata(pdev);
0770     int err = 0;
0771 
0772     mutex_lock(&kbc->idev->mutex);
0773     if (device_may_wakeup(&pdev->dev)) {
0774         disable_irq_wake(kbc->irq);
0775         tegra_kbc_setup_wakekeys(kbc, false);
0776         /* We will use fifo interrupts for key detection. */
0777         tegra_kbc_set_keypress_interrupt(kbc, false);
0778 
0779         /* Restore the resident time of continuous polling mode. */
0780         writel(kbc->cp_to_wkup_dly, kbc->mmio + KBC_TO_CNT_0);
0781 
0782         tegra_kbc_set_fifo_interrupt(kbc, true);
0783 
0784         if (kbc->keypress_caused_wake && kbc->wakeup_key) {
0785             /*
0786              * We can't report events directly from the ISR
0787              * because timekeeping is stopped when processing
0788              * wakeup request and we get a nasty warning when
0789              * we try to call do_gettimeofday() in evdev
0790              * handler.
0791              */
0792             input_report_key(kbc->idev, kbc->wakeup_key, 1);
0793             input_sync(kbc->idev);
0794             input_report_key(kbc->idev, kbc->wakeup_key, 0);
0795             input_sync(kbc->idev);
0796         }
0797     } else {
0798         if (input_device_enabled(kbc->idev))
0799             err = tegra_kbc_start(kbc);
0800     }
0801     mutex_unlock(&kbc->idev->mutex);
0802 
0803     return err;
0804 }
0805 #endif
0806 
0807 static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume);
0808 
0809 static struct platform_driver tegra_kbc_driver = {
0810     .probe      = tegra_kbc_probe,
0811     .driver = {
0812         .name   = "tegra-kbc",
0813         .pm = &tegra_kbc_pm_ops,
0814         .of_match_table = tegra_kbc_of_match,
0815     },
0816 };
0817 module_platform_driver(tegra_kbc_driver);
0818 
0819 MODULE_LICENSE("GPL");
0820 MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
0821 MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
0822 MODULE_ALIAS("platform:tegra-kbc");
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