sw/rxe/rxe_opcode.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
0002 /*
0003  * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.
0004  * Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.
0005  */
0006
0007 #ifndef RXE_OPCODE_H
0008 #define RXE_OPCODE_H
0009
0010 /*
0011  * contains header bit mask definitions and header lengths
0012  * declaration of the rxe_opcode_info struct and
0013  * rxe_wr_opcode_info struct
0014  */
0015
0016 enum rxe_wr_mask {
0017     WR_INLINE_MASK          = BIT(0),
0018     WR_ATOMIC_MASK          = BIT(1),
0019     WR_SEND_MASK            = BIT(2),
0020     WR_READ_MASK            = BIT(3),
0021     WR_WRITE_MASK           = BIT(4),
0022     WR_LOCAL_OP_MASK        = BIT(5),
0023
0024     WR_READ_OR_WRITE_MASK       = WR_READ_MASK | WR_WRITE_MASK,
0025     WR_WRITE_OR_SEND_MASK       = WR_WRITE_MASK | WR_SEND_MASK,
0026     WR_ATOMIC_OR_READ_MASK      = WR_ATOMIC_MASK | WR_READ_MASK,
0027 };
0028
0029 #define WR_MAX_QPT      (8)
0030
0031 struct rxe_wr_opcode_info {
0032     char            *name;
0033     enum rxe_wr_mask    mask[WR_MAX_QPT];
0034 };
0035
0036 extern struct rxe_wr_opcode_info rxe_wr_opcode_info[];
0037
0038 enum rxe_hdr_type {
0039     RXE_LRH,
0040     RXE_GRH,
0041     RXE_BTH,
0042     RXE_RETH,
0043     RXE_AETH,
0044     RXE_ATMETH,
0045     RXE_ATMACK,
0046     RXE_IETH,
0047     RXE_RDETH,
0048     RXE_DETH,
0049     RXE_IMMDT,
0050     RXE_PAYLOAD,
0051     NUM_HDR_TYPES
0052 };
0053
0054 enum rxe_hdr_mask {
0055     RXE_LRH_MASK        = BIT(RXE_LRH),
0056     RXE_GRH_MASK        = BIT(RXE_GRH),
0057     RXE_BTH_MASK        = BIT(RXE_BTH),
0058     RXE_IMMDT_MASK      = BIT(RXE_IMMDT),
0059     RXE_RETH_MASK       = BIT(RXE_RETH),
0060     RXE_AETH_MASK       = BIT(RXE_AETH),
0061     RXE_ATMETH_MASK     = BIT(RXE_ATMETH),
0062     RXE_ATMACK_MASK     = BIT(RXE_ATMACK),
0063     RXE_IETH_MASK       = BIT(RXE_IETH),
0064     RXE_RDETH_MASK      = BIT(RXE_RDETH),
0065     RXE_DETH_MASK       = BIT(RXE_DETH),
0066     RXE_PAYLOAD_MASK    = BIT(RXE_PAYLOAD),
0067
0068     RXE_REQ_MASK        = BIT(NUM_HDR_TYPES + 0),
0069     RXE_ACK_MASK        = BIT(NUM_HDR_TYPES + 1),
0070     RXE_SEND_MASK       = BIT(NUM_HDR_TYPES + 2),
0071     RXE_WRITE_MASK      = BIT(NUM_HDR_TYPES + 3),
0072     RXE_READ_MASK       = BIT(NUM_HDR_TYPES + 4),
0073     RXE_ATOMIC_MASK     = BIT(NUM_HDR_TYPES + 5),
0074
0075     RXE_RWR_MASK        = BIT(NUM_HDR_TYPES + 6),
0076     RXE_COMP_MASK       = BIT(NUM_HDR_TYPES + 7),
0077
0078     RXE_START_MASK      = BIT(NUM_HDR_TYPES + 8),
0079     RXE_MIDDLE_MASK     = BIT(NUM_HDR_TYPES + 9),
0080     RXE_END_MASK        = BIT(NUM_HDR_TYPES + 10),
0081
0082     RXE_LOOPBACK_MASK   = BIT(NUM_HDR_TYPES + 12),
0083
0084     RXE_READ_OR_ATOMIC_MASK = (RXE_READ_MASK | RXE_ATOMIC_MASK),
0085     RXE_WRITE_OR_SEND_MASK  = (RXE_WRITE_MASK | RXE_SEND_MASK),
0086     RXE_READ_OR_WRITE_MASK  = (RXE_READ_MASK | RXE_WRITE_MASK),
0087 };
0088
0089 #define OPCODE_NONE     (-1)
0090 #define RXE_NUM_OPCODE      256
0091
0092 struct rxe_opcode_info {
0093     char            *name;
0094     enum rxe_hdr_mask   mask;
0095     int         length;
0096     int         offset[NUM_HDR_TYPES];
0097 };
0098
0099 extern struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE];
0100
0101 #endif /* RXE_OPCODE_H */