hw/vmw_pvrdma/pvrdma_dev_api.h

0001 /*
0002  * Copyright (c) 2012-2016 VMware, Inc.  All rights reserved.
0003  *
0004  * This program is free software; you can redistribute it and/or
0005  * modify it under the terms of EITHER the GNU General Public License
0006  * version 2 as published by the Free Software Foundation or the BSD
0007  * 2-Clause License. This program is distributed in the hope that it
0008  * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
0009  * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
0010  * See the GNU General Public License version 2 for more details at
0011  * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
0012  *
0013  * You should have received a copy of the GNU General Public License
0014  * along with this program available in the file COPYING in the main
0015  * directory of this source tree.
0016  *
0017  * The BSD 2-Clause License
0018  *
0019  *     Redistribution and use in source and binary forms, with or
0020  *     without modification, are permitted provided that the following
0021  *     conditions are met:
0022  *
0023  *      - Redistributions of source code must retain the above
0024  *        copyright notice, this list of conditions and the following
0025  *        disclaimer.
0026  *
0027  *      - Redistributions in binary form must reproduce the above
0028  *        copyright notice, this list of conditions and the following
0029  *        disclaimer in the documentation and/or other materials
0030  *        provided with the distribution.
0031  *
0032  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0033  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0034  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
0035  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
0036  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
0037  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0038  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
0039  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0040  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
0041  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0042  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
0043  * OF THE POSSIBILITY OF SUCH DAMAGE.
0044  */
0045
0046 #ifndef __PVRDMA_DEV_API_H__
0047 #define __PVRDMA_DEV_API_H__
0048
0049 #include <linux/types.h>
0050
0051 #include "pvrdma_verbs.h"
0052
0053 /*
0054  * PVRDMA version macros. Some new features require updates to PVRDMA_VERSION.
0055  * These macros allow us to check for different features if necessary.
0056  */
0057
0058 #define PVRDMA_ROCEV1_VERSION       17
0059 #define PVRDMA_ROCEV2_VERSION       18
0060 #define PVRDMA_PPN64_VERSION        19
0061 #define PVRDMA_QPHANDLE_VERSION     20
0062 #define PVRDMA_VERSION          PVRDMA_QPHANDLE_VERSION
0063
0064 #define PVRDMA_BOARD_ID         1
0065 #define PVRDMA_REV_ID           1
0066
0067 /*
0068  * Masks and accessors for page directory, which is a two-level lookup:
0069  * page directory -> page table -> page. Only one directory for now, but we
0070  * could expand that easily. 9 bits for tables, 9 bits for pages, gives one
0071  * gigabyte for memory regions and so forth.
0072  */
0073
0074 #define PVRDMA_PDIR_SHIFT       18
0075 #define PVRDMA_PTABLE_SHIFT     9
0076 #define PVRDMA_PAGE_DIR_DIR(x)      (((x) >> PVRDMA_PDIR_SHIFT) & 0x1)
0077 #define PVRDMA_PAGE_DIR_TABLE(x)    (((x) >> PVRDMA_PTABLE_SHIFT) & 0x1ff)
0078 #define PVRDMA_PAGE_DIR_PAGE(x)     ((x) & 0x1ff)
0079 #define PVRDMA_PAGE_DIR_MAX_PAGES   (1 * 512 * 512)
0080 #define PVRDMA_MAX_FAST_REG_PAGES   128
0081
0082 /*
0083  * Max MSI-X vectors.
0084  */
0085
0086 #define PVRDMA_MAX_INTERRUPTS   3
0087
0088 /* Register offsets within PCI resource on BAR1. */
0089 #define PVRDMA_REG_VERSION  0x00    /* R: Version of device. */
0090 #define PVRDMA_REG_DSRLOW   0x04    /* W: Device shared region low PA. */
0091 #define PVRDMA_REG_DSRHIGH  0x08    /* W: Device shared region high PA. */
0092 #define PVRDMA_REG_CTL      0x0c    /* W: PVRDMA_DEVICE_CTL */
0093 #define PVRDMA_REG_REQUEST  0x10    /* W: Indicate device request. */
0094 #define PVRDMA_REG_ERR      0x14    /* R: Device error. */
0095 #define PVRDMA_REG_ICR      0x18    /* R: Interrupt cause. */
0096 #define PVRDMA_REG_IMR      0x1c    /* R/W: Interrupt mask. */
0097 #define PVRDMA_REG_MACL     0x20    /* R/W: MAC address low. */
0098 #define PVRDMA_REG_MACH     0x24    /* R/W: MAC address high. */
0099
0100 /* Object flags. */
0101 #define PVRDMA_CQ_FLAG_ARMED_SOL    BIT(0)  /* Armed for solicited-only. */
0102 #define PVRDMA_CQ_FLAG_ARMED        BIT(1)  /* Armed. */
0103 #define PVRDMA_MR_FLAG_DMA      BIT(0)  /* DMA region. */
0104 #define PVRDMA_MR_FLAG_FRMR     BIT(1)  /* Fast reg memory region. */
0105
0106 /*
0107  * Atomic operation capability (masked versions are extended atomic
0108  * operations.
0109  */
0110
0111 #define PVRDMA_ATOMIC_OP_COMP_SWAP  BIT(0)  /* Compare and swap. */
0112 #define PVRDMA_ATOMIC_OP_FETCH_ADD  BIT(1)  /* Fetch and add. */
0113 #define PVRDMA_ATOMIC_OP_MASK_COMP_SWAP BIT(2)  /* Masked compare and swap. */
0114 #define PVRDMA_ATOMIC_OP_MASK_FETCH_ADD BIT(3)  /* Masked fetch and add. */
0115
0116 /*
0117  * Base Memory Management Extension flags to support Fast Reg Memory Regions
0118  * and Fast Reg Work Requests. Each flag represents a verb operation and we
0119  * must support all of them to qualify for the BMME device cap.
0120  */
0121
0122 #define PVRDMA_BMME_FLAG_LOCAL_INV  BIT(0)  /* Local Invalidate. */
0123 #define PVRDMA_BMME_FLAG_REMOTE_INV BIT(1)  /* Remote Invalidate. */
0124 #define PVRDMA_BMME_FLAG_FAST_REG_WR    BIT(2)  /* Fast Reg Work Request. */
0125
0126 /*
0127  * GID types. The interpretation of the gid_types bit field in the device
0128  * capabilities will depend on the device mode. For now, the device only
0129  * supports RoCE as mode, so only the different GID types for RoCE are
0130  * defined.
0131  */
0132
0133 #define PVRDMA_GID_TYPE_FLAG_ROCE_V1    BIT(0)
0134 #define PVRDMA_GID_TYPE_FLAG_ROCE_V2    BIT(1)
0135
0136 /*
0137  * Version checks. This checks whether each version supports specific
0138  * capabilities from the device.
0139  */
0140
0141 #define PVRDMA_IS_VERSION17(_dev)                   \
0142     (_dev->dsr_version == PVRDMA_ROCEV1_VERSION &&          \
0143      _dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V1)
0144
0145 #define PVRDMA_IS_VERSION18(_dev)                   \
0146     (_dev->dsr_version >= PVRDMA_ROCEV2_VERSION &&          \
0147      (_dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V1 ||  \
0148       _dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V2))   \
0149
0150 #define PVRDMA_SUPPORTED(_dev)                      \
0151     ((_dev->dsr->caps.mode == PVRDMA_DEVICE_MODE_ROCE) &&       \
0152      (PVRDMA_IS_VERSION17(_dev) || PVRDMA_IS_VERSION18(_dev)))
0153
0154 /*
0155  * Get capability values based on device version.
0156  */
0157
0158 #define PVRDMA_GET_CAP(_dev, _old_val, _val) \
0159     ((PVRDMA_IS_VERSION18(_dev)) ? _val : _old_val)
0160
0161 enum pvrdma_pci_resource {
0162     PVRDMA_PCI_RESOURCE_MSIX,   /* BAR0: MSI-X, MMIO. */
0163     PVRDMA_PCI_RESOURCE_REG,    /* BAR1: Registers, MMIO. */
0164     PVRDMA_PCI_RESOURCE_UAR,    /* BAR2: UAR pages, MMIO, 64-bit. */
0165     PVRDMA_PCI_RESOURCE_LAST,   /* Last. */
0166 };
0167
0168 enum pvrdma_device_ctl {
0169     PVRDMA_DEVICE_CTL_ACTIVATE, /* Activate device. */
0170     PVRDMA_DEVICE_CTL_UNQUIESCE,    /* Unquiesce device. */
0171     PVRDMA_DEVICE_CTL_RESET,    /* Reset device. */
0172 };
0173
0174 enum pvrdma_intr_vector {
0175     PVRDMA_INTR_VECTOR_RESPONSE,    /* Command response. */
0176     PVRDMA_INTR_VECTOR_ASYNC,   /* Async events. */
0177     PVRDMA_INTR_VECTOR_CQ,      /* CQ notification. */
0178     /* Additional CQ notification vectors. */
0179 };
0180
0181 enum pvrdma_intr_cause {
0182     PVRDMA_INTR_CAUSE_RESPONSE  = (1 << PVRDMA_INTR_VECTOR_RESPONSE),
0183     PVRDMA_INTR_CAUSE_ASYNC     = (1 << PVRDMA_INTR_VECTOR_ASYNC),
0184     PVRDMA_INTR_CAUSE_CQ        = (1 << PVRDMA_INTR_VECTOR_CQ),
0185 };
0186
0187 enum pvrdma_gos_bits {
0188     PVRDMA_GOS_BITS_UNK,        /* Unknown. */
0189     PVRDMA_GOS_BITS_32,     /* 32-bit. */
0190     PVRDMA_GOS_BITS_64,     /* 64-bit. */
0191 };
0192
0193 enum pvrdma_gos_type {
0194     PVRDMA_GOS_TYPE_UNK,        /* Unknown. */
0195     PVRDMA_GOS_TYPE_LINUX,      /* Linux. */
0196 };
0197
0198 enum pvrdma_device_mode {
0199     PVRDMA_DEVICE_MODE_ROCE,    /* RoCE. */
0200     PVRDMA_DEVICE_MODE_IWARP,   /* iWarp. */
0201     PVRDMA_DEVICE_MODE_IB,      /* InfiniBand. */
0202 };
0203
0204 struct pvrdma_gos_info {
0205     u32 gos_bits:2;         /* W: PVRDMA_GOS_BITS_ */
0206     u32 gos_type:4;         /* W: PVRDMA_GOS_TYPE_ */
0207     u32 gos_ver:16;         /* W: Guest OS version. */
0208     u32 gos_misc:10;        /* W: Other. */
0209     u32 pad;            /* Pad to 8-byte alignment. */
0210 };
0211
0212 struct pvrdma_device_caps {
0213     u64 fw_ver;             /* R: Query device. */
0214     __be64 node_guid;
0215     __be64 sys_image_guid;
0216     u64 max_mr_size;
0217     u64 page_size_cap;
0218     u64 atomic_arg_sizes;           /* EX verbs. */
0219     u32 ex_comp_mask;           /* EX verbs. */
0220     u32 device_cap_flags2;          /* EX verbs. */
0221     u32 max_fa_bit_boundary;        /* EX verbs. */
0222     u32 log_max_atomic_inline_arg;      /* EX verbs. */
0223     u32 vendor_id;
0224     u32 vendor_part_id;
0225     u32 hw_ver;
0226     u32 max_qp;
0227     u32 max_qp_wr;
0228     u32 device_cap_flags;
0229     u32 max_sge;
0230     u32 max_sge_rd;
0231     u32 max_cq;
0232     u32 max_cqe;
0233     u32 max_mr;
0234     u32 max_pd;
0235     u32 max_qp_rd_atom;
0236     u32 max_ee_rd_atom;
0237     u32 max_res_rd_atom;
0238     u32 max_qp_init_rd_atom;
0239     u32 max_ee_init_rd_atom;
0240     u32 max_ee;
0241     u32 max_rdd;
0242     u32 max_mw;
0243     u32 max_raw_ipv6_qp;
0244     u32 max_raw_ethy_qp;
0245     u32 max_mcast_grp;
0246     u32 max_mcast_qp_attach;
0247     u32 max_total_mcast_qp_attach;
0248     u32 max_ah;
0249     u32 max_fmr;
0250     u32 max_map_per_fmr;
0251     u32 max_srq;
0252     u32 max_srq_wr;
0253     u32 max_srq_sge;
0254     u32 max_uar;
0255     u32 gid_tbl_len;
0256     u16 max_pkeys;
0257     u8  local_ca_ack_delay;
0258     u8  phys_port_cnt;
0259     u8  mode;               /* PVRDMA_DEVICE_MODE_ */
0260     u8  atomic_ops;             /* PVRDMA_ATOMIC_OP_* bits */
0261     u8  bmme_flags;             /* FRWR Mem Mgmt Extensions */
0262     u8  gid_types;              /* PVRDMA_GID_TYPE_FLAG_ */
0263     u32 max_fast_reg_page_list_len;
0264 };
0265
0266 struct pvrdma_ring_page_info {
0267     u32 num_pages;              /* Num pages incl. header. */
0268     u32 reserved;               /* Reserved. */
0269     u64 pdir_dma;               /* Page directory PA. */
0270 };
0271
0272 #pragma pack(push, 1)
0273
0274 struct pvrdma_device_shared_region {
0275     u32 driver_version;         /* W: Driver version. */
0276     u32 pad;                /* Pad to 8-byte align. */
0277     struct pvrdma_gos_info gos_info;    /* W: Guest OS information. */
0278     u64 cmd_slot_dma;           /* W: Command slot address. */
0279     u64 resp_slot_dma;          /* W: Response slot address. */
0280     struct pvrdma_ring_page_info async_ring_pages;
0281                         /* W: Async ring page info. */
0282     struct pvrdma_ring_page_info cq_ring_pages;
0283                         /* W: CQ ring page info. */
0284     union {
0285         u32 uar_pfn;            /* W: UAR pageframe. */
0286         u64 uar_pfn64;          /* W: 64-bit UAR page frame. */
0287     };
0288     struct pvrdma_device_caps caps;     /* R: Device capabilities. */
0289 };
0290
0291 #pragma pack(pop)
0292
0293 /* Event types. Currently a 1:1 mapping with enum ib_event. */
0294 enum pvrdma_eqe_type {
0295     PVRDMA_EVENT_CQ_ERR,
0296     PVRDMA_EVENT_QP_FATAL,
0297     PVRDMA_EVENT_QP_REQ_ERR,
0298     PVRDMA_EVENT_QP_ACCESS_ERR,
0299     PVRDMA_EVENT_COMM_EST,
0300     PVRDMA_EVENT_SQ_DRAINED,
0301     PVRDMA_EVENT_PATH_MIG,
0302     PVRDMA_EVENT_PATH_MIG_ERR,
0303     PVRDMA_EVENT_DEVICE_FATAL,
0304     PVRDMA_EVENT_PORT_ACTIVE,
0305     PVRDMA_EVENT_PORT_ERR,
0306     PVRDMA_EVENT_LID_CHANGE,
0307     PVRDMA_EVENT_PKEY_CHANGE,
0308     PVRDMA_EVENT_SM_CHANGE,
0309     PVRDMA_EVENT_SRQ_ERR,
0310     PVRDMA_EVENT_SRQ_LIMIT_REACHED,
0311     PVRDMA_EVENT_QP_LAST_WQE_REACHED,
0312     PVRDMA_EVENT_CLIENT_REREGISTER,
0313     PVRDMA_EVENT_GID_CHANGE,
0314 };
0315
0316 /* Event queue element. */
0317 struct pvrdma_eqe {
0318     u32 type;   /* Event type. */
0319     u32 info;   /* Handle, other. */
0320 };
0321
0322 /* CQ notification queue element. */
0323 struct pvrdma_cqne {
0324     u32 info;   /* Handle */
0325 };
0326
0327 enum {
0328     PVRDMA_CMD_FIRST,
0329     PVRDMA_CMD_QUERY_PORT = PVRDMA_CMD_FIRST,
0330     PVRDMA_CMD_QUERY_PKEY,
0331     PVRDMA_CMD_CREATE_PD,
0332     PVRDMA_CMD_DESTROY_PD,
0333     PVRDMA_CMD_CREATE_MR,
0334     PVRDMA_CMD_DESTROY_MR,
0335     PVRDMA_CMD_CREATE_CQ,
0336     PVRDMA_CMD_RESIZE_CQ,
0337     PVRDMA_CMD_DESTROY_CQ,
0338     PVRDMA_CMD_CREATE_QP,
0339     PVRDMA_CMD_MODIFY_QP,
0340     PVRDMA_CMD_QUERY_QP,
0341     PVRDMA_CMD_DESTROY_QP,
0342     PVRDMA_CMD_CREATE_UC,
0343     PVRDMA_CMD_DESTROY_UC,
0344     PVRDMA_CMD_CREATE_BIND,
0345     PVRDMA_CMD_DESTROY_BIND,
0346     PVRDMA_CMD_CREATE_SRQ,
0347     PVRDMA_CMD_MODIFY_SRQ,
0348     PVRDMA_CMD_QUERY_SRQ,
0349     PVRDMA_CMD_DESTROY_SRQ,
0350     PVRDMA_CMD_MAX,
0351 };
0352
0353 enum {
0354     PVRDMA_CMD_FIRST_RESP = (1 << 31),
0355     PVRDMA_CMD_QUERY_PORT_RESP = PVRDMA_CMD_FIRST_RESP,
0356     PVRDMA_CMD_QUERY_PKEY_RESP,
0357     PVRDMA_CMD_CREATE_PD_RESP,
0358     PVRDMA_CMD_DESTROY_PD_RESP_NOOP,
0359     PVRDMA_CMD_CREATE_MR_RESP,
0360     PVRDMA_CMD_DESTROY_MR_RESP_NOOP,
0361     PVRDMA_CMD_CREATE_CQ_RESP,
0362     PVRDMA_CMD_RESIZE_CQ_RESP,
0363     PVRDMA_CMD_DESTROY_CQ_RESP_NOOP,
0364     PVRDMA_CMD_CREATE_QP_RESP,
0365     PVRDMA_CMD_MODIFY_QP_RESP,
0366     PVRDMA_CMD_QUERY_QP_RESP,
0367     PVRDMA_CMD_DESTROY_QP_RESP,
0368     PVRDMA_CMD_CREATE_UC_RESP,
0369     PVRDMA_CMD_DESTROY_UC_RESP_NOOP,
0370     PVRDMA_CMD_CREATE_BIND_RESP_NOOP,
0371     PVRDMA_CMD_DESTROY_BIND_RESP_NOOP,
0372     PVRDMA_CMD_CREATE_SRQ_RESP,
0373     PVRDMA_CMD_MODIFY_SRQ_RESP,
0374     PVRDMA_CMD_QUERY_SRQ_RESP,
0375     PVRDMA_CMD_DESTROY_SRQ_RESP,
0376     PVRDMA_CMD_MAX_RESP,
0377 };
0378
0379 struct pvrdma_cmd_hdr {
0380     u64 response;       /* Key for response lookup. */
0381     u32 cmd;        /* PVRDMA_CMD_ */
0382     u32 reserved;       /* Reserved. */
0383 };
0384
0385 struct pvrdma_cmd_resp_hdr {
0386     u64 response;       /* From cmd hdr. */
0387     u32 ack;        /* PVRDMA_CMD_XXX_RESP */
0388     u8 err;         /* Error. */
0389     u8 reserved[3];     /* Reserved. */
0390 };
0391
0392 struct pvrdma_cmd_query_port {
0393     struct pvrdma_cmd_hdr hdr;
0394     u8 port_num;
0395     u8 reserved[7];
0396 };
0397
0398 struct pvrdma_cmd_query_port_resp {
0399     struct pvrdma_cmd_resp_hdr hdr;
0400     struct pvrdma_port_attr attrs;
0401 };
0402
0403 struct pvrdma_cmd_query_pkey {
0404     struct pvrdma_cmd_hdr hdr;
0405     u8 port_num;
0406     u8 index;
0407     u8 reserved[6];
0408 };
0409
0410 struct pvrdma_cmd_query_pkey_resp {
0411     struct pvrdma_cmd_resp_hdr hdr;
0412     u16 pkey;
0413     u8 reserved[6];
0414 };
0415
0416 struct pvrdma_cmd_create_uc {
0417     struct pvrdma_cmd_hdr hdr;
0418     union {
0419         u32 pfn; /* UAR page frame number */
0420         u64 pfn64; /* 64-bit UAR page frame number */
0421     };
0422 };
0423
0424 struct pvrdma_cmd_create_uc_resp {
0425     struct pvrdma_cmd_resp_hdr hdr;
0426     u32 ctx_handle;
0427     u8 reserved[4];
0428 };
0429
0430 struct pvrdma_cmd_destroy_uc {
0431     struct pvrdma_cmd_hdr hdr;
0432     u32 ctx_handle;
0433     u8 reserved[4];
0434 };
0435
0436 struct pvrdma_cmd_create_pd {
0437     struct pvrdma_cmd_hdr hdr;
0438     u32 ctx_handle;
0439     u8 reserved[4];
0440 };
0441
0442 struct pvrdma_cmd_create_pd_resp {
0443     struct pvrdma_cmd_resp_hdr hdr;
0444     u32 pd_handle;
0445     u8 reserved[4];
0446 };
0447
0448 struct pvrdma_cmd_destroy_pd {
0449     struct pvrdma_cmd_hdr hdr;
0450     u32 pd_handle;
0451     u8 reserved[4];
0452 };
0453
0454 struct pvrdma_cmd_create_mr {
0455     struct pvrdma_cmd_hdr hdr;
0456     u64 start;
0457     u64 length;
0458     u64 pdir_dma;
0459     u32 pd_handle;
0460     u32 access_flags;
0461     u32 flags;
0462     u32 nchunks;
0463 };
0464
0465 struct pvrdma_cmd_create_mr_resp {
0466     struct pvrdma_cmd_resp_hdr hdr;
0467     u32 mr_handle;
0468     u32 lkey;
0469     u32 rkey;
0470     u8 reserved[4];
0471 };
0472
0473 struct pvrdma_cmd_destroy_mr {
0474     struct pvrdma_cmd_hdr hdr;
0475     u32 mr_handle;
0476     u8 reserved[4];
0477 };
0478
0479 struct pvrdma_cmd_create_cq {
0480     struct pvrdma_cmd_hdr hdr;
0481     u64 pdir_dma;
0482     u32 ctx_handle;
0483     u32 cqe;
0484     u32 nchunks;
0485     u8 reserved[4];
0486 };
0487
0488 struct pvrdma_cmd_create_cq_resp {
0489     struct pvrdma_cmd_resp_hdr hdr;
0490     u32 cq_handle;
0491     u32 cqe;
0492 };
0493
0494 struct pvrdma_cmd_resize_cq {
0495     struct pvrdma_cmd_hdr hdr;
0496     u32 cq_handle;
0497     u32 cqe;
0498 };
0499
0500 struct pvrdma_cmd_resize_cq_resp {
0501     struct pvrdma_cmd_resp_hdr hdr;
0502     u32 cqe;
0503     u8 reserved[4];
0504 };
0505
0506 struct pvrdma_cmd_destroy_cq {
0507     struct pvrdma_cmd_hdr hdr;
0508     u32 cq_handle;
0509     u8 reserved[4];
0510 };
0511
0512 struct pvrdma_cmd_create_srq {
0513     struct pvrdma_cmd_hdr hdr;
0514     u64 pdir_dma;
0515     u32 pd_handle;
0516     u32 nchunks;
0517     struct pvrdma_srq_attr attrs;
0518     u8 srq_type;
0519     u8 reserved[7];
0520 };
0521
0522 struct pvrdma_cmd_create_srq_resp {
0523     struct pvrdma_cmd_resp_hdr hdr;
0524     u32 srqn;
0525     u8 reserved[4];
0526 };
0527
0528 struct pvrdma_cmd_modify_srq {
0529     struct pvrdma_cmd_hdr hdr;
0530     u32 srq_handle;
0531     u32 attr_mask;
0532     struct pvrdma_srq_attr attrs;
0533 };
0534
0535 struct pvrdma_cmd_query_srq {
0536     struct pvrdma_cmd_hdr hdr;
0537     u32 srq_handle;
0538     u8 reserved[4];
0539 };
0540
0541 struct pvrdma_cmd_query_srq_resp {
0542     struct pvrdma_cmd_resp_hdr hdr;
0543     struct pvrdma_srq_attr attrs;
0544 };
0545
0546 struct pvrdma_cmd_destroy_srq {
0547     struct pvrdma_cmd_hdr hdr;
0548     u32 srq_handle;
0549     u8 reserved[4];
0550 };
0551
0552 struct pvrdma_cmd_create_qp {
0553     struct pvrdma_cmd_hdr hdr;
0554     u64 pdir_dma;
0555     u32 pd_handle;
0556     u32 send_cq_handle;
0557     u32 recv_cq_handle;
0558     u32 srq_handle;
0559     u32 max_send_wr;
0560     u32 max_recv_wr;
0561     u32 max_send_sge;
0562     u32 max_recv_sge;
0563     u32 max_inline_data;
0564     u32 lkey;
0565     u32 access_flags;
0566     u16 total_chunks;
0567     u16 send_chunks;
0568     u16 max_atomic_arg;
0569     u8 sq_sig_all;
0570     u8 qp_type;
0571     u8 is_srq;
0572     u8 reserved[3];
0573 };
0574
0575 struct pvrdma_cmd_create_qp_resp {
0576     struct pvrdma_cmd_resp_hdr hdr;
0577     u32 qpn;
0578     u32 max_send_wr;
0579     u32 max_recv_wr;
0580     u32 max_send_sge;
0581     u32 max_recv_sge;
0582     u32 max_inline_data;
0583 };
0584
0585 struct pvrdma_cmd_create_qp_resp_v2 {
0586     struct pvrdma_cmd_resp_hdr hdr;
0587     u32 qpn;
0588     u32 qp_handle;
0589     u32 max_send_wr;
0590     u32 max_recv_wr;
0591     u32 max_send_sge;
0592     u32 max_recv_sge;
0593     u32 max_inline_data;
0594 };
0595
0596 struct pvrdma_cmd_modify_qp {
0597     struct pvrdma_cmd_hdr hdr;
0598     u32 qp_handle;
0599     u32 attr_mask;
0600     struct pvrdma_qp_attr attrs;
0601 };
0602
0603 struct pvrdma_cmd_query_qp {
0604     struct pvrdma_cmd_hdr hdr;
0605     u32 qp_handle;
0606     u32 attr_mask;
0607 };
0608
0609 struct pvrdma_cmd_query_qp_resp {
0610     struct pvrdma_cmd_resp_hdr hdr;
0611     struct pvrdma_qp_attr attrs;
0612 };
0613
0614 struct pvrdma_cmd_destroy_qp {
0615     struct pvrdma_cmd_hdr hdr;
0616     u32 qp_handle;
0617     u8 reserved[4];
0618 };
0619
0620 struct pvrdma_cmd_destroy_qp_resp {
0621     struct pvrdma_cmd_resp_hdr hdr;
0622     u32 events_reported;
0623     u8 reserved[4];
0624 };
0625
0626 struct pvrdma_cmd_create_bind {
0627     struct pvrdma_cmd_hdr hdr;
0628     u32 mtu;
0629     u32 vlan;
0630     u32 index;
0631     u8 new_gid[16];
0632     u8 gid_type;
0633     u8 reserved[3];
0634 };
0635
0636 struct pvrdma_cmd_destroy_bind {
0637     struct pvrdma_cmd_hdr hdr;
0638     u32 index;
0639     u8 dest_gid[16];
0640     u8 reserved[4];
0641 };
0642
0643 union pvrdma_cmd_req {
0644     struct pvrdma_cmd_hdr hdr;
0645     struct pvrdma_cmd_query_port query_port;
0646     struct pvrdma_cmd_query_pkey query_pkey;
0647     struct pvrdma_cmd_create_uc create_uc;
0648     struct pvrdma_cmd_destroy_uc destroy_uc;
0649     struct pvrdma_cmd_create_pd create_pd;
0650     struct pvrdma_cmd_destroy_pd destroy_pd;
0651     struct pvrdma_cmd_create_mr create_mr;
0652     struct pvrdma_cmd_destroy_mr destroy_mr;
0653     struct pvrdma_cmd_create_cq create_cq;
0654     struct pvrdma_cmd_resize_cq resize_cq;
0655     struct pvrdma_cmd_destroy_cq destroy_cq;
0656     struct pvrdma_cmd_create_qp create_qp;
0657     struct pvrdma_cmd_modify_qp modify_qp;
0658     struct pvrdma_cmd_query_qp query_qp;
0659     struct pvrdma_cmd_destroy_qp destroy_qp;
0660     struct pvrdma_cmd_create_bind create_bind;
0661     struct pvrdma_cmd_destroy_bind destroy_bind;
0662     struct pvrdma_cmd_create_srq create_srq;
0663     struct pvrdma_cmd_modify_srq modify_srq;
0664     struct pvrdma_cmd_query_srq query_srq;
0665     struct pvrdma_cmd_destroy_srq destroy_srq;
0666 };
0667
0668 union pvrdma_cmd_resp {
0669     struct pvrdma_cmd_resp_hdr hdr;
0670     struct pvrdma_cmd_query_port_resp query_port_resp;
0671     struct pvrdma_cmd_query_pkey_resp query_pkey_resp;
0672     struct pvrdma_cmd_create_uc_resp create_uc_resp;
0673     struct pvrdma_cmd_create_pd_resp create_pd_resp;
0674     struct pvrdma_cmd_create_mr_resp create_mr_resp;
0675     struct pvrdma_cmd_create_cq_resp create_cq_resp;
0676     struct pvrdma_cmd_resize_cq_resp resize_cq_resp;
0677     struct pvrdma_cmd_create_qp_resp create_qp_resp;
0678     struct pvrdma_cmd_create_qp_resp_v2 create_qp_resp_v2;
0679     struct pvrdma_cmd_query_qp_resp query_qp_resp;
0680     struct pvrdma_cmd_destroy_qp_resp destroy_qp_resp;
0681     struct pvrdma_cmd_create_srq_resp create_srq_resp;
0682     struct pvrdma_cmd_query_srq_resp query_srq_resp;
0683 };
0684
0685 #endif /* __PVRDMA_DEV_API_H__ */