hw/mthca/mthca_cmd.h

0001 /*
0002  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
0003  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
0004  * Copyright (c) 2006 Cisco Systems.  All rights reserved.
0005  *
0006  * This software is available to you under a choice of one of two
0007  * licenses.  You may choose to be licensed under the terms of the GNU
0008  * General Public License (GPL) Version 2, available from the file
0009  * COPYING in the main directory of this source tree, or the
0010  * OpenIB.org BSD license below:
0011  *
0012  *     Redistribution and use in source and binary forms, with or
0013  *     without modification, are permitted provided that the following
0014  *     conditions are met:
0015  *
0016  *      - Redistributions of source code must retain the above
0017  *        copyright notice, this list of conditions and the following
0018  *        disclaimer.
0019  *
0020  *      - Redistributions in binary form must reproduce the above
0021  *        copyright notice, this list of conditions and the following
0022  *        disclaimer in the documentation and/or other materials
0023  *        provided with the distribution.
0024  *
0025  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0026  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0027  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0028  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0029  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0030  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0031  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0032  * SOFTWARE.
0033  */
0034
0035 #ifndef MTHCA_CMD_H
0036 #define MTHCA_CMD_H
0037
0038 #include <rdma/ib_verbs.h>
0039
0040 #define MTHCA_MAILBOX_SIZE 4096
0041
0042 enum {
0043     /* command completed successfully: */
0044     MTHCA_CMD_STAT_OK         = 0x00,
0045     /* Internal error (such as a bus error) occurred while processing command: */
0046     MTHCA_CMD_STAT_INTERNAL_ERR   = 0x01,
0047     /* Operation/command not supported or opcode modifier not supported: */
0048     MTHCA_CMD_STAT_BAD_OP         = 0x02,
0049     /* Parameter not supported or parameter out of range: */
0050     MTHCA_CMD_STAT_BAD_PARAM      = 0x03,
0051     /* System not enabled or bad system state: */
0052     MTHCA_CMD_STAT_BAD_SYS_STATE  = 0x04,
0053     /* Attempt to access reserved or unallocaterd resource: */
0054     MTHCA_CMD_STAT_BAD_RESOURCE   = 0x05,
0055     /* Requested resource is currently executing a command, or is otherwise busy: */
0056     MTHCA_CMD_STAT_RESOURCE_BUSY  = 0x06,
0057     /* memory error: */
0058     MTHCA_CMD_STAT_DDR_MEM_ERR    = 0x07,
0059     /* Required capability exceeds device limits: */
0060     MTHCA_CMD_STAT_EXCEED_LIM     = 0x08,
0061     /* Resource is not in the appropriate state or ownership: */
0062     MTHCA_CMD_STAT_BAD_RES_STATE  = 0x09,
0063     /* Index out of range: */
0064     MTHCA_CMD_STAT_BAD_INDEX      = 0x0a,
0065     /* FW image corrupted: */
0066     MTHCA_CMD_STAT_BAD_NVMEM      = 0x0b,
0067     /* Attempt to modify a QP/EE which is not in the presumed state: */
0068     MTHCA_CMD_STAT_BAD_QPEE_STATE = 0x10,
0069     /* Bad segment parameters (Address/Size): */
0070     MTHCA_CMD_STAT_BAD_SEG_PARAM  = 0x20,
0071     /* Memory Region has Memory Windows bound to: */
0072     MTHCA_CMD_STAT_REG_BOUND      = 0x21,
0073     /* HCA local attached memory not present: */
0074     MTHCA_CMD_STAT_LAM_NOT_PRE    = 0x22,
0075     /* Bad management packet (silently discarded): */
0076     MTHCA_CMD_STAT_BAD_PKT        = 0x30,
0077     /* More outstanding CQEs in CQ than new CQ size: */
0078     MTHCA_CMD_STAT_BAD_SIZE       = 0x40
0079 };
0080
0081 enum {
0082     MTHCA_TRANS_INVALID = 0,
0083     MTHCA_TRANS_RST2INIT,
0084     MTHCA_TRANS_INIT2INIT,
0085     MTHCA_TRANS_INIT2RTR,
0086     MTHCA_TRANS_RTR2RTS,
0087     MTHCA_TRANS_RTS2RTS,
0088     MTHCA_TRANS_SQERR2RTS,
0089     MTHCA_TRANS_ANY2ERR,
0090     MTHCA_TRANS_RTS2SQD,
0091     MTHCA_TRANS_SQD2SQD,
0092     MTHCA_TRANS_SQD2RTS,
0093     MTHCA_TRANS_ANY2RST,
0094 };
0095
0096 enum {
0097     DEV_LIM_FLAG_RC                 = 1 << 0,
0098     DEV_LIM_FLAG_UC                 = 1 << 1,
0099     DEV_LIM_FLAG_UD                 = 1 << 2,
0100     DEV_LIM_FLAG_RD                 = 1 << 3,
0101     DEV_LIM_FLAG_RAW_IPV6           = 1 << 4,
0102     DEV_LIM_FLAG_RAW_ETHER          = 1 << 5,
0103     DEV_LIM_FLAG_SRQ                = 1 << 6,
0104     DEV_LIM_FLAG_IPOIB_CSUM     = 1 << 7,
0105     DEV_LIM_FLAG_BAD_PKEY_CNTR      = 1 << 8,
0106     DEV_LIM_FLAG_BAD_QKEY_CNTR      = 1 << 9,
0107     DEV_LIM_FLAG_MW                 = 1 << 16,
0108     DEV_LIM_FLAG_AUTO_PATH_MIG      = 1 << 17,
0109     DEV_LIM_FLAG_ATOMIC             = 1 << 18,
0110     DEV_LIM_FLAG_RAW_MULTI          = 1 << 19,
0111     DEV_LIM_FLAG_UD_AV_PORT_ENFORCE = 1 << 20,
0112     DEV_LIM_FLAG_UD_MULTI           = 1 << 21,
0113 };
0114
0115 struct mthca_mailbox {
0116     dma_addr_t dma;
0117     void      *buf;
0118 };
0119
0120 struct mthca_dev_lim {
0121     int max_srq_sz;
0122     int max_qp_sz;
0123     int reserved_qps;
0124     int max_qps;
0125     int reserved_srqs;
0126     int max_srqs;
0127     int reserved_eecs;
0128     int max_eecs;
0129     int max_cq_sz;
0130     int reserved_cqs;
0131     int max_cqs;
0132     int max_mpts;
0133     int reserved_eqs;
0134     int max_eqs;
0135     int reserved_mtts;
0136     int max_mrw_sz;
0137     int reserved_mrws;
0138     int max_mtt_seg;
0139     int max_requester_per_qp;
0140     int max_responder_per_qp;
0141     int max_rdma_global;
0142     int local_ca_ack_delay;
0143     int max_mtu;
0144     int max_port_width;
0145     int max_vl;
0146     int num_ports;
0147     int max_gids;
0148     u16 stat_rate_support;
0149     int max_pkeys;
0150     u32 flags;
0151     int reserved_uars;
0152     int uar_size;
0153     int min_page_sz;
0154     int max_sg;
0155     int max_desc_sz;
0156     int max_qp_per_mcg;
0157     int reserved_mgms;
0158     int max_mcgs;
0159     int reserved_pds;
0160     int max_pds;
0161     int reserved_rdds;
0162     int max_rdds;
0163     int eec_entry_sz;
0164     int qpc_entry_sz;
0165     int eeec_entry_sz;
0166     int eqpc_entry_sz;
0167     int eqc_entry_sz;
0168     int cqc_entry_sz;
0169     int srq_entry_sz;
0170     int uar_scratch_entry_sz;
0171     int mpt_entry_sz;
0172     union {
0173         struct {
0174             int max_avs;
0175         } tavor;
0176         struct {
0177             int resize_srq;
0178             int max_pbl_sz;
0179             u8  bmme_flags;
0180             u32 reserved_lkey;
0181             int lam_required;
0182             u64 max_icm_sz;
0183         } arbel;
0184     } hca;
0185 };
0186
0187 struct mthca_adapter {
0188     u32  vendor_id;
0189     u32  device_id;
0190     u32  revision_id;
0191     char board_id[MTHCA_BOARD_ID_LEN];
0192     u8   inta_pin;
0193 };
0194
0195 struct mthca_init_hca_param {
0196     u64 qpc_base;
0197     u64 eec_base;
0198     u64 srqc_base;
0199     u64 cqc_base;
0200     u64 eqpc_base;
0201     u64 eeec_base;
0202     u64 eqc_base;
0203     u64 rdb_base;
0204     u64 mc_base;
0205     u64 mpt_base;
0206     u64 mtt_base;
0207     u64 uar_scratch_base;
0208     u64 uarc_base;
0209     u16 log_mc_entry_sz;
0210     u16 mc_hash_sz;
0211     u8  log_num_qps;
0212     u8  log_num_eecs;
0213     u8  log_num_srqs;
0214     u8  log_num_cqs;
0215     u8  log_num_eqs;
0216     u8  log_mc_table_sz;
0217     u8  mtt_seg_sz;
0218     u8  log_mpt_sz;
0219     u8  log_uar_sz;
0220     u8  log_uarc_sz;
0221 };
0222
0223 struct mthca_init_ib_param {
0224     int port_width;
0225     int vl_cap;
0226     int mtu_cap;
0227     u16 gid_cap;
0228     u16 pkey_cap;
0229     int set_guid0;
0230     u64 guid0;
0231     int set_node_guid;
0232     u64 node_guid;
0233     int set_si_guid;
0234     u64 si_guid;
0235 };
0236
0237 struct mthca_set_ib_param {
0238     int set_si_guid;
0239     int reset_qkey_viol;
0240     u64 si_guid;
0241     u32 cap_mask;
0242 };
0243
0244 int mthca_cmd_init(struct mthca_dev *dev);
0245 void mthca_cmd_cleanup(struct mthca_dev *dev);
0246 int mthca_cmd_use_events(struct mthca_dev *dev);
0247 void mthca_cmd_use_polling(struct mthca_dev *dev);
0248 void mthca_cmd_event(struct mthca_dev *dev, u16 token,
0249              u8  status, u64 out_param);
0250
0251 struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
0252                       gfp_t gfp_mask);
0253 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox);
0254
0255 int mthca_SYS_EN(struct mthca_dev *dev);
0256 int mthca_SYS_DIS(struct mthca_dev *dev);
0257 int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm);
0258 int mthca_UNMAP_FA(struct mthca_dev *dev);
0259 int mthca_RUN_FW(struct mthca_dev *dev);
0260 int mthca_QUERY_FW(struct mthca_dev *dev);
0261 int mthca_ENABLE_LAM(struct mthca_dev *dev);
0262 int mthca_DISABLE_LAM(struct mthca_dev *dev);
0263 int mthca_QUERY_DDR(struct mthca_dev *dev);
0264 int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
0265             struct mthca_dev_lim *dev_lim);
0266 int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
0267             struct mthca_adapter *adapter);
0268 int mthca_INIT_HCA(struct mthca_dev *dev,
0269            struct mthca_init_hca_param *param);
0270 int mthca_INIT_IB(struct mthca_dev *dev,
0271           struct mthca_init_ib_param *param,
0272           int port);
0273 int mthca_CLOSE_IB(struct mthca_dev *dev, int port);
0274 int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic);
0275 int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
0276          int port);
0277 int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt);
0278 int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt);
0279 int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count);
0280 int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm);
0281 int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev);
0282 int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages);
0283 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
0284             int mpt_index);
0285 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
0286             int mpt_index);
0287 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
0288             int num_mtt);
0289 int mthca_SYNC_TPT(struct mthca_dev *dev);
0290 int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
0291          int eq_num);
0292 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
0293            int eq_num);
0294 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
0295            int eq_num);
0296 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
0297            int cq_num);
0298 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
0299            int cq_num);
0300 int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size);
0301 int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
0302             int srq_num);
0303 int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
0304             int srq_num);
0305 int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num,
0306             struct mthca_mailbox *mailbox);
0307 int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit);
0308 int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
0309             enum ib_qp_state next, u32 num, int is_ee,
0310             struct mthca_mailbox *mailbox, u32 optmask);
0311 int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
0312            struct mthca_mailbox *mailbox);
0313 int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn);
0314 int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
0315           int port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
0316           const void *in_mad, void *response_mad);
0317 int mthca_READ_MGM(struct mthca_dev *dev, int index,
0318            struct mthca_mailbox *mailbox);
0319 int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
0320             struct mthca_mailbox *mailbox);
0321 int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
0322             u16 *hash);
0323 int mthca_NOP(struct mthca_dev *dev);
0324
0325 #endif /* MTHCA_CMD_H */