hw/irdma/uda_d.h

0001 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
0002 /* Copyright (c) 2016 - 2021 Intel Corporation */
0003 #ifndef IRDMA_UDA_D_H
0004 #define IRDMA_UDA_D_H
0005
0006 /* L4 packet type */
0007 #define IRDMA_E_UDA_SQ_L4T_UNKNOWN  0
0008 #define IRDMA_E_UDA_SQ_L4T_TCP      1
0009 #define IRDMA_E_UDA_SQ_L4T_SCTP     2
0010 #define IRDMA_E_UDA_SQ_L4T_UDP      3
0011
0012 /* Inner IP header type */
0013 #define IRDMA_E_UDA_SQ_IIPT_UNKNOWN     0
0014 #define IRDMA_E_UDA_SQ_IIPT_IPV6        1
0015 #define IRDMA_E_UDA_SQ_IIPT_IPV4_NO_CSUM    2
0016 #define IRDMA_E_UDA_SQ_IIPT_IPV4_CSUM       3
0017 #define IRDMA_UDA_QPSQ_PUSHWQE BIT_ULL(56)
0018 #define IRDMA_UDA_QPSQ_INLINEDATAFLAG BIT_ULL(57)
0019 #define IRDMA_UDA_QPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
0020 #define IRDMA_UDA_QPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)
0021 #define IRDMA_UDA_QPSQ_IPFRAGFLAGS GENMASK_ULL(43, 42)
0022 #define IRDMA_UDA_QPSQ_NOCHECKSUM BIT_ULL(45)
0023 #define IRDMA_UDA_QPSQ_AHIDXVALID BIT_ULL(46)
0024 #define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61)
0025 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
0026 #define IRDMA_UDA_QPSQ_PROTOCOL GENMASK_ULL(23, 16)
0027 #define IRDMA_UDA_QPSQ_EXTHDRLEN GENMASK_ULL(40, 32)
0028 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)
0029 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)
0030 #define IRDMA_UDA_QPSQ_MACLEN_LINE 2
0031 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
0032 #define IRDMA_UDA_QPSQ_IPLEN_LINE 2
0033 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)
0034 #define IRDMA_UDA_QPSQ_L4T_LINE 2
0035 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)
0036 #define IRDMA_UDA_QPSQ_IIPT_LINE 2
0037
0038 #define IRDMA_UDA_QPSQ_DO_LPB_LINE 3
0039 #define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM BIT_ULL(45)
0040 #define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM_LINE 3
0041 #define IRDMA_UDA_QPSQ_IMMDATA GENMASK_ULL(63, 0)
0042
0043 /* Byte Offset 0 */
0044 #define IRDMA_UDAQPC_IPV4_M BIT_ULL(3)
0045 #define IRDMA_UDAQPC_INSERTVLANTAG BIT_ULL(5)
0046 #define IRDMA_UDAQPC_ISQP1 BIT_ULL(6)
0047
0048 #define IRDMA_UDAQPC_ECNENABLE BIT_ULL(14)
0049 #define IRDMA_UDAQPC_PDINDEXHI GENMASK_ULL(21, 20)
0050 #define IRDMA_UDAQPC_DCTCPENABLE BIT_ULL(25)
0051
0052 #define IRDMA_UDAQPC_RCVTPHEN IRDMAQPC_RCVTPHEN
0053 #define IRDMA_UDAQPC_XMITTPHEN IRDMAQPC_XMITTPHEN
0054 #define IRDMA_UDAQPC_RQTPHEN IRDMAQPC_RQTPHEN
0055 #define IRDMA_UDAQPC_SQTPHEN IRDMAQPC_SQTPHEN
0056 #define IRDMA_UDAQPC_PPIDX IRDMAQPC_PPIDX
0057 #define IRDMA_UDAQPC_PMENA IRDMAQPC_PMENA
0058 #define IRDMA_UDAQPC_INSERTTAG2 BIT_ULL(11)
0059 #define IRDMA_UDAQPC_INSERTTAG3 BIT_ULL(14)
0060
0061 #define IRDMA_UDAQPC_RQSIZE IRDMAQPC_RQSIZE
0062 #define IRDMA_UDAQPC_SQSIZE IRDMAQPC_SQSIZE
0063 #define IRDMA_UDAQPC_TXCQNUM IRDMAQPC_TXCQNUM
0064 #define IRDMA_UDAQPC_RXCQNUM IRDMAQPC_RXCQNUM
0065 #define IRDMA_UDAQPC_QPCOMPCTX IRDMAQPC_QPCOMPCTX
0066 #define IRDMA_UDAQPC_SQTPHVAL IRDMAQPC_SQTPHVAL
0067 #define IRDMA_UDAQPC_RQTPHVAL IRDMAQPC_RQTPHVAL
0068 #define IRDMA_UDAQPC_QSHANDLE IRDMAQPC_QSHANDLE
0069 #define IRDMA_UDAQPC_RQHDRRINGBUFSIZE GENMASK_ULL(49, 48)
0070 #define IRDMA_UDAQPC_SQHDRRINGBUFSIZE GENMASK_ULL(33, 32)
0071 #define IRDMA_UDAQPC_PRIVILEGEENABLE BIT_ULL(25)
0072 #define IRDMA_UDAQPC_USE_STATISTICS_INSTANCE BIT_ULL(26)
0073 #define IRDMA_UDAQPC_STATISTICS_INSTANCE_INDEX GENMASK_ULL(6, 0)
0074 #define IRDMA_UDAQPC_PRIVHDRGENENABLE BIT_ULL(0)
0075 #define IRDMA_UDAQPC_RQHDRSPLITENABLE BIT_ULL(3)
0076 #define IRDMA_UDAQPC_RQHDRRINGBUFENABLE BIT_ULL(2)
0077 #define IRDMA_UDAQPC_SQHDRRINGBUFENABLE BIT_ULL(1)
0078 #define IRDMA_UDAQPC_IPID GENMASK_ULL(47, 32)
0079 #define IRDMA_UDAQPC_SNDMSS GENMASK_ULL(29, 16)
0080 #define IRDMA_UDAQPC_VLANTAG GENMASK_ULL(15, 0)
0081
0082 #define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI GENMASK_ULL(21, 20)
0083 #define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO GENMASK_ULL(63, 48)
0084 #define IRDMA_UDA_CQPSQ_MAV_SRCMACADDRINDEX GENMASK_ULL(29, 24)
0085 #define IRDMA_UDA_CQPSQ_MAV_ARPINDEX GENMASK_ULL(63, 48)
0086 #define IRDMA_UDA_CQPSQ_MAV_TC GENMASK_ULL(39, 32)
0087 #define IRDMA_UDA_CQPSQ_MAV_HOPLIMIT GENMASK_ULL(39, 32)
0088 #define IRDMA_UDA_CQPSQ_MAV_FLOWLABEL GENMASK_ULL(19, 0)
0089 #define IRDMA_UDA_CQPSQ_MAV_ADDR0 GENMASK_ULL(63, 32)
0090 #define IRDMA_UDA_CQPSQ_MAV_ADDR1 GENMASK_ULL(31, 0)
0091 #define IRDMA_UDA_CQPSQ_MAV_ADDR2 GENMASK_ULL(63, 32)
0092 #define IRDMA_UDA_CQPSQ_MAV_ADDR3 GENMASK_ULL(31, 0)
0093 #define IRDMA_UDA_CQPSQ_MAV_WQEVALID BIT_ULL(63)
0094 #define IRDMA_UDA_CQPSQ_MAV_OPCODE GENMASK_ULL(37, 32)
0095 #define IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK BIT_ULL(62)
0096 #define IRDMA_UDA_CQPSQ_MAV_IPV4VALID BIT_ULL(59)
0097 #define IRDMA_UDA_CQPSQ_MAV_AVIDX GENMASK_ULL(16, 0)
0098 #define IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG BIT_ULL(60)
0099 #define IRDMA_UDA_MGCTX_VFFLAG BIT_ULL(29)
0100 #define IRDMA_UDA_MGCTX_DESTPORT GENMASK_ULL(47, 32)
0101 #define IRDMA_UDA_MGCTX_VFID GENMASK_ULL(28, 22)
0102 #define IRDMA_UDA_MGCTX_VALIDENT BIT_ULL(31)
0103 #define IRDMA_UDA_MGCTX_PFID GENMASK_ULL(21, 18)
0104 #define IRDMA_UDA_MGCTX_FLAGIGNOREDPORT BIT_ULL(30)
0105 #define IRDMA_UDA_MGCTX_QPID GENMASK_ULL(17, 0)
0106 #define IRDMA_UDA_CQPSQ_MG_WQEVALID BIT_ULL(63)
0107 #define IRDMA_UDA_CQPSQ_MG_OPCODE GENMASK_ULL(37, 32)
0108 #define IRDMA_UDA_CQPSQ_MG_MGIDX GENMASK_ULL(12, 0)
0109 #define IRDMA_UDA_CQPSQ_MG_IPV4VALID BIT_ULL(60)
0110 #define IRDMA_UDA_CQPSQ_MG_VLANVALID BIT_ULL(59)
0111 #define IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID GENMASK_ULL(5, 0)
0112 #define IRDMA_UDA_CQPSQ_MG_VLANID GENMASK_ULL(43, 32)
0113 #define IRDMA_UDA_CQPSQ_QS_HANDLE GENMASK_ULL(9, 0)
0114 #define IRDMA_UDA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
0115 #define IRDMA_UDA_CQPSQ_QHASH_ BIT_ULL(0)
0116 #define IRDMA_UDA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)
0117 #define IRDMA_UDA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
0118 #define IRDMA_UDA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
0119 #define IRDMA_UDA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
0120 #define IRDMA_UDA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
0121 #define IRDMA_UDA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
0122 #define IRDMA_UDA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
0123 #define IRDMA_UDA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
0124 #define IRDMA_UDA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61)
0125 #define IRDMA_UDA_CQPSQ_QHASH_IPV4VALID GENMASK_ULL(60, 60)
0126 #define IRDMA_UDA_CQPSQ_QHASH_LANFWD GENMASK_ULL(59, 59)
0127 #define IRDMA_UDA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42)
0128 #endif /* IRDMA_UDA_D_H */