0001
0002
0003 #ifndef IRDMA_TYPE_H
0004 #define IRDMA_TYPE_H
0005 #include "osdep.h"
0006 #include "irdma.h"
0007 #include "user.h"
0008 #include "hmc.h"
0009 #include "uda.h"
0010 #include "ws.h"
0011 #define IRDMA_DEBUG_ERR "ERR"
0012 #define IRDMA_DEBUG_INIT "INIT"
0013 #define IRDMA_DEBUG_DEV "DEV"
0014 #define IRDMA_DEBUG_CM "CM"
0015 #define IRDMA_DEBUG_VERBS "VERBS"
0016 #define IRDMA_DEBUG_PUDA "PUDA"
0017 #define IRDMA_DEBUG_ILQ "ILQ"
0018 #define IRDMA_DEBUG_IEQ "IEQ"
0019 #define IRDMA_DEBUG_QP "QP"
0020 #define IRDMA_DEBUG_CQ "CQ"
0021 #define IRDMA_DEBUG_MR "MR"
0022 #define IRDMA_DEBUG_PBLE "PBLE"
0023 #define IRDMA_DEBUG_WQE "WQE"
0024 #define IRDMA_DEBUG_AEQ "AEQ"
0025 #define IRDMA_DEBUG_CQP "CQP"
0026 #define IRDMA_DEBUG_HMC "HMC"
0027 #define IRDMA_DEBUG_USER "USER"
0028 #define IRDMA_DEBUG_VIRT "VIRT"
0029 #define IRDMA_DEBUG_DCB "DCB"
0030 #define IRDMA_DEBUG_CQE "CQE"
0031 #define IRDMA_DEBUG_CLNT "CLNT"
0032 #define IRDMA_DEBUG_WS "WS"
0033 #define IRDMA_DEBUG_STATS "STATS"
0034
0035 enum irdma_page_size {
0036 IRDMA_PAGE_SIZE_4K = 0,
0037 IRDMA_PAGE_SIZE_2M,
0038 IRDMA_PAGE_SIZE_1G,
0039 };
0040
0041 enum irdma_hdrct_flags {
0042 DDP_LEN_FLAG = 0x80,
0043 DDP_HDR_FLAG = 0x40,
0044 RDMA_HDR_FLAG = 0x20,
0045 };
0046
0047 enum irdma_term_layers {
0048 LAYER_RDMA = 0,
0049 LAYER_DDP = 1,
0050 LAYER_MPA = 2,
0051 };
0052
0053 enum irdma_term_error_types {
0054 RDMAP_REMOTE_PROT = 1,
0055 RDMAP_REMOTE_OP = 2,
0056 DDP_CATASTROPHIC = 0,
0057 DDP_TAGGED_BUF = 1,
0058 DDP_UNTAGGED_BUF = 2,
0059 DDP_LLP = 3,
0060 };
0061
0062 enum irdma_term_rdma_errors {
0063 RDMAP_INV_STAG = 0x00,
0064 RDMAP_INV_BOUNDS = 0x01,
0065 RDMAP_ACCESS = 0x02,
0066 RDMAP_UNASSOC_STAG = 0x03,
0067 RDMAP_TO_WRAP = 0x04,
0068 RDMAP_INV_RDMAP_VER = 0x05,
0069 RDMAP_UNEXPECTED_OP = 0x06,
0070 RDMAP_CATASTROPHIC_LOCAL = 0x07,
0071 RDMAP_CATASTROPHIC_GLOBAL = 0x08,
0072 RDMAP_CANT_INV_STAG = 0x09,
0073 RDMAP_UNSPECIFIED = 0xff,
0074 };
0075
0076 enum irdma_term_ddp_errors {
0077 DDP_CATASTROPHIC_LOCAL = 0x00,
0078 DDP_TAGGED_INV_STAG = 0x00,
0079 DDP_TAGGED_BOUNDS = 0x01,
0080 DDP_TAGGED_UNASSOC_STAG = 0x02,
0081 DDP_TAGGED_TO_WRAP = 0x03,
0082 DDP_TAGGED_INV_DDP_VER = 0x04,
0083 DDP_UNTAGGED_INV_QN = 0x01,
0084 DDP_UNTAGGED_INV_MSN_NO_BUF = 0x02,
0085 DDP_UNTAGGED_INV_MSN_RANGE = 0x03,
0086 DDP_UNTAGGED_INV_MO = 0x04,
0087 DDP_UNTAGGED_INV_TOO_LONG = 0x05,
0088 DDP_UNTAGGED_INV_DDP_VER = 0x06,
0089 };
0090
0091 enum irdma_term_mpa_errors {
0092 MPA_CLOSED = 0x01,
0093 MPA_CRC = 0x02,
0094 MPA_MARKER = 0x03,
0095 MPA_REQ_RSP = 0x04,
0096 };
0097
0098 enum irdma_qp_event_type {
0099 IRDMA_QP_EVENT_CATASTROPHIC,
0100 IRDMA_QP_EVENT_ACCESS_ERR,
0101 };
0102
0103 enum irdma_hw_stats_index_32b {
0104 IRDMA_HW_STAT_INDEX_IP4RXDISCARD = 0,
0105 IRDMA_HW_STAT_INDEX_IP4RXTRUNC = 1,
0106 IRDMA_HW_STAT_INDEX_IP4TXNOROUTE = 2,
0107 IRDMA_HW_STAT_INDEX_IP6RXDISCARD = 3,
0108 IRDMA_HW_STAT_INDEX_IP6RXTRUNC = 4,
0109 IRDMA_HW_STAT_INDEX_IP6TXNOROUTE = 5,
0110 IRDMA_HW_STAT_INDEX_TCPRTXSEG = 6,
0111 IRDMA_HW_STAT_INDEX_TCPRXOPTERR = 7,
0112 IRDMA_HW_STAT_INDEX_TCPRXPROTOERR = 8,
0113 IRDMA_HW_STAT_INDEX_MAX_32_GEN_1 = 9,
0114 IRDMA_HW_STAT_INDEX_RXVLANERR = 9,
0115 IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED = 10,
0116 IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED = 11,
0117 IRDMA_HW_STAT_INDEX_TXNPCNPSENT = 12,
0118 IRDMA_HW_STAT_INDEX_MAX_32,
0119 };
0120
0121 enum irdma_hw_stats_index_64b {
0122 IRDMA_HW_STAT_INDEX_IP4RXOCTS = 0,
0123 IRDMA_HW_STAT_INDEX_IP4RXPKTS = 1,
0124 IRDMA_HW_STAT_INDEX_IP4RXFRAGS = 2,
0125 IRDMA_HW_STAT_INDEX_IP4RXMCPKTS = 3,
0126 IRDMA_HW_STAT_INDEX_IP4TXOCTS = 4,
0127 IRDMA_HW_STAT_INDEX_IP4TXPKTS = 5,
0128 IRDMA_HW_STAT_INDEX_IP4TXFRAGS = 6,
0129 IRDMA_HW_STAT_INDEX_IP4TXMCPKTS = 7,
0130 IRDMA_HW_STAT_INDEX_IP6RXOCTS = 8,
0131 IRDMA_HW_STAT_INDEX_IP6RXPKTS = 9,
0132 IRDMA_HW_STAT_INDEX_IP6RXFRAGS = 10,
0133 IRDMA_HW_STAT_INDEX_IP6RXMCPKTS = 11,
0134 IRDMA_HW_STAT_INDEX_IP6TXOCTS = 12,
0135 IRDMA_HW_STAT_INDEX_IP6TXPKTS = 13,
0136 IRDMA_HW_STAT_INDEX_IP6TXFRAGS = 14,
0137 IRDMA_HW_STAT_INDEX_IP6TXMCPKTS = 15,
0138 IRDMA_HW_STAT_INDEX_TCPRXSEGS = 16,
0139 IRDMA_HW_STAT_INDEX_TCPTXSEG = 17,
0140 IRDMA_HW_STAT_INDEX_RDMARXRDS = 18,
0141 IRDMA_HW_STAT_INDEX_RDMARXSNDS = 19,
0142 IRDMA_HW_STAT_INDEX_RDMARXWRS = 20,
0143 IRDMA_HW_STAT_INDEX_RDMATXRDS = 21,
0144 IRDMA_HW_STAT_INDEX_RDMATXSNDS = 22,
0145 IRDMA_HW_STAT_INDEX_RDMATXWRS = 23,
0146 IRDMA_HW_STAT_INDEX_RDMAVBND = 24,
0147 IRDMA_HW_STAT_INDEX_RDMAVINV = 25,
0148 IRDMA_HW_STAT_INDEX_MAX_64_GEN_1 = 26,
0149 IRDMA_HW_STAT_INDEX_IP4RXMCOCTS = 26,
0150 IRDMA_HW_STAT_INDEX_IP4TXMCOCTS = 27,
0151 IRDMA_HW_STAT_INDEX_IP6RXMCOCTS = 28,
0152 IRDMA_HW_STAT_INDEX_IP6TXMCOCTS = 29,
0153 IRDMA_HW_STAT_INDEX_UDPRXPKTS = 30,
0154 IRDMA_HW_STAT_INDEX_UDPTXPKTS = 31,
0155 IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS = 32,
0156 IRDMA_HW_STAT_INDEX_MAX_64,
0157 };
0158
0159 enum irdma_feature_type {
0160 IRDMA_FEATURE_FW_INFO = 0,
0161 IRDMA_HW_VERSION_INFO = 1,
0162 IRDMA_QSETS_MAX = 26,
0163 IRDMA_MAX_FEATURES,
0164 };
0165
0166 enum irdma_sched_prio_type {
0167 IRDMA_PRIO_WEIGHTED_RR = 1,
0168 IRDMA_PRIO_STRICT = 2,
0169 IRDMA_PRIO_WEIGHTED_STRICT = 3,
0170 };
0171
0172 enum irdma_vm_vf_type {
0173 IRDMA_VF_TYPE = 0,
0174 IRDMA_VM_TYPE,
0175 IRDMA_PF_TYPE,
0176 };
0177
0178 enum irdma_cqp_hmc_profile {
0179 IRDMA_HMC_PROFILE_DEFAULT = 1,
0180 IRDMA_HMC_PROFILE_FAVOR_VF = 2,
0181 IRDMA_HMC_PROFILE_EQUAL = 3,
0182 };
0183
0184 enum irdma_quad_entry_type {
0185 IRDMA_QHASH_TYPE_TCP_ESTABLISHED = 1,
0186 IRDMA_QHASH_TYPE_TCP_SYN,
0187 IRDMA_QHASH_TYPE_UDP_UNICAST,
0188 IRDMA_QHASH_TYPE_UDP_MCAST,
0189 IRDMA_QHASH_TYPE_ROCE_MCAST,
0190 IRDMA_QHASH_TYPE_ROCEV2_HW,
0191 };
0192
0193 enum irdma_quad_hash_manage_type {
0194 IRDMA_QHASH_MANAGE_TYPE_DELETE = 0,
0195 IRDMA_QHASH_MANAGE_TYPE_ADD,
0196 IRDMA_QHASH_MANAGE_TYPE_MODIFY,
0197 };
0198
0199 enum irdma_syn_rst_handling {
0200 IRDMA_SYN_RST_HANDLING_HW_TCP_SECURE = 0,
0201 IRDMA_SYN_RST_HANDLING_HW_TCP,
0202 IRDMA_SYN_RST_HANDLING_FW_TCP_SECURE,
0203 IRDMA_SYN_RST_HANDLING_FW_TCP,
0204 };
0205
0206 enum irdma_queue_type {
0207 IRDMA_QUEUE_TYPE_SQ_RQ = 0,
0208 IRDMA_QUEUE_TYPE_CQP,
0209 };
0210
0211 struct irdma_sc_dev;
0212 struct irdma_vsi_pestat;
0213
0214 struct irdma_dcqcn_cc_params {
0215 u8 cc_cfg_valid;
0216 u8 min_dec_factor;
0217 u8 min_rate;
0218 u8 dcqcn_f;
0219 u16 rai_factor;
0220 u16 hai_factor;
0221 u16 dcqcn_t;
0222 u32 dcqcn_b;
0223 u32 rreduce_mperiod;
0224 };
0225
0226 struct irdma_cqp_init_info {
0227 u64 cqp_compl_ctx;
0228 u64 host_ctx_pa;
0229 u64 sq_pa;
0230 struct irdma_sc_dev *dev;
0231 struct irdma_cqp_quanta *sq;
0232 struct irdma_dcqcn_cc_params dcqcn_params;
0233 __le64 *host_ctx;
0234 u64 *scratch_array;
0235 u32 sq_size;
0236 u16 hw_maj_ver;
0237 u16 hw_min_ver;
0238 u8 struct_ver;
0239 u8 hmc_profile;
0240 u8 ena_vf_count;
0241 u8 ceqs_per_vf;
0242 bool en_datacenter_tcp:1;
0243 bool disable_packed:1;
0244 bool rocev2_rto_policy:1;
0245 enum irdma_protocol_used protocol_used;
0246 };
0247
0248 struct irdma_terminate_hdr {
0249 u8 layer_etype;
0250 u8 error_code;
0251 u8 hdrct;
0252 u8 rsvd;
0253 };
0254
0255 struct irdma_cqp_sq_wqe {
0256 __le64 buf[IRDMA_CQP_WQE_SIZE];
0257 };
0258
0259 struct irdma_sc_aeqe {
0260 __le64 buf[IRDMA_AEQE_SIZE];
0261 };
0262
0263 struct irdma_ceqe {
0264 __le64 buf[IRDMA_CEQE_SIZE];
0265 };
0266
0267 struct irdma_cqp_ctx {
0268 __le64 buf[IRDMA_CQP_CTX_SIZE];
0269 };
0270
0271 struct irdma_cq_shadow_area {
0272 __le64 buf[IRDMA_SHADOW_AREA_SIZE];
0273 };
0274
0275 struct irdma_dev_hw_stats_offsets {
0276 u32 stats_offset_32[IRDMA_HW_STAT_INDEX_MAX_32];
0277 u32 stats_offset_64[IRDMA_HW_STAT_INDEX_MAX_64];
0278 };
0279
0280 struct irdma_dev_hw_stats {
0281 u64 stats_val_32[IRDMA_HW_STAT_INDEX_MAX_32];
0282 u64 stats_val_64[IRDMA_HW_STAT_INDEX_MAX_64];
0283 };
0284
0285 struct irdma_gather_stats {
0286 u32 rsvd1;
0287 u32 rxvlanerr;
0288 u64 ip4rxocts;
0289 u64 ip4rxpkts;
0290 u32 ip4rxtrunc;
0291 u32 ip4rxdiscard;
0292 u64 ip4rxfrags;
0293 u64 ip4rxmcocts;
0294 u64 ip4rxmcpkts;
0295 u64 ip6rxocts;
0296 u64 ip6rxpkts;
0297 u32 ip6rxtrunc;
0298 u32 ip6rxdiscard;
0299 u64 ip6rxfrags;
0300 u64 ip6rxmcocts;
0301 u64 ip6rxmcpkts;
0302 u64 ip4txocts;
0303 u64 ip4txpkts;
0304 u64 ip4txfrag;
0305 u64 ip4txmcocts;
0306 u64 ip4txmcpkts;
0307 u64 ip6txocts;
0308 u64 ip6txpkts;
0309 u64 ip6txfrags;
0310 u64 ip6txmcocts;
0311 u64 ip6txmcpkts;
0312 u32 ip6txnoroute;
0313 u32 ip4txnoroute;
0314 u64 tcprxsegs;
0315 u32 tcprxprotoerr;
0316 u32 tcprxopterr;
0317 u64 tcptxsegs;
0318 u32 rsvd2;
0319 u32 tcprtxseg;
0320 u64 udprxpkts;
0321 u64 udptxpkts;
0322 u64 rdmarxwrs;
0323 u64 rdmarxrds;
0324 u64 rdmarxsnds;
0325 u64 rdmatxwrs;
0326 u64 rdmatxrds;
0327 u64 rdmatxsnds;
0328 u64 rdmavbn;
0329 u64 rdmavinv;
0330 u64 rxnpecnmrkpkts;
0331 u32 rxrpcnphandled;
0332 u32 rxrpcnpignored;
0333 u32 txnpcnpsent;
0334 u32 rsvd3[88];
0335 };
0336
0337 struct irdma_stats_gather_info {
0338 bool use_hmc_fcn_index:1;
0339 bool use_stats_inst:1;
0340 u8 hmc_fcn_index;
0341 u8 stats_inst_index;
0342 struct irdma_dma_mem stats_buff_mem;
0343 void *gather_stats_va;
0344 void *last_gather_stats_va;
0345 };
0346
0347 struct irdma_vsi_pestat {
0348 struct irdma_hw *hw;
0349 struct irdma_dev_hw_stats hw_stats;
0350 struct irdma_stats_gather_info gather_info;
0351 struct timer_list stats_timer;
0352 struct irdma_sc_vsi *vsi;
0353 struct irdma_dev_hw_stats last_hw_stats;
0354 spinlock_t lock;
0355 };
0356
0357 struct irdma_hw {
0358 u8 __iomem *hw_addr;
0359 u8 __iomem *priv_hw_addr;
0360 struct device *device;
0361 struct irdma_hmc_info hmc;
0362 };
0363
0364 struct irdma_pfpdu {
0365 struct list_head rxlist;
0366 u32 rcv_nxt;
0367 u32 fps;
0368 u32 max_fpdu_data;
0369 u32 nextseqnum;
0370 u32 rcv_start_seq;
0371 bool mode:1;
0372 bool mpa_crc_err:1;
0373 u8 marker_len;
0374 u64 total_ieq_bufs;
0375 u64 fpdu_processed;
0376 u64 bad_seq_num;
0377 u64 crc_err;
0378 u64 no_tx_bufs;
0379 u64 tx_err;
0380 u64 out_of_order;
0381 u64 pmode_count;
0382 struct irdma_sc_ah *ah;
0383 struct irdma_puda_buf *ah_buf;
0384 spinlock_t lock;
0385 struct irdma_puda_buf *lastrcv_buf;
0386 };
0387
0388 struct irdma_sc_pd {
0389 struct irdma_sc_dev *dev;
0390 u32 pd_id;
0391 int abi_ver;
0392 };
0393
0394 struct irdma_cqp_quanta {
0395 __le64 elem[IRDMA_CQP_WQE_SIZE];
0396 };
0397
0398 struct irdma_sc_cqp {
0399 u32 size;
0400 u64 sq_pa;
0401 u64 host_ctx_pa;
0402 void *back_cqp;
0403 struct irdma_sc_dev *dev;
0404 int (*process_cqp_sds)(struct irdma_sc_dev *dev,
0405 struct irdma_update_sds_info *info);
0406 struct irdma_dma_mem sdbuf;
0407 struct irdma_ring sq_ring;
0408 struct irdma_cqp_quanta *sq_base;
0409 struct irdma_dcqcn_cc_params dcqcn_params;
0410 __le64 *host_ctx;
0411 u64 *scratch_array;
0412 u32 cqp_id;
0413 u32 sq_size;
0414 u32 hw_sq_size;
0415 u16 hw_maj_ver;
0416 u16 hw_min_ver;
0417 u8 struct_ver;
0418 u8 polarity;
0419 u8 hmc_profile;
0420 u8 ena_vf_count;
0421 u8 timeout_count;
0422 u8 ceqs_per_vf;
0423 bool en_datacenter_tcp:1;
0424 bool disable_packed:1;
0425 bool rocev2_rto_policy:1;
0426 enum irdma_protocol_used protocol_used;
0427 };
0428
0429 struct irdma_sc_aeq {
0430 u32 size;
0431 u64 aeq_elem_pa;
0432 struct irdma_sc_dev *dev;
0433 struct irdma_sc_aeqe *aeqe_base;
0434 void *pbl_list;
0435 u32 elem_cnt;
0436 struct irdma_ring aeq_ring;
0437 u8 pbl_chunk_size;
0438 u32 first_pm_pbl_idx;
0439 u32 msix_idx;
0440 u8 polarity;
0441 bool virtual_map:1;
0442 };
0443
0444 struct irdma_sc_ceq {
0445 u32 size;
0446 u64 ceq_elem_pa;
0447 struct irdma_sc_dev *dev;
0448 struct irdma_ceqe *ceqe_base;
0449 void *pbl_list;
0450 u32 ceq_id;
0451 u32 elem_cnt;
0452 struct irdma_ring ceq_ring;
0453 u8 pbl_chunk_size;
0454 u8 tph_val;
0455 u32 first_pm_pbl_idx;
0456 u8 polarity;
0457 struct irdma_sc_vsi *vsi;
0458 struct irdma_sc_cq **reg_cq;
0459 u32 reg_cq_size;
0460 spinlock_t req_cq_lock;
0461 bool virtual_map:1;
0462 bool tph_en:1;
0463 bool itr_no_expire:1;
0464 };
0465
0466 struct irdma_sc_cq {
0467 struct irdma_cq_uk cq_uk;
0468 u64 cq_pa;
0469 u64 shadow_area_pa;
0470 struct irdma_sc_dev *dev;
0471 struct irdma_sc_vsi *vsi;
0472 void *pbl_list;
0473 void *back_cq;
0474 u32 ceq_id;
0475 u32 shadow_read_threshold;
0476 u8 pbl_chunk_size;
0477 u8 cq_type;
0478 u8 tph_val;
0479 u32 first_pm_pbl_idx;
0480 bool ceqe_mask:1;
0481 bool virtual_map:1;
0482 bool check_overflow:1;
0483 bool ceq_id_valid:1;
0484 bool tph_en;
0485 };
0486
0487 struct irdma_sc_qp {
0488 struct irdma_qp_uk qp_uk;
0489 u64 sq_pa;
0490 u64 rq_pa;
0491 u64 hw_host_ctx_pa;
0492 u64 shadow_area_pa;
0493 u64 q2_pa;
0494 struct irdma_sc_dev *dev;
0495 struct irdma_sc_vsi *vsi;
0496 struct irdma_sc_pd *pd;
0497 __le64 *hw_host_ctx;
0498 void *llp_stream_handle;
0499 struct irdma_pfpdu pfpdu;
0500 u32 ieq_qp;
0501 u8 *q2_buf;
0502 u64 qp_compl_ctx;
0503 u32 push_idx;
0504 u16 qs_handle;
0505 u16 push_offset;
0506 u8 flush_wqes_count;
0507 u8 sq_tph_val;
0508 u8 rq_tph_val;
0509 u8 qp_state;
0510 u8 hw_sq_size;
0511 u8 hw_rq_size;
0512 u8 src_mac_addr_idx;
0513 bool on_qoslist:1;
0514 bool ieq_pass_thru:1;
0515 bool sq_tph_en:1;
0516 bool rq_tph_en:1;
0517 bool rcv_tph_en:1;
0518 bool xmit_tph_en:1;
0519 bool virtual_map:1;
0520 bool flush_sq:1;
0521 bool flush_rq:1;
0522 bool sq_flush_code:1;
0523 bool rq_flush_code:1;
0524 enum irdma_flush_opcode flush_code;
0525 enum irdma_qp_event_type event_type;
0526 u8 term_flags;
0527 u8 user_pri;
0528 struct list_head list;
0529 };
0530
0531 struct irdma_stats_inst_info {
0532 bool use_hmc_fcn_index;
0533 u8 hmc_fn_id;
0534 u8 stats_idx;
0535 };
0536
0537 struct irdma_up_info {
0538 u8 map[8];
0539 u8 cnp_up_override;
0540 u8 hmc_fcn_idx;
0541 bool use_vlan:1;
0542 bool use_cnp_up_override:1;
0543 };
0544
0545 #define IRDMA_MAX_WS_NODES 0x3FF
0546 #define IRDMA_WS_NODE_INVALID 0xFFFF
0547
0548 struct irdma_ws_node_info {
0549 u16 id;
0550 u16 vsi;
0551 u16 parent_id;
0552 u16 qs_handle;
0553 bool type_leaf:1;
0554 bool enable:1;
0555 u8 prio_type;
0556 u8 tc;
0557 u8 weight;
0558 };
0559
0560 struct irdma_hmc_fpm_misc {
0561 u32 max_ceqs;
0562 u32 max_sds;
0563 u32 xf_block_size;
0564 u32 q1_block_size;
0565 u32 ht_multiplier;
0566 u32 timer_bucket;
0567 u32 rrf_block_size;
0568 u32 ooiscf_block_size;
0569 };
0570
0571 #define IRDMA_LEAF_DEFAULT_REL_BW 64
0572 #define IRDMA_PARENT_DEFAULT_REL_BW 1
0573
0574 struct irdma_qos {
0575 struct list_head qplist;
0576 struct mutex qos_mutex;
0577 u64 lan_qos_handle;
0578 u32 l2_sched_node_id;
0579 u16 qs_handle;
0580 u8 traffic_class;
0581 u8 rel_bw;
0582 u8 prio_type;
0583 bool valid;
0584 };
0585
0586 #define IRDMA_INVALID_FCN_ID 0xff
0587 struct irdma_sc_vsi {
0588 u16 vsi_idx;
0589 struct irdma_sc_dev *dev;
0590 void *back_vsi;
0591 u32 ilq_count;
0592 struct irdma_virt_mem ilq_mem;
0593 struct irdma_puda_rsrc *ilq;
0594 u32 ieq_count;
0595 struct irdma_virt_mem ieq_mem;
0596 struct irdma_puda_rsrc *ieq;
0597 u32 exception_lan_q;
0598 u16 mtu;
0599 u16 vm_id;
0600 u8 fcn_id;
0601 enum irdma_vm_vf_type vm_vf_type;
0602 bool stats_fcn_id_alloc:1;
0603 bool tc_change_pending:1;
0604 struct irdma_qos qos[IRDMA_MAX_USER_PRIORITY];
0605 struct irdma_vsi_pestat *pestat;
0606 atomic_t qp_suspend_reqs;
0607 int (*register_qset)(struct irdma_sc_vsi *vsi,
0608 struct irdma_ws_node *tc_node);
0609 void (*unregister_qset)(struct irdma_sc_vsi *vsi,
0610 struct irdma_ws_node *tc_node);
0611 u8 qos_rel_bw;
0612 u8 qos_prio_type;
0613 u8 dscp_map[IIDC_MAX_DSCP_MAPPING];
0614 bool dscp_mode:1;
0615 };
0616
0617 struct irdma_sc_dev {
0618 struct list_head cqp_cmd_head;
0619 spinlock_t cqp_lock;
0620 bool fcn_id_array[IRDMA_MAX_STATS_COUNT];
0621 struct irdma_dma_mem vf_fpm_query_buf[IRDMA_MAX_PE_ENA_VF_COUNT];
0622 u64 fpm_query_buf_pa;
0623 u64 fpm_commit_buf_pa;
0624 __le64 *fpm_query_buf;
0625 __le64 *fpm_commit_buf;
0626 struct irdma_hw *hw;
0627 u8 __iomem *db_addr;
0628 u32 __iomem *wqe_alloc_db;
0629 u32 __iomem *cq_arm_db;
0630 u32 __iomem *aeq_alloc_db;
0631 u32 __iomem *cqp_db;
0632 u32 __iomem *cq_ack_db;
0633 u32 __iomem *ceq_itr_mask_db;
0634 u32 __iomem *aeq_itr_mask_db;
0635 u32 __iomem *hw_regs[IRDMA_MAX_REGS];
0636 u32 ceq_itr;
0637 u64 hw_masks[IRDMA_MAX_MASKS];
0638 u64 hw_shifts[IRDMA_MAX_SHIFTS];
0639 u64 hw_stats_regs_32[IRDMA_HW_STAT_INDEX_MAX_32];
0640 u64 hw_stats_regs_64[IRDMA_HW_STAT_INDEX_MAX_64];
0641 u64 feature_info[IRDMA_MAX_FEATURES];
0642 u64 cqp_cmd_stats[IRDMA_MAX_CQP_OPS];
0643 struct irdma_hw_attrs hw_attrs;
0644 struct irdma_hmc_info *hmc_info;
0645 struct irdma_sc_cqp *cqp;
0646 struct irdma_sc_aeq *aeq;
0647 struct irdma_sc_ceq *ceq[IRDMA_CEQ_MAX_COUNT];
0648 struct irdma_sc_cq *ccq;
0649 const struct irdma_irq_ops *irq_ops;
0650 struct irdma_hmc_fpm_misc hmc_fpm_misc;
0651 struct irdma_ws_node *ws_tree_root;
0652 struct mutex ws_mutex;
0653 u16 num_vfs;
0654 u8 hmc_fn_id;
0655 u8 vf_id;
0656 bool vchnl_up:1;
0657 bool ceq_valid:1;
0658 u8 pci_rev;
0659 int (*ws_add)(struct irdma_sc_vsi *vsi, u8 user_pri);
0660 void (*ws_remove)(struct irdma_sc_vsi *vsi, u8 user_pri);
0661 void (*ws_reset)(struct irdma_sc_vsi *vsi);
0662 };
0663
0664 struct irdma_modify_cq_info {
0665 u64 cq_pa;
0666 struct irdma_cqe *cq_base;
0667 u32 cq_size;
0668 u32 shadow_read_threshold;
0669 u8 pbl_chunk_size;
0670 u32 first_pm_pbl_idx;
0671 bool virtual_map:1;
0672 bool check_overflow;
0673 bool cq_resize:1;
0674 };
0675
0676 struct irdma_create_qp_info {
0677 bool ord_valid:1;
0678 bool tcp_ctx_valid:1;
0679 bool cq_num_valid:1;
0680 bool arp_cache_idx_valid:1;
0681 bool mac_valid:1;
0682 bool force_lpb;
0683 u8 next_iwarp_state;
0684 };
0685
0686 struct irdma_modify_qp_info {
0687 u64 rx_win0;
0688 u64 rx_win1;
0689 u16 new_mss;
0690 u8 next_iwarp_state;
0691 u8 curr_iwarp_state;
0692 u8 termlen;
0693 bool ord_valid:1;
0694 bool tcp_ctx_valid:1;
0695 bool udp_ctx_valid:1;
0696 bool cq_num_valid:1;
0697 bool arp_cache_idx_valid:1;
0698 bool reset_tcp_conn:1;
0699 bool remove_hash_idx:1;
0700 bool dont_send_term:1;
0701 bool dont_send_fin:1;
0702 bool cached_var_valid:1;
0703 bool mss_change:1;
0704 bool force_lpb:1;
0705 bool mac_valid:1;
0706 };
0707
0708 struct irdma_ccq_cqe_info {
0709 struct irdma_sc_cqp *cqp;
0710 u64 scratch;
0711 u32 op_ret_val;
0712 u16 maj_err_code;
0713 u16 min_err_code;
0714 u8 op_code;
0715 bool error;
0716 };
0717
0718 struct irdma_dcb_app_info {
0719 u8 priority;
0720 u8 selector;
0721 u16 prot_id;
0722 };
0723
0724 struct irdma_qos_tc_info {
0725 u64 tc_ctx;
0726 u8 rel_bw;
0727 u8 prio_type;
0728 u8 egress_virt_up;
0729 u8 ingress_virt_up;
0730 };
0731
0732 struct irdma_l2params {
0733 struct irdma_qos_tc_info tc_info[IRDMA_MAX_USER_PRIORITY];
0734 struct irdma_dcb_app_info apps[IRDMA_MAX_APPS];
0735 u32 num_apps;
0736 u16 qs_handle_list[IRDMA_MAX_USER_PRIORITY];
0737 u16 mtu;
0738 u8 up2tc[IRDMA_MAX_USER_PRIORITY];
0739 u8 dscp_map[IIDC_MAX_DSCP_MAPPING];
0740 u8 num_tc;
0741 u8 vsi_rel_bw;
0742 u8 vsi_prio_type;
0743 bool mtu_changed:1;
0744 bool tc_changed:1;
0745 bool dscp_mode:1;
0746 };
0747
0748 struct irdma_vsi_init_info {
0749 struct irdma_sc_dev *dev;
0750 void *back_vsi;
0751 struct irdma_l2params *params;
0752 u16 exception_lan_q;
0753 u16 pf_data_vsi_num;
0754 enum irdma_vm_vf_type vm_vf_type;
0755 u16 vm_id;
0756 int (*register_qset)(struct irdma_sc_vsi *vsi,
0757 struct irdma_ws_node *tc_node);
0758 void (*unregister_qset)(struct irdma_sc_vsi *vsi,
0759 struct irdma_ws_node *tc_node);
0760 };
0761
0762 struct irdma_vsi_stats_info {
0763 struct irdma_vsi_pestat *pestat;
0764 u8 fcn_id;
0765 bool alloc_fcn_id;
0766 };
0767
0768 struct irdma_device_init_info {
0769 u64 fpm_query_buf_pa;
0770 u64 fpm_commit_buf_pa;
0771 __le64 *fpm_query_buf;
0772 __le64 *fpm_commit_buf;
0773 struct irdma_hw *hw;
0774 void __iomem *bar0;
0775 u8 hmc_fn_id;
0776 };
0777
0778 struct irdma_ceq_init_info {
0779 u64 ceqe_pa;
0780 struct irdma_sc_dev *dev;
0781 u64 *ceqe_base;
0782 void *pbl_list;
0783 u32 elem_cnt;
0784 u32 ceq_id;
0785 bool virtual_map:1;
0786 bool tph_en:1;
0787 bool itr_no_expire:1;
0788 u8 pbl_chunk_size;
0789 u8 tph_val;
0790 u32 first_pm_pbl_idx;
0791 struct irdma_sc_vsi *vsi;
0792 struct irdma_sc_cq **reg_cq;
0793 u32 reg_cq_idx;
0794 };
0795
0796 struct irdma_aeq_init_info {
0797 u64 aeq_elem_pa;
0798 struct irdma_sc_dev *dev;
0799 u32 *aeqe_base;
0800 void *pbl_list;
0801 u32 elem_cnt;
0802 bool virtual_map;
0803 u8 pbl_chunk_size;
0804 u32 first_pm_pbl_idx;
0805 u32 msix_idx;
0806 };
0807
0808 struct irdma_ccq_init_info {
0809 u64 cq_pa;
0810 u64 shadow_area_pa;
0811 struct irdma_sc_dev *dev;
0812 struct irdma_cqe *cq_base;
0813 __le64 *shadow_area;
0814 void *pbl_list;
0815 u32 num_elem;
0816 u32 ceq_id;
0817 u32 shadow_read_threshold;
0818 bool ceqe_mask:1;
0819 bool ceq_id_valid:1;
0820 bool avoid_mem_cflct:1;
0821 bool virtual_map:1;
0822 bool tph_en:1;
0823 u8 tph_val;
0824 u8 pbl_chunk_size;
0825 u32 first_pm_pbl_idx;
0826 struct irdma_sc_vsi *vsi;
0827 };
0828
0829 struct irdma_udp_offload_info {
0830 bool ipv4:1;
0831 bool insert_vlan_tag:1;
0832 u8 ttl;
0833 u8 tos;
0834 u16 src_port;
0835 u16 dst_port;
0836 u32 dest_ip_addr[4];
0837 u32 snd_mss;
0838 u16 vlan_tag;
0839 u16 arp_idx;
0840 u32 flow_label;
0841 u8 udp_state;
0842 u32 psn_nxt;
0843 u32 lsn;
0844 u32 epsn;
0845 u32 psn_max;
0846 u32 psn_una;
0847 u32 local_ipaddr[4];
0848 u32 cwnd;
0849 u8 rexmit_thresh;
0850 u8 rnr_nak_thresh;
0851 };
0852
0853 struct irdma_roce_offload_info {
0854 u16 p_key;
0855 u16 err_rq_idx;
0856 u32 qkey;
0857 u32 dest_qp;
0858 u8 roce_tver;
0859 u8 ack_credits;
0860 u8 err_rq_idx_valid;
0861 u32 pd_id;
0862 u16 ord_size;
0863 u16 ird_size;
0864 bool is_qp1:1;
0865 bool udprivcq_en:1;
0866 bool dcqcn_en:1;
0867 bool rcv_no_icrc:1;
0868 bool wr_rdresp_en:1;
0869 bool bind_en:1;
0870 bool fast_reg_en:1;
0871 bool priv_mode_en:1;
0872 bool rd_en:1;
0873 bool timely_en:1;
0874 bool dctcp_en:1;
0875 bool fw_cc_enable:1;
0876 bool use_stats_inst:1;
0877 u16 t_high;
0878 u16 t_low;
0879 u8 last_byte_sent;
0880 u8 mac_addr[ETH_ALEN];
0881 u8 rtomin;
0882 };
0883
0884 struct irdma_iwarp_offload_info {
0885 u16 rcv_mark_offset;
0886 u16 snd_mark_offset;
0887 u8 ddp_ver;
0888 u8 rdmap_ver;
0889 u8 iwarp_mode;
0890 u16 err_rq_idx;
0891 u32 pd_id;
0892 u16 ord_size;
0893 u16 ird_size;
0894 bool ib_rd_en:1;
0895 bool align_hdrs:1;
0896 bool rcv_no_mpa_crc:1;
0897 bool err_rq_idx_valid:1;
0898 bool snd_mark_en:1;
0899 bool rcv_mark_en:1;
0900 bool wr_rdresp_en:1;
0901 bool bind_en:1;
0902 bool fast_reg_en:1;
0903 bool priv_mode_en:1;
0904 bool rd_en:1;
0905 bool timely_en:1;
0906 bool use_stats_inst:1;
0907 bool ecn_en:1;
0908 bool dctcp_en:1;
0909 u16 t_high;
0910 u16 t_low;
0911 u8 last_byte_sent;
0912 u8 mac_addr[ETH_ALEN];
0913 u8 rtomin;
0914 };
0915
0916 struct irdma_tcp_offload_info {
0917 bool ipv4:1;
0918 bool no_nagle:1;
0919 bool insert_vlan_tag:1;
0920 bool time_stamp:1;
0921 bool drop_ooo_seg:1;
0922 bool avoid_stretch_ack:1;
0923 bool wscale:1;
0924 bool ignore_tcp_opt:1;
0925 bool ignore_tcp_uns_opt:1;
0926 u8 cwnd_inc_limit;
0927 u8 dup_ack_thresh;
0928 u8 ttl;
0929 u8 src_mac_addr_idx;
0930 u8 tos;
0931 u16 src_port;
0932 u16 dst_port;
0933 u32 dest_ip_addr[4];
0934
0935
0936
0937
0938 u32 snd_mss;
0939 u16 syn_rst_handling;
0940 u16 vlan_tag;
0941 u16 arp_idx;
0942 u32 flow_label;
0943 u8 tcp_state;
0944 u8 snd_wscale;
0945 u8 rcv_wscale;
0946 u32 time_stamp_recent;
0947 u32 time_stamp_age;
0948 u32 snd_nxt;
0949 u32 snd_wnd;
0950 u32 rcv_nxt;
0951 u32 rcv_wnd;
0952 u32 snd_max;
0953 u32 snd_una;
0954 u32 srtt;
0955 u32 rtt_var;
0956 u32 ss_thresh;
0957 u32 cwnd;
0958 u32 snd_wl1;
0959 u32 snd_wl2;
0960 u32 max_snd_window;
0961 u8 rexmit_thresh;
0962 u32 local_ipaddr[4];
0963 };
0964
0965 struct irdma_qp_host_ctx_info {
0966 u64 qp_compl_ctx;
0967 union {
0968 struct irdma_tcp_offload_info *tcp_info;
0969 struct irdma_udp_offload_info *udp_info;
0970 };
0971 union {
0972 struct irdma_iwarp_offload_info *iwarp_info;
0973 struct irdma_roce_offload_info *roce_info;
0974 };
0975 u32 send_cq_num;
0976 u32 rcv_cq_num;
0977 u32 rem_endpoint_idx;
0978 u8 stats_idx;
0979 bool srq_valid:1;
0980 bool tcp_info_valid:1;
0981 bool iwarp_info_valid:1;
0982 bool stats_idx_valid:1;
0983 u8 user_pri;
0984 };
0985
0986 struct irdma_aeqe_info {
0987 u64 compl_ctx;
0988 u32 qp_cq_id;
0989 u16 ae_id;
0990 u16 wqe_idx;
0991 u8 tcp_state;
0992 u8 iwarp_state;
0993 bool qp:1;
0994 bool cq:1;
0995 bool sq:1;
0996 bool rq:1;
0997 bool in_rdrsp_wr:1;
0998 bool out_rdrsp:1;
0999 bool aeqe_overflow:1;
1000 u8 q2_data_written;
1001 u8 ae_src;
1002 };
1003
1004 struct irdma_allocate_stag_info {
1005 u64 total_len;
1006 u64 first_pm_pbl_idx;
1007 u32 chunk_size;
1008 u32 stag_idx;
1009 u32 page_size;
1010 u32 pd_id;
1011 u16 access_rights;
1012 bool remote_access:1;
1013 bool use_hmc_fcn_index:1;
1014 bool use_pf_rid:1;
1015 u8 hmc_fcn_index;
1016 };
1017
1018 struct irdma_mw_alloc_info {
1019 u32 mw_stag_index;
1020 u32 page_size;
1021 u32 pd_id;
1022 bool remote_access:1;
1023 bool mw_wide:1;
1024 bool mw1_bind_dont_vldt_key:1;
1025 };
1026
1027 struct irdma_reg_ns_stag_info {
1028 u64 reg_addr_pa;
1029 u64 va;
1030 u64 total_len;
1031 u32 page_size;
1032 u32 chunk_size;
1033 u32 first_pm_pbl_index;
1034 enum irdma_addressing_type addr_type;
1035 irdma_stag_index stag_idx;
1036 u16 access_rights;
1037 u32 pd_id;
1038 irdma_stag_key stag_key;
1039 bool use_hmc_fcn_index:1;
1040 u8 hmc_fcn_index;
1041 bool use_pf_rid:1;
1042 };
1043
1044 struct irdma_fast_reg_stag_info {
1045 u64 wr_id;
1046 u64 reg_addr_pa;
1047 u64 fbo;
1048 void *va;
1049 u64 total_len;
1050 u32 page_size;
1051 u32 chunk_size;
1052 u32 first_pm_pbl_index;
1053 enum irdma_addressing_type addr_type;
1054 irdma_stag_index stag_idx;
1055 u16 access_rights;
1056 u32 pd_id;
1057 irdma_stag_key stag_key;
1058 bool local_fence:1;
1059 bool read_fence:1;
1060 bool signaled:1;
1061 bool push_wqe:1;
1062 bool use_hmc_fcn_index:1;
1063 u8 hmc_fcn_index;
1064 bool use_pf_rid:1;
1065 bool defer_flag:1;
1066 };
1067
1068 struct irdma_dealloc_stag_info {
1069 u32 stag_idx;
1070 u32 pd_id;
1071 bool mr:1;
1072 bool dealloc_pbl:1;
1073 };
1074
1075 struct irdma_register_shared_stag {
1076 u64 va;
1077 enum irdma_addressing_type addr_type;
1078 irdma_stag_index new_stag_idx;
1079 irdma_stag_index parent_stag_idx;
1080 u32 access_rights;
1081 u32 pd_id;
1082 u32 page_size;
1083 irdma_stag_key new_stag_key;
1084 };
1085
1086 struct irdma_qp_init_info {
1087 struct irdma_qp_uk_init_info qp_uk_init_info;
1088 struct irdma_sc_pd *pd;
1089 struct irdma_sc_vsi *vsi;
1090 __le64 *host_ctx;
1091 u8 *q2;
1092 u64 sq_pa;
1093 u64 rq_pa;
1094 u64 host_ctx_pa;
1095 u64 q2_pa;
1096 u64 shadow_area_pa;
1097 u8 sq_tph_val;
1098 u8 rq_tph_val;
1099 bool sq_tph_en:1;
1100 bool rq_tph_en:1;
1101 bool rcv_tph_en:1;
1102 bool xmit_tph_en:1;
1103 bool virtual_map:1;
1104 };
1105
1106 struct irdma_cq_init_info {
1107 struct irdma_sc_dev *dev;
1108 u64 cq_base_pa;
1109 u64 shadow_area_pa;
1110 u32 ceq_id;
1111 u32 shadow_read_threshold;
1112 u8 pbl_chunk_size;
1113 u32 first_pm_pbl_idx;
1114 bool virtual_map:1;
1115 bool ceqe_mask:1;
1116 bool ceq_id_valid:1;
1117 bool tph_en:1;
1118 u8 tph_val;
1119 u8 type;
1120 struct irdma_cq_uk_init_info cq_uk_init_info;
1121 struct irdma_sc_vsi *vsi;
1122 };
1123
1124 struct irdma_upload_context_info {
1125 u64 buf_pa;
1126 u32 qp_id;
1127 u8 qp_type;
1128 bool freeze_qp:1;
1129 bool raw_format:1;
1130 };
1131
1132 struct irdma_local_mac_entry_info {
1133 u8 mac_addr[6];
1134 u16 entry_idx;
1135 };
1136
1137 struct irdma_add_arp_cache_entry_info {
1138 u8 mac_addr[ETH_ALEN];
1139 u32 reach_max;
1140 u16 arp_index;
1141 bool permanent;
1142 };
1143
1144 struct irdma_apbvt_info {
1145 u16 port;
1146 bool add;
1147 };
1148
1149 struct irdma_qhash_table_info {
1150 struct irdma_sc_vsi *vsi;
1151 enum irdma_quad_hash_manage_type manage;
1152 enum irdma_quad_entry_type entry_type;
1153 bool vlan_valid:1;
1154 bool ipv4_valid:1;
1155 u8 mac_addr[ETH_ALEN];
1156 u16 vlan_id;
1157 u8 user_pri;
1158 u32 qp_num;
1159 u32 dest_ip[4];
1160 u32 src_ip[4];
1161 u16 dest_port;
1162 u16 src_port;
1163 };
1164
1165 struct irdma_cqp_manage_push_page_info {
1166 u32 push_idx;
1167 u16 qs_handle;
1168 u8 free_page;
1169 u8 push_page_type;
1170 };
1171
1172 struct irdma_qp_flush_info {
1173 u16 sq_minor_code;
1174 u16 sq_major_code;
1175 u16 rq_minor_code;
1176 u16 rq_major_code;
1177 u16 ae_code;
1178 u8 ae_src;
1179 bool sq:1;
1180 bool rq:1;
1181 bool userflushcode:1;
1182 bool generate_ae:1;
1183 };
1184
1185 struct irdma_gen_ae_info {
1186 u16 ae_code;
1187 u8 ae_src;
1188 };
1189
1190 struct irdma_cqp_timeout {
1191 u64 compl_cqp_cmds;
1192 u32 count;
1193 };
1194
1195 struct irdma_irq_ops {
1196 void (*irdma_cfg_aeq)(struct irdma_sc_dev *dev, u32 idx, bool enable);
1197 void (*irdma_cfg_ceq)(struct irdma_sc_dev *dev, u32 ceq_id, u32 idx,
1198 bool enable);
1199 void (*irdma_dis_irq)(struct irdma_sc_dev *dev, u32 idx);
1200 void (*irdma_en_irq)(struct irdma_sc_dev *dev, u32 idx);
1201 };
1202
1203 void irdma_sc_ccq_arm(struct irdma_sc_cq *ccq);
1204 int irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch,
1205 bool check_overflow, bool post_sq);
1206 int irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, bool post_sq);
1207 int irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq,
1208 struct irdma_ccq_cqe_info *info);
1209 int irdma_sc_ccq_init(struct irdma_sc_cq *ccq,
1210 struct irdma_ccq_init_info *info);
1211
1212 int irdma_sc_cceq_create(struct irdma_sc_ceq *ceq, u64 scratch);
1213 int irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq);
1214
1215 int irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, bool post_sq);
1216 int irdma_sc_ceq_init(struct irdma_sc_ceq *ceq,
1217 struct irdma_ceq_init_info *info);
1218 void irdma_sc_cleanup_ceqes(struct irdma_sc_cq *cq, struct irdma_sc_ceq *ceq);
1219 void *irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq);
1220
1221 int irdma_sc_aeq_init(struct irdma_sc_aeq *aeq,
1222 struct irdma_aeq_init_info *info);
1223 int irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq,
1224 struct irdma_aeqe_info *info);
1225 void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count);
1226
1227 void irdma_sc_pd_init(struct irdma_sc_dev *dev, struct irdma_sc_pd *pd, u32 pd_id,
1228 int abi_ver);
1229 void irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable);
1230 void irdma_check_cqp_progress(struct irdma_cqp_timeout *cqp_timeout,
1231 struct irdma_sc_dev *dev);
1232 int irdma_sc_cqp_create(struct irdma_sc_cqp *cqp, u16 *maj_err, u16 *min_err);
1233 int irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp);
1234 int irdma_sc_cqp_init(struct irdma_sc_cqp *cqp,
1235 struct irdma_cqp_init_info *info);
1236 void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp);
1237 int irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 opcode,
1238 struct irdma_ccq_cqe_info *cmpl_info);
1239 int irdma_sc_fast_register(struct irdma_sc_qp *qp,
1240 struct irdma_fast_reg_stag_info *info, bool post_sq);
1241 int irdma_sc_qp_create(struct irdma_sc_qp *qp,
1242 struct irdma_create_qp_info *info, u64 scratch,
1243 bool post_sq);
1244 int irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch,
1245 bool remove_hash_idx, bool ignore_mw_bnd, bool post_sq);
1246 int irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp,
1247 struct irdma_qp_flush_info *info, u64 scratch,
1248 bool post_sq);
1249 int irdma_sc_qp_init(struct irdma_sc_qp *qp, struct irdma_qp_init_info *info);
1250 int irdma_sc_qp_modify(struct irdma_sc_qp *qp,
1251 struct irdma_modify_qp_info *info, u64 scratch,
1252 bool post_sq);
1253 void irdma_sc_send_lsmm(struct irdma_sc_qp *qp, void *lsmm_buf, u32 size,
1254 irdma_stag stag);
1255
1256 void irdma_sc_send_rtt(struct irdma_sc_qp *qp, bool read);
1257 void irdma_sc_qp_setctx(struct irdma_sc_qp *qp, __le64 *qp_ctx,
1258 struct irdma_qp_host_ctx_info *info);
1259 void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx,
1260 struct irdma_qp_host_ctx_info *info);
1261 int irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, bool post_sq);
1262 int irdma_sc_cq_init(struct irdma_sc_cq *cq, struct irdma_cq_init_info *info);
1263 void irdma_sc_cq_resize(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info);
1264 int irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,
1265 u8 hmc_fn_id, bool post_sq,
1266 bool poll_registers);
1267
1268 void sc_vsi_update_stats(struct irdma_sc_vsi *vsi);
1269 struct cqp_info {
1270 union {
1271 struct {
1272 struct irdma_sc_qp *qp;
1273 struct irdma_create_qp_info info;
1274 u64 scratch;
1275 } qp_create;
1276
1277 struct {
1278 struct irdma_sc_qp *qp;
1279 struct irdma_modify_qp_info info;
1280 u64 scratch;
1281 } qp_modify;
1282
1283 struct {
1284 struct irdma_sc_qp *qp;
1285 u64 scratch;
1286 bool remove_hash_idx;
1287 bool ignore_mw_bnd;
1288 } qp_destroy;
1289
1290 struct {
1291 struct irdma_sc_cq *cq;
1292 u64 scratch;
1293 bool check_overflow;
1294 } cq_create;
1295
1296 struct {
1297 struct irdma_sc_cq *cq;
1298 struct irdma_modify_cq_info info;
1299 u64 scratch;
1300 } cq_modify;
1301
1302 struct {
1303 struct irdma_sc_cq *cq;
1304 u64 scratch;
1305 } cq_destroy;
1306
1307 struct {
1308 struct irdma_sc_dev *dev;
1309 struct irdma_allocate_stag_info info;
1310 u64 scratch;
1311 } alloc_stag;
1312
1313 struct {
1314 struct irdma_sc_dev *dev;
1315 struct irdma_mw_alloc_info info;
1316 u64 scratch;
1317 } mw_alloc;
1318
1319 struct {
1320 struct irdma_sc_dev *dev;
1321 struct irdma_reg_ns_stag_info info;
1322 u64 scratch;
1323 } mr_reg_non_shared;
1324
1325 struct {
1326 struct irdma_sc_dev *dev;
1327 struct irdma_dealloc_stag_info info;
1328 u64 scratch;
1329 } dealloc_stag;
1330
1331 struct {
1332 struct irdma_sc_cqp *cqp;
1333 struct irdma_add_arp_cache_entry_info info;
1334 u64 scratch;
1335 } add_arp_cache_entry;
1336
1337 struct {
1338 struct irdma_sc_cqp *cqp;
1339 u64 scratch;
1340 u16 arp_index;
1341 } del_arp_cache_entry;
1342
1343 struct {
1344 struct irdma_sc_cqp *cqp;
1345 struct irdma_local_mac_entry_info info;
1346 u64 scratch;
1347 } add_local_mac_entry;
1348
1349 struct {
1350 struct irdma_sc_cqp *cqp;
1351 u64 scratch;
1352 u8 entry_idx;
1353 u8 ignore_ref_count;
1354 } del_local_mac_entry;
1355
1356 struct {
1357 struct irdma_sc_cqp *cqp;
1358 u64 scratch;
1359 } alloc_local_mac_entry;
1360
1361 struct {
1362 struct irdma_sc_cqp *cqp;
1363 struct irdma_cqp_manage_push_page_info info;
1364 u64 scratch;
1365 } manage_push_page;
1366
1367 struct {
1368 struct irdma_sc_dev *dev;
1369 struct irdma_upload_context_info info;
1370 u64 scratch;
1371 } qp_upload_context;
1372
1373 struct {
1374 struct irdma_sc_dev *dev;
1375 struct irdma_hmc_fcn_info info;
1376 u64 scratch;
1377 } manage_hmc_pm;
1378
1379 struct {
1380 struct irdma_sc_ceq *ceq;
1381 u64 scratch;
1382 } ceq_create;
1383
1384 struct {
1385 struct irdma_sc_ceq *ceq;
1386 u64 scratch;
1387 } ceq_destroy;
1388
1389 struct {
1390 struct irdma_sc_aeq *aeq;
1391 u64 scratch;
1392 } aeq_create;
1393
1394 struct {
1395 struct irdma_sc_aeq *aeq;
1396 u64 scratch;
1397 } aeq_destroy;
1398
1399 struct {
1400 struct irdma_sc_qp *qp;
1401 struct irdma_qp_flush_info info;
1402 u64 scratch;
1403 } qp_flush_wqes;
1404
1405 struct {
1406 struct irdma_sc_qp *qp;
1407 struct irdma_gen_ae_info info;
1408 u64 scratch;
1409 } gen_ae;
1410
1411 struct {
1412 struct irdma_sc_cqp *cqp;
1413 void *fpm_val_va;
1414 u64 fpm_val_pa;
1415 u8 hmc_fn_id;
1416 u64 scratch;
1417 } query_fpm_val;
1418
1419 struct {
1420 struct irdma_sc_cqp *cqp;
1421 void *fpm_val_va;
1422 u64 fpm_val_pa;
1423 u8 hmc_fn_id;
1424 u64 scratch;
1425 } commit_fpm_val;
1426
1427 struct {
1428 struct irdma_sc_cqp *cqp;
1429 struct irdma_apbvt_info info;
1430 u64 scratch;
1431 } manage_apbvt_entry;
1432
1433 struct {
1434 struct irdma_sc_cqp *cqp;
1435 struct irdma_qhash_table_info info;
1436 u64 scratch;
1437 } manage_qhash_table_entry;
1438
1439 struct {
1440 struct irdma_sc_dev *dev;
1441 struct irdma_update_sds_info info;
1442 u64 scratch;
1443 } update_pe_sds;
1444
1445 struct {
1446 struct irdma_sc_cqp *cqp;
1447 struct irdma_sc_qp *qp;
1448 u64 scratch;
1449 } suspend_resume;
1450
1451 struct {
1452 struct irdma_sc_cqp *cqp;
1453 struct irdma_ah_info info;
1454 u64 scratch;
1455 } ah_create;
1456
1457 struct {
1458 struct irdma_sc_cqp *cqp;
1459 struct irdma_ah_info info;
1460 u64 scratch;
1461 } ah_destroy;
1462
1463 struct {
1464 struct irdma_sc_cqp *cqp;
1465 struct irdma_mcast_grp_info info;
1466 u64 scratch;
1467 } mc_create;
1468
1469 struct {
1470 struct irdma_sc_cqp *cqp;
1471 struct irdma_mcast_grp_info info;
1472 u64 scratch;
1473 } mc_destroy;
1474
1475 struct {
1476 struct irdma_sc_cqp *cqp;
1477 struct irdma_mcast_grp_info info;
1478 u64 scratch;
1479 } mc_modify;
1480
1481 struct {
1482 struct irdma_sc_cqp *cqp;
1483 struct irdma_stats_inst_info info;
1484 u64 scratch;
1485 } stats_manage;
1486
1487 struct {
1488 struct irdma_sc_cqp *cqp;
1489 struct irdma_stats_gather_info info;
1490 u64 scratch;
1491 } stats_gather;
1492
1493 struct {
1494 struct irdma_sc_cqp *cqp;
1495 struct irdma_ws_node_info info;
1496 u64 scratch;
1497 } ws_node;
1498
1499 struct {
1500 struct irdma_sc_cqp *cqp;
1501 struct irdma_up_info info;
1502 u64 scratch;
1503 } up_map;
1504
1505 struct {
1506 struct irdma_sc_cqp *cqp;
1507 struct irdma_dma_mem query_buff_mem;
1508 u64 scratch;
1509 } query_rdma;
1510 } u;
1511 };
1512
1513 struct cqp_cmds_info {
1514 struct list_head cqp_cmd_entry;
1515 u8 cqp_cmd;
1516 u8 post_sq;
1517 struct cqp_info in;
1518 };
1519
1520 __le64 *irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp *cqp, u64 scratch,
1521 u32 *wqe_idx);
1522
1523
1524
1525
1526
1527
1528 static inline __le64 *irdma_sc_cqp_get_next_send_wqe(struct irdma_sc_cqp *cqp, u64 scratch)
1529 {
1530 u32 wqe_idx;
1531
1532 return irdma_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx);
1533 }
1534 #endif
