hw/irdma/irdma.h

0001 /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */
0002 /* Copyright (c) 2017 - 2021 Intel Corporation */
0003 #ifndef IRDMA_H
0004 #define IRDMA_H
0005
0006 #define IRDMA_WQEALLOC_WQE_DESC_INDEX GENMASK(31, 20)
0007
0008 #define IRDMA_CQPTAIL_WQTAIL GENMASK(10, 0)
0009 #define IRDMA_CQPTAIL_CQP_OP_ERR BIT(31)
0010
0011 #define IRDMA_CQPERRCODES_CQP_MINOR_CODE GENMASK(15, 0)
0012 #define IRDMA_CQPERRCODES_CQP_MAJOR_CODE GENMASK(31, 16)
0013 #define IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE GENMASK(5, 4)
0014 #define IRDMA_GLINT_RATE_INTERVAL GENMASK(5, 0)
0015 #define IRDMA_GLINT_RATE_INTRL_ENA BIT(6)
0016 #define IRDMA_GLINT_DYN_CTL_INTENA BIT(0)
0017 #define IRDMA_GLINT_DYN_CTL_CLEARPBA BIT(1)
0018 #define IRDMA_GLINT_DYN_CTL_ITR_INDX GENMASK(4, 3)
0019 #define IRDMA_GLINT_DYN_CTL_INTERVAL GENMASK(16, 5)
0020 #define IRDMA_GLINT_CEQCTL_ITR_INDX GENMASK(12, 11)
0021 #define IRDMA_GLINT_CEQCTL_CAUSE_ENA BIT(30)
0022 #define IRDMA_GLINT_CEQCTL_MSIX_INDX GENMASK(10, 0)
0023 #define IRDMA_PFINT_AEQCTL_MSIX_INDX GENMASK(10, 0)
0024 #define IRDMA_PFINT_AEQCTL_ITR_INDX GENMASK(12, 11)
0025 #define IRDMA_PFINT_AEQCTL_CAUSE_ENA BIT(30)
0026 #define IRDMA_PFHMC_PDINV_PMSDIDX GENMASK(11, 0)
0027 #define IRDMA_PFHMC_PDINV_PMSDPARTSEL BIT(15)
0028 #define IRDMA_PFHMC_PDINV_PMPDIDX GENMASK(24, 16)
0029 #define IRDMA_PFHMC_SDDATALOW_PMSDVALID BIT(0)
0030 #define IRDMA_PFHMC_SDDATALOW_PMSDTYPE BIT(1)
0031 #define IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT GENMASK(11, 2)
0032 #define IRDMA_PFHMC_SDDATALOW_PMSDDATALOW GENMASK(31, 12)
0033 #define IRDMA_PFHMC_SDCMD_PMSDWR BIT(31)
0034
0035 #define IRDMA_INVALID_CQ_IDX            0xffffffff
0036 enum irdma_registers {
0037     IRDMA_CQPTAIL,
0038     IRDMA_CQPDB,
0039     IRDMA_CCQPSTATUS,
0040     IRDMA_CCQPHIGH,
0041     IRDMA_CCQPLOW,
0042     IRDMA_CQARM,
0043     IRDMA_CQACK,
0044     IRDMA_AEQALLOC,
0045     IRDMA_CQPERRCODES,
0046     IRDMA_WQEALLOC,
0047     IRDMA_GLINT_DYN_CTL,
0048     IRDMA_DB_ADDR_OFFSET,
0049     IRDMA_GLPCI_LBARCTRL,
0050     IRDMA_GLPE_CPUSTATUS0,
0051     IRDMA_GLPE_CPUSTATUS1,
0052     IRDMA_GLPE_CPUSTATUS2,
0053     IRDMA_PFINT_AEQCTL,
0054     IRDMA_GLINT_CEQCTL,
0055     IRDMA_VSIQF_PE_CTL1,
0056     IRDMA_PFHMC_PDINV,
0057     IRDMA_GLHMC_VFPDINV,
0058     IRDMA_GLPE_CRITERR,
0059     IRDMA_GLINT_RATE,
0060     IRDMA_MAX_REGS, /* Must be last entry */
0061 };
0062
0063 enum irdma_shifts {
0064     IRDMA_CCQPSTATUS_CCQP_DONE_S,
0065     IRDMA_CCQPSTATUS_CCQP_ERR_S,
0066     IRDMA_CQPSQ_STAG_PDID_S,
0067     IRDMA_CQPSQ_CQ_CEQID_S,
0068     IRDMA_CQPSQ_CQ_CQID_S,
0069     IRDMA_COMMIT_FPM_CQCNT_S,
0070     IRDMA_MAX_SHIFTS,
0071 };
0072
0073 enum irdma_masks {
0074     IRDMA_CCQPSTATUS_CCQP_DONE_M,
0075     IRDMA_CCQPSTATUS_CCQP_ERR_M,
0076     IRDMA_CQPSQ_STAG_PDID_M,
0077     IRDMA_CQPSQ_CQ_CEQID_M,
0078     IRDMA_CQPSQ_CQ_CQID_M,
0079     IRDMA_COMMIT_FPM_CQCNT_M,
0080     IRDMA_MAX_MASKS, /* Must be last entry */
0081 };
0082
0083 #define IRDMA_MAX_MGS_PER_CTX   8
0084
0085 struct irdma_mcast_grp_ctx_entry_info {
0086     u32 qp_id;
0087     bool valid_entry;
0088     u16 dest_port;
0089     u32 use_cnt;
0090 };
0091
0092 struct irdma_mcast_grp_info {
0093     u8 dest_mac_addr[ETH_ALEN];
0094     u16 vlan_id;
0095     u8 hmc_fcn_id;
0096     bool ipv4_valid:1;
0097     bool vlan_valid:1;
0098     u16 mg_id;
0099     u32 no_of_mgs;
0100     u32 dest_ip_addr[4];
0101     u16 qs_handle;
0102     struct irdma_dma_mem dma_mem_mc;
0103     struct irdma_mcast_grp_ctx_entry_info mg_ctx_info[IRDMA_MAX_MGS_PER_CTX];
0104 };
0105
0106 enum irdma_vers {
0107     IRDMA_GEN_RSVD,
0108     IRDMA_GEN_1,
0109     IRDMA_GEN_2,
0110 };
0111
0112 struct irdma_uk_attrs {
0113     u64 feature_flags;
0114     u32 max_hw_wq_frags;
0115     u32 max_hw_read_sges;
0116     u32 max_hw_inline;
0117     u32 max_hw_rq_quanta;
0118     u32 max_hw_wq_quanta;
0119     u32 min_hw_cq_size;
0120     u32 max_hw_cq_size;
0121     u16 max_hw_sq_chunk;
0122     u8 hw_rev;
0123 };
0124
0125 struct irdma_hw_attrs {
0126     struct irdma_uk_attrs uk_attrs;
0127     u64 max_hw_outbound_msg_size;
0128     u64 max_hw_inbound_msg_size;
0129     u64 max_mr_size;
0130     u64 page_size_cap;
0131     u32 min_hw_qp_id;
0132     u32 min_hw_aeq_size;
0133     u32 max_hw_aeq_size;
0134     u32 min_hw_ceq_size;
0135     u32 max_hw_ceq_size;
0136     u32 max_hw_device_pages;
0137     u32 max_hw_vf_fpm_id;
0138     u32 first_hw_vf_fpm_id;
0139     u32 max_hw_ird;
0140     u32 max_hw_ord;
0141     u32 max_hw_wqes;
0142     u32 max_hw_pds;
0143     u32 max_hw_ena_vf_count;
0144     u32 max_qp_wr;
0145     u32 max_pe_ready_count;
0146     u32 max_done_count;
0147     u32 max_sleep_count;
0148     u32 max_cqp_compl_wait_time_ms;
0149     u16 max_stat_inst;
0150 };
0151
0152 void i40iw_init_hw(struct irdma_sc_dev *dev);
0153 void icrdma_init_hw(struct irdma_sc_dev *dev);
0154 #endif /* IRDMA_H*/